From: AngeloGioacchino Del Regno
The Adreno 508/509/512 GPUs are stripped versions of the Adreno
5xx found in the mid-end SoCs such as SDM630, SDM636, SDM660 and
SDA variants; these SoCs are usually provided with ZAP firmwares,
but they have no available GPMU.
Signed-off-by: AngeloGioacchino
From: Konrad Dybcio
Port over the command from downstream to prevent undefined
behaviour.
Signed-off-by: Konrad Dybcio
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/adreno/a5xx.xml.h | 2 ++
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 3 +++
2 files changed, 5 insertions(+)
From: Konrad Dybcio
The upstream API for some reason uses logbase2 instead of
just passing the argument as-is, whereas downstream CAF
kernel does the latter.
Hence, a mistake has been made when porting:
4 is the value that's supposed to be passed, but
log2(4) = 2. Changing the value to 16 (=
From: AngeloGioacchino Del Regno
The "main" if branch where we program the other registers for the
Adreno 5xx family of GPUs should not contain the PC_DBG_ECO_CNTL
register programming because this has logical similarity
differences from all the others.
A later commit will show the entire sense
From: AngeloGioacchino Del Regno
Resetting the VBIF before power collapse is done to avoid getting
bogus FIFO entries during the suspend sequence or subsequent resume,
but this is doable only on Adreno 510 and Adreno 530, as the other
units will tendentially lock up.
Especially on Adreno 508,
From: Konrad Dybcio
Port over the command from downstream to prevent undefined
behaviour.
Signed-off-by: Konrad Dybcio
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
From: AngeloGioacchino Del Regno
The PC_DBG_ECO_CNTL register on the Adreno A5xx family gets
programmed to some different values on a per-model basis.
At least, this is what we intend to do here;
Unfortunately, though, this register is being overwritten with a
static magic number, right after
From: AngeloGioacchino Del Regno
In this patch series, we are adding support for lower end Adreno 5
series GPUs, such as A508, A509 and A512 that we have found in the
Qualcomm SDM630, SDM636 and SDM660 SoCs.
On a note, adding support for these three units, also adds 99% of
the required "things"
From: AngeloGioacchino Del Regno
In this patch series, we are adding support for lower end Adreno 5
series GPUs, such as A508, A509 and A512 that we have found in the
Qualcomm SDM630, SDM636 and SDM660 SoCs.
On a note, adding support for these three units, also adds 99% of
the required "things"
From: AngeloGioacchino Del Regno
Resetting the VBIF before power collapse is done to avoid getting
bogus FIFO entries during the suspend sequence or subsequent resume,
but this is doable only on Adreno 510 and Adreno 530, as the other
units will tendentially lock up.
Especially on Adreno 508,
From: AngeloGioacchino Del Regno
The PC_DBG_ECO_CNTL register on the Adreno A5xx family gets
programmed to some different values on a per-model basis.
At least, this is what we intend to do here;
Unfortunately, though, this register is being overwritten with a
static magic number, right after
From: Konrad Dybcio
Port over the command from downstream to prevent undefined
behaviour.
Signed-off-by: Konrad Dybcio
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
From: Konrad Dybcio
The upstream API for some reason uses logbase2 instead of
just passing the argument as-is, whereas downstream CAF
kernel does the latter.
Hence, a mistake has been made when porting:
4 is the value that's supposed to be passed, but
log2(4) = 2. Changing the value to 16 (=
From: AngeloGioacchino Del Regno
The "main" if branch where we program the other regsiters for the
Adreno 5xx family of GPUs should not contain the PC_DBG_ECO_CNTL
register programming because this has logical similarity
differences from all the others.
A later commit will show the entire sense
From: AngeloGioacchino Del Regno
The Adreno 508/509/512 GPUs are stripped versions of the Adreno
5xx found in the mid-end SoCs such as SDM630, SDM636, SDM660 and
SDA variants; these SoCs are usually provided with ZAP firmwares,
but they have no available GPMU.
Signed-off-by: AngeloGioacchino
From: Konrad Dybcio
Port over the command from downstream to prevent undefined
behaviour.
Signed-off-by: Konrad Dybcio
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
From: AngeloGioacchino Del Regno
These two clocks aren't present in all versions of the MDP5 HW:
where present, they are needed to enable the Translation Buffer
Unit(s).
Signed-off-by: AngeloGioacchino Del Regno
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/display/msm/mdp5.txt
From: AngeloGioacchino Del Regno
On family B SoCs, the 28nm PLL has a different iospace address
and that required a new compatible in the driver.
Signed-off-by: AngeloGioacchino Del Regno
---
Documentation/devicetree/bindings/display/msm/dsi.txt | 1 +
1 file changed, 1 insertion(+)
diff
From: AngeloGioacchino Del Regno
This patch series enables support for MSM8956/76 and its Adreno 510
GPU on the current DRM driver.
The personal aim is to upstream MSM8956 as much as possible.
This code has been tested on two Sony phones featuring the Qualcomm
MSM8956 SoC.
Changes in v2:
-
From: AngeloGioacchino Del Regno
The Adreno 510 GPU is a stripped version of the Adreno 5xx,
found in low-end SoCs like 8x56 and 8x76, which has 256K of
GMEM, with no GPMU nor ZAP.
Also, since the Adreno 5xx part of this driver seems to be
developed with high-end Adreno GPUs in mind, and since
From: AngeloGioacchino Del Regno
The 28nm PLL has a different iospace on MSM/APQ family B SoCs:
add a new configuration and use it when the DT reports the
"qcom,dsi-phy-28nm-hpm-fam-b" compatible.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
From: AngeloGioacchino Del Regno
MSM8976, MSM8976 and APQ variants have DSI version 3:10040002
(DSI 6G V1.4.2), featuring two DSIs.
They need three clocks (mdp_core, iface, bus), one GDSC and
two vregs, VDDA at 1.2V and VDDIO at 1.8V.
Signed-off-by: AngeloGioacchino Del Regno
---
From: AngeloGioacchino Del Regno
Add the configuration entries for the MDP5 v1.11, found on
MSM8956, MSM8976 and APQ variants.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 98
1 file changed, 98 insertions(+)
diff --git
From: AngeloGioacchino Del Regno
These two clocks aren't present in all versions of the MDP5 HW:
where present, they are needed to enable the Translation Buffer
Unit(s).
Signed-off-by: AngeloGioacchino Del Regno
---
Documentation/devicetree/bindings/display/msm/mdp5.txt | 2 ++
1 file
From: AngeloGioacchino Del Regno
Add the configuration entries for the MDP5 v1.11, found on
MSM8956, MSM8976 and APQ variants.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 98
1 file changed, 98 insertions(+)
diff --git
From: AngeloGioacchino Del Regno
MSM8976, MSM8976 and APQ variants have DSI version 3:10040002
(DSI 6G V1.4.2), featuring two DSIs.
They need three clocks (mdp_core, iface, bus), one GDSC and
two vregs, VDDA at 1.2V and VDDIO at 1.8V.
Signed-off-by: AngeloGioacchino Del Regno
---
From: AngeloGioacchino Del Regno
The 28nm PLL has a different iospace on MSM/APQ family B SoCs:
add a new configuration and use it when the DT reports the
"qcom,dsi-phy-28nm-hpm-fam-b" compatible.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
From: AngeloGioacchino Del Regno
These two clocks aren't present in all versions of the MDP5 HW:
where present, they are needed to enable the Translation Buffer
Unit(s).
Signed-off-by: AngeloGioacchino Del Regno
---
Documentation/devicetree/bindings/display/msm/mdp5.txt | 2 ++
1 file
From: AngeloGioacchino Del Regno
The Adreno 510 GPU is a stripped version of the Adreno 5xx,
found in low-end SoCs like 8x56 and 8x76, which has 256K of
GMEM, with no GPMU nor ZAP.
Also, since the Adreno 5xx part of this driver seems to be
developed with high-end Adreno GPUs in mind, and since
From: AngeloGioacchino Del Regno
This patch series enables support for MSM8956/76 and its Adreno 510
GPU on the current DRM driver.
The personal aim is to upstream MSM8956 as much as possible.
This code has been tested on two Sony phones featuring the Qualcomm
MSM8956 SoC.
Changes in v2:
-
From: AngeloGioacchino Del Regno
Some SoCs, like MSM8956/8976 (and APQ variants), do feature these
clocks and we need to enable them in order to get both of the
hw (mdp5/rot) Translation Buffer Units (TBUs) to properly work.
Signed-off-by: AngeloGioacchino Del Regno
---
From: AngeloGioacchino Del Regno
On family B SoCs, the 28nm PLL has a different iospace address
and that required a new compatible in the driver.
Signed-off-by: AngeloGioacchino Del Regno
---
Documentation/devicetree/bindings/display/msm/dsi.txt | 1 +
1 file changed, 1 insertion(+)
diff
From: "Angelo G. Del Regno"
The 28nm PLL has a different iospace on MSM/APQ family B SoCs:
add a new configuration and use it when the DT reports the
"qcom,dsi-phy-28nm-hpm-fam-b" compatible.
Signed-off-by: Angelo G. Del Regno
---
.../devicetree/bindings/display/msm/dsi.txt| 1 +
From: "Angelo G. Del Regno"
MSM8956/APQ8056 has DSI version 3:10040002 (DSI 6G V1.4.2), featuring
two DSIs. It needs three clocks (mdp_core, iface, bus), one GDSC and
two vregs, VDDA at 1.2V and VDDIO at 1.8V.
Signed-off-by: Angelo G. Del Regno
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 22
From: "Angelo G. Del Regno"
The Adreno 510 GPU is a stripped version of the Adreno 5xx,
found in low-end SoCs like 8x56 and 8x76, which has 256K of
GMEM, with no GPMU nor ZAP.
Also, since the Adreno 5xx part of this driver seems to be
developed with high-end Adreno GPUs in mind, and since this
From: "Angelo G. Del Regno"
Some SoCs, like MSM8956/8976 (and APQ variants), do feature these
clocks and we need to enable them in order to get the hardware to
properly work.
Signed-off-by: Angelo G. Del Regno
---
Documentation/devicetree/bindings/display/msm/mdp5.txt | 2 ++
From: "Angelo G. Del Regno"
Add the configuration entries for the MDP5 v1.11, found on MSM8956
and APQ8056.
Signed-off-by: Angelo G. Del Regno
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 99
1 file changed, 99 insertions(+)
diff --git
From: AngeloGioacchino Del Regno
This patch series enables support for MSM8956/76 and its Adreno 510
GPU on the current DRM driver.
The personal aim is to upstream MSM8956 as much as possible.
This code has been tested on two Sony phones featuring the Qualcomm
MSM8956 SoC.
Changes in v2:
-
From: "Angelo G. Del Regno"
Some SoCs, like MSM8956/8976 (and APQ variants), do feature these
clocks and we need to enable them in order to get the hardware to
properly work.
Signed-off-by: Angelo G. Del Regno
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 10 ++
From: "Angelo G. Del Regno"
The 28nm PLL has a different iospace on MSM/APQ family B SoCs:
add a new configuration and use it when the DT reports the
"qcom,dsi-phy-28nm-hpm-fam-b" compatible.
Signed-off-by: Angelo G. Del Regno
---
.../devicetree/bindings/display/msm/dsi.txt| 1 +
From: "Angelo G. Del Regno"
The Adreno 510 GPU is a stripped version of the Adreno 5xx,
found in low-end SoCs like 8x56 and 8x76, which has 256K of
GMEM, with no GPMU nor ZAP.
Also, since the Adreno 5xx part of this driver seems to be
developed with high-end Adreno GPUs in mind, and since this
From: AngeloGioacchino Del Regno
This patch series enables support for MSM8956/76 and its Adreno 510
GPU on the current DRM driver.
The personal aim is to upstream MSM8956 as much as possible.
This code has been tested on two Sony phones featuring the Qualcomm
MSM8956 SoC.
Angelo G. Del Regno
From: "Angelo G. Del Regno"
Add the configuration entries for the MDP5 v1.11, found on MSM8956
and APQ8056.
Signed-off-by: Angelo G. Del Regno
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 99
1 file changed, 99 insertions(+)
diff --git
From: "Angelo G. Del Regno"
MSM8956/APQ8056 has DSI version 3:10040002 (DSI 6G V1.4.2), featuring
two DSIs. It needs three clocks (mdp_core, iface, bus), one GDSC and
two vregs, VDDA at 1.2V and VDDIO at 1.8V.
Signed-off-by: Angelo G. Del Regno
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 22
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