Re: [Freedreno] [DPU PATCH v3 4/5] drm/msm/dp: add support for DP PLL driver

2020-02-27 Thread Matthias Kaehlcke
On Mon, Dec 02, 2019 at 01:48:27PM +, Chandan Uddaraju wrote:
> Add the needed DP PLL specific files to support
> display port interface on msm targets.
> 
> The DP driver calls the DP PLL driver registration.
> The DP driver sets the link and pixel clock sources.
> 
> Changes in v2:
> -- Update copyright markings on all relevant files.
> -- Use DRM_DEBUG_DP for debug msgs.
> 
> Signed-off-by: Chandan Uddaraju 
> ---
> diff --git a/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c 
> b/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c
> new file mode 100644
> index 000..6ef2492
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c
>
> ...
>
> +static u8 dp_mux_get_parent_10nm(struct clk_hw *hw)
> +{
> + u32 auxclk_div = 0;
> + struct dp_pll_10nm_pclksel *pclksel = to_pll_10nm_pclksel(hw);
> + struct dp_pll_10nm *dp_res = pclksel->pll;
> + u8 val = 0;
> +
> + DRM_ERROR("clk_hw->init->name = %s\n", hw->init->name);

drive-by comment: DRM_ERROR doesn't seem the right level, DRM_DEBUG_DP
would probably be more adequate.

Also I found this line triggers a NULL pointer dereference on a SC7180
system, where clk_hw->init is NULL.
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[Freedreno] [DPU PATCH v3 4/5] drm/msm/dp: add support for DP PLL driver

2019-12-02 Thread Chandan Uddaraju
Add the needed DP PLL specific files to support
display port interface on msm targets.

The DP driver calls the DP PLL driver registration.
The DP driver sets the link and pixel clock sources.

Changes in v2:
-- Update copyright markings on all relevant files.
-- Use DRM_DEBUG_DP for debug msgs.

Signed-off-by: Chandan Uddaraju 
---
 drivers/gpu/drm/msm/Kconfig   |  13 +
 drivers/gpu/drm/msm/Makefile  |   4 +
 drivers/gpu/drm/msm/dp/dp_display.c   |  48 +++
 drivers/gpu/drm/msm/dp/dp_display.h   |   3 +
 drivers/gpu/drm/msm/dp/dp_parser.h|   4 +
 drivers/gpu/drm/msm/dp/dp_power.h |   1 -
 drivers/gpu/drm/msm/dp/pll/dp_pll.c   | 135 +++
 drivers/gpu/drm/msm/dp/pll/dp_pll.h   |  57 +++
 drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c  | 401 +
 drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.h  |  86 +
 drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c | 494 ++
 11 files changed, 1245 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll.c
 create mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll.h
 create mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c
 create mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.h
 create mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c

diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index 7946cb1..e73ad23 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -66,6 +66,19 @@ config DRM_MSM_DP
  display support is enabled through this config option. It can
  be primary or secondary display on device.
 
+config DRM_MSM_DP_PLL
+   bool "Enable DP PLL driver in MSM DRM"
+   depends on DRM_MSM_DP && COMMON_CLK
+   help
+ Choose this option to enable DP PLL driver which provides DP
+ source clocks under common clock framework.
+
+config DRM_MSM_DP_10NM_PLL
+   bool "Enable DP 10nm PLL driver in MSM DRM (used by SDM845)"
+   depends on DRM_MSM_DP_PLL
+   help
+ Choose this option if DP PLL on SDM845 is used on the platform.
+
 config DRM_MSM_DSI
bool "Enable DSI support in MSM DRM driver"
depends on DRM_MSM
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 5939f41..3ba0c8b 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -140,4 +140,8 @@ msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/pll/dsi_pll_14nm.o
 msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/pll/dsi_pll_10nm.o
 endif
 
+msm-$(CONFIG_DRM_MSM_DP_PLL)+= dp/pll/dp_pll.o
+msm-$(CONFIG_DRM_MSM_DP_10NM_PLL)+= dp/pll/dp_pll_10nm.o \
+   dp/pll/dp_pll_10nm_util.o
+
 obj-$(CONFIG_DRM_MSM)  += msm.o
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c 
b/drivers/gpu/drm/msm/dp/dp_display.c
index a893542..b57a8c1 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -61,6 +61,48 @@ struct dp_display_private {
{}
 };
 
+static int dp_get_pll(struct dp_display_private *dp_priv)
+{
+   struct platform_device *pdev = NULL;
+   struct platform_device *pll_pdev;
+   struct device_node *pll_node;
+   struct dp_parser *dp_parser = NULL;
+
+   if (!dp_priv) {
+   DRM_ERROR("Invalid Arguments\n");
+   return -EINVAL;
+   }
+
+   pdev = dp_priv->pdev;
+   dp_parser = dp_priv->parser;
+
+   if (!dp_parser) {
+   DRM_DEV_ERROR(>dev, "%s: Parser not initialized\n", 
__func__);
+   return -EINVAL;
+   }
+
+   pll_node = of_parse_phandle(pdev->dev.of_node, "pll-node", 0);
+   if (!pll_node) {
+   DRM_DEV_ERROR(>dev, "%s: cannot find pll device\n", 
__func__);
+   return -ENXIO;
+   }
+
+   pll_pdev = of_find_device_by_node(pll_node);
+   if (pll_pdev)
+   dp_parser->pll = platform_get_drvdata(pll_pdev);
+
+   of_node_put(pll_node);
+
+   if (!pll_pdev || !dp_parser->pll) {
+   DRM_DEV_ERROR(>dev, "%s: pll driver is not ready\n", 
__func__);
+   return -EPROBE_DEFER;
+   }
+
+   dp_parser->pll_dev = get_device(_pdev->dev);
+
+   return 0;
+}
+
 static irqreturn_t dp_display_irq(int irq, void *dev_id)
 {
struct dp_display_private *dp = dev_id;
@@ -114,6 +156,10 @@ static int dp_display_bind(struct device *dev, struct 
device *master,
goto end;
}
 
+   rc = dp_get_pll(dp);
+   if (rc)
+   goto end;
+
rc = dp_aux_register(dp->aux);
if (rc) {
DRM_ERROR("DRM DP AUX register failed\n");
@@ -812,6 +858,7 @@ int __init msm_dp_register(void)
 {
int ret;
 
+   msm_dp_pll_driver_register();
ret = platform_driver_register(_display_driver);
if (ret) {
DRM_ERROR("driver register failed");
@@ -823,6 +870,7 @@ int __init msm_dp_register(void)
 
 void __exit