Re: [Freedreno] [v5] drm/msm/disp/dpu1: add support for dspp sub block flush in sc7280
On Sat, 1 Oct 2022 at 17:25, Kalyan Thota wrote: > > > >-Original Message- > >From: Dmitry Baryshkov > >Sent: Friday, September 30, 2022 1:59 PM > >To: Doug Anderson ; Kalyan Thota (QUIC) > > > >Cc: y...@qualcomm.com; dri-devel ; > >linux-arm- > >msm ; freedreno > >; open list:OPEN FIRMWARE AND FLATTENED > >DEVICE TREE BINDINGS ; LKML >ker...@vger.kernel.org>; Rob Clark ; Stephen Boyd > >; Vinod Polimera (QUIC) > >; Abhinav Kumar (QUIC) > > > >Subject: Re: [v5] drm/msm/disp/dpu1: add support for dspp sub block flush in > >sc7280 > > > >WARNING: This email originated from outside of Qualcomm. Please be wary of > >any links or attachments, and do not enable macros. > > > >On 29 September 2022 19:13:20 GMT+03:00, Doug Anderson > > wrote: > >>Hi, > >> > >>On Wed, Sep 14, 2022 at 5:16 AM Kalyan Thota > >wrote: > >>> > >>> Flush mechanism for DSPP blocks has changed in sc7280 family, it > >>> allows individual sub blocks to be flushed in coordination with > >>> master flush control. > >>> > >>> Representation: master_flush && (PCC_flush | IGC_flush .. etc ) > >>> > >>> This change adds necessary support for the above design. > >>> > >>> Changes in v1: > >>> - Few nits (Doug, Dmitry) > >>> - Restrict sub-block flush programming to dpu_hw_ctl file (Dmitry) > >>> > >>> Changes in v2: > >>> - Move the address offset to flush macro (Dmitry) > >>> - Seperate ops for the sub block flush (Dmitry) > >>> > >>> Changes in v3: > >>> - Reuse the DPU_DSPP_xx enum instead of a new one (Dmitry) > >>> > >>> Changes in v4: > >>> - Use shorter version for unsigned int (Stephen) > >>> > >>> Reviewed-by: Dmitry Baryshkov > >>> --- > >>> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +- > >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 +++- > >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +++ > >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 35 > >-- > >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 10 ++-- > >>> 5 files changed, 50 insertions(+), 6 deletions(-) > >> > >>Breadcrumbs: though this is tagged in the subject as v5 I think the > >>newest version is actually "resend v4" [1] which just fixes the > >>Signed-off-by. > > > >Not to mention that v5 misses the S-o-B tag. > > > >> > >>[1] > >>https://lore.kernel.org/r/1663825463-6715-1-git-send-email-quic_kalyant > >>@quicinc.com > > > Latest one is > https://lore.kernel.org/r/1663825463-6715-1-git-send-email-quic_kaly...@quicinc.com > that I last posted. > Don’t recollect on why tag was marked as v5. To avoid confusion, shall I > resend it again ? Currently I see v5 and after that comes a resend of v4. So, please send v6 with all the tags being present, no y@ in the msg-id/in-reply-to/etc. -- With best wishes Dmitry
Re: [Freedreno] [v5] drm/msm/disp/dpu1: add support for dspp sub block flush in sc7280
>-Original Message- >From: Dmitry Baryshkov >Sent: Friday, September 30, 2022 1:59 PM >To: Doug Anderson ; Kalyan Thota (QUIC) > >Cc: y...@qualcomm.com; dri-devel ; linux-arm- >msm ; freedreno >; open list:OPEN FIRMWARE AND FLATTENED >DEVICE TREE BINDINGS ; LKML ker...@vger.kernel.org>; Rob Clark ; Stephen Boyd >; Vinod Polimera (QUIC) >; Abhinav Kumar (QUIC) > >Subject: Re: [v5] drm/msm/disp/dpu1: add support for dspp sub block flush in >sc7280 > >WARNING: This email originated from outside of Qualcomm. Please be wary of >any links or attachments, and do not enable macros. > >On 29 September 2022 19:13:20 GMT+03:00, Doug Anderson > wrote: >>Hi, >> >>On Wed, Sep 14, 2022 at 5:16 AM Kalyan Thota >wrote: >>> >>> Flush mechanism for DSPP blocks has changed in sc7280 family, it >>> allows individual sub blocks to be flushed in coordination with >>> master flush control. >>> >>> Representation: master_flush && (PCC_flush | IGC_flush .. etc ) >>> >>> This change adds necessary support for the above design. >>> >>> Changes in v1: >>> - Few nits (Doug, Dmitry) >>> - Restrict sub-block flush programming to dpu_hw_ctl file (Dmitry) >>> >>> Changes in v2: >>> - Move the address offset to flush macro (Dmitry) >>> - Seperate ops for the sub block flush (Dmitry) >>> >>> Changes in v3: >>> - Reuse the DPU_DSPP_xx enum instead of a new one (Dmitry) >>> >>> Changes in v4: >>> - Use shorter version for unsigned int (Stephen) >>> >>> Reviewed-by: Dmitry Baryshkov >>> --- >>> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +- >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 +++- >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +++ >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 35 >-- >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 10 ++-- >>> 5 files changed, 50 insertions(+), 6 deletions(-) >> >>Breadcrumbs: though this is tagged in the subject as v5 I think the >>newest version is actually "resend v4" [1] which just fixes the >>Signed-off-by. > >Not to mention that v5 misses the S-o-B tag. > >> >>[1] >>https://lore.kernel.org/r/1663825463-6715-1-git-send-email-quic_kalyant >>@quicinc.com > Latest one is https://lore.kernel.org/r/1663825463-6715-1-git-send-email-quic_kaly...@quicinc.com that I last posted. Don’t recollect on why tag was marked as v5. To avoid confusion, shall I resend it again ? >-- >With best wishes >Dmitry
Re: [Freedreno] [v5] drm/msm/disp/dpu1: add support for dspp sub block flush in sc7280
On 29 September 2022 19:13:20 GMT+03:00, Doug Anderson wrote: >Hi, > >On Wed, Sep 14, 2022 at 5:16 AM Kalyan Thota wrote: >> >> Flush mechanism for DSPP blocks has changed in sc7280 family, it >> allows individual sub blocks to be flushed in coordination with >> master flush control. >> >> Representation: master_flush && (PCC_flush | IGC_flush .. etc ) >> >> This change adds necessary support for the above design. >> >> Changes in v1: >> - Few nits (Doug, Dmitry) >> - Restrict sub-block flush programming to dpu_hw_ctl file (Dmitry) >> >> Changes in v2: >> - Move the address offset to flush macro (Dmitry) >> - Seperate ops for the sub block flush (Dmitry) >> >> Changes in v3: >> - Reuse the DPU_DSPP_xx enum instead of a new one (Dmitry) >> >> Changes in v4: >> - Use shorter version for unsigned int (Stephen) >> >> Reviewed-by: Dmitry Baryshkov >> --- >> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +- >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 +++- >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +++ >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 35 >> -- >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 10 ++-- >> 5 files changed, 50 insertions(+), 6 deletions(-) > >Breadcrumbs: though this is tagged in the subject as v5 I think the >newest version is actually "resend v4" [1] which just fixes the >Signed-off-by. Not to mention that v5 misses the S-o-B tag. > >[1] >https://lore.kernel.org/r/1663825463-6715-1-git-send-email-quic_kaly...@quicinc.com -- With best wishes Dmitry
Re: [Freedreno] [v5] drm/msm/disp/dpu1: add support for dspp sub block flush in sc7280
On 29 September 2022 19:13:20 GMT+03:00, Doug Anderson wrote: >Hi, > >On Wed, Sep 14, 2022 at 5:16 AM Kalyan Thota wrote: >> >> Flush mechanism for DSPP blocks has changed in sc7280 family, it >> allows individual sub blocks to be flushed in coordination with >> master flush control. >> >> Representation: master_flush && (PCC_flush | IGC_flush .. etc ) >> >> This change adds necessary support for the above design. >> >> Changes in v1: >> - Few nits (Doug, Dmitry) >> - Restrict sub-block flush programming to dpu_hw_ctl file (Dmitry) >> >> Changes in v2: >> - Move the address offset to flush macro (Dmitry) >> - Seperate ops for the sub block flush (Dmitry) >> >> Changes in v3: >> - Reuse the DPU_DSPP_xx enum instead of a new one (Dmitry) >> >> Changes in v4: >> - Use shorter version for unsigned int (Stephen) >> >> Reviewed-by: Dmitry Baryshkov >> --- >> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +- >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 +++- >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +++ >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 35 >> -- >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 10 ++-- >> 5 files changed, 50 insertions(+), 6 deletions(-) > >Breadcrumbs: though this is tagged in the subject as v5 I think the >newest version is actually "resend v4" [1] which just fixes the >Signed-off-by. Not to mention that v5 misses the S-o-B tag. > >[1] >https://lore.kernel.org/r/1663825463-6715-1-git-send-email-quic_kaly...@quicinc.com -- With best wishes Dmitry
Re: [Freedreno] [v5] drm/msm/disp/dpu1: add support for dspp sub block flush in sc7280
Hi, On Wed, Sep 14, 2022 at 5:16 AM Kalyan Thota wrote: > > Flush mechanism for DSPP blocks has changed in sc7280 family, it > allows individual sub blocks to be flushed in coordination with > master flush control. > > Representation: master_flush && (PCC_flush | IGC_flush .. etc ) > > This change adds necessary support for the above design. > > Changes in v1: > - Few nits (Doug, Dmitry) > - Restrict sub-block flush programming to dpu_hw_ctl file (Dmitry) > > Changes in v2: > - Move the address offset to flush macro (Dmitry) > - Seperate ops for the sub block flush (Dmitry) > > Changes in v3: > - Reuse the DPU_DSPP_xx enum instead of a new one (Dmitry) > > Changes in v4: > - Use shorter version for unsigned int (Stephen) > > Reviewed-by: Dmitry Baryshkov > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 +++- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +++ > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 35 > -- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 10 ++-- > 5 files changed, 50 insertions(+), 6 deletions(-) Breadcrumbs: though this is tagged in the subject as v5 I think the newest version is actually "resend v4" [1] which just fixes the Signed-off-by. [1] https://lore.kernel.org/r/1663825463-6715-1-git-send-email-quic_kaly...@quicinc.com
[Freedreno] [v5] drm/msm/disp/dpu1: add support for dspp sub block flush in sc7280
Flush mechanism for DSPP blocks has changed in sc7280 family, it
allows individual sub blocks to be flushed in coordination with
master flush control.
Representation: master_flush && (PCC_flush | IGC_flush .. etc )
This change adds necessary support for the above design.
Changes in v1:
- Few nits (Doug, Dmitry)
- Restrict sub-block flush programming to dpu_hw_ctl file (Dmitry)
Changes in v2:
- Move the address offset to flush macro (Dmitry)
- Seperate ops for the sub block flush (Dmitry)
Changes in v3:
- Reuse the DPU_DSPP_xx enum instead of a new one (Dmitry)
Changes in v4:
- Use shorter version for unsigned int (Stephen)
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 35 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 10 ++--
5 files changed, 50 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 601d687..4170fbe 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -766,7 +766,7 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc)
/* stage config flush mask */
ctl->ops.update_pending_flush_dspp(ctl,
- mixer[i].hw_dspp->idx);
+ mixer[i].hw_dspp->idx, DPU_DSPP_PCC);
}
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 27f029f..0eecb2f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -65,7 +65,10 @@
(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
#define CTL_SC7280_MASK \
- (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) |
BIT(DPU_CTL_VM_CFG))
+ (BIT(DPU_CTL_ACTIVE_CFG) | \
+BIT(DPU_CTL_FETCH_ACTIVE) | \
+BIT(DPU_CTL_VM_CFG) | \
+BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
#define MERGE_3D_SM8150_MASK (0)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 38aa38a..8148e91 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -161,10 +161,12 @@ enum {
* DSPP sub-blocks
* @DPU_DSPP_PCC Panel color correction block
* @DPU_DSPP_GC Gamma correction block
+ * @DPU_DSPP_IGC Inverse Gamma correction block
*/
enum {
DPU_DSPP_PCC = 0x1,
DPU_DSPP_GC,
+ DPU_DSPP_IGC,
DPU_DSPP_MAX
};
@@ -191,6 +193,7 @@ enum {
* @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
* @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs)
* @DPU_CTL_VM_CFG:CTL config to support multiple VMs
+ * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush
* @DPU_CTL_MAX
*/
enum {
@@ -198,6 +201,7 @@ enum {
DPU_CTL_ACTIVE_CFG,
DPU_CTL_FETCH_ACTIVE,
DPU_CTL_VM_CFG,
+ DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
DPU_CTL_MAX
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index a35ecb6..f26f484 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -33,6 +33,7 @@
#define CTL_INTF_FLUSH0x110
#define CTL_INTF_MASTER 0x134
#define CTL_FETCH_PIPE_ACTIVE 0x0FC
+#define CTL_DSPP_n_FLUSH(n) ((0x13C) + ((n - 1) * 4))
#define CTL_MIXER_BORDER_OUTBIT(24)
#define CTL_FLUSH_MASK_CTL BIT(17)
@@ -287,8 +288,9 @@ static void
dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct dpu_hw_ctl *ctx,
}
static void dpu_hw_ctl_update_pending_flush_dspp(struct dpu_hw_ctl *ctx,
- enum dpu_dspp dspp)
+ enum dpu_dspp dspp, u32 dspp_sub_blk)
{
+
switch (dspp) {
case DSPP_0:
ctx->pending_flush_mask |= BIT(13);
@@ -307,6 +309,31 @@ static void dpu_hw_ctl_update_pending_flush_dspp(struct
dpu_hw_ctl *ctx,
}
}
+static void dpu_hw_ctl_update_pending_flush_dspp_subblocks(
+ struct dpu_hw_ctl *ctx, enum dpu_dspp dspp, u32 dspp_sub_blk)
+{
+ u32 flushbits = 0, active;
+
+ switch (dspp_sub_blk) {
+ case DPU_DSPP_IGC:
+ flushbits = BIT(2);
+ break;
+ case DPU_DSPP_PCC:
+ flushbits = BIT(4);
+ break;
+ case DPU_DSPP_GC:
+ flushbits = BIT(5);
+ break;
+ default:
+ return;
+ }
+
+ active = DPU_REG_READ(>hw, CTL_DSPP_n_FLUSH(dspp));
+ DPU_REG_WRITE(>hw, CTL_DSPP_n_FLUSH(dspp), active | flushbits);
+
+ ctx->pending_flush_mask |= BIT(29);
+}
+
