Quoting Sandeep Panda (2018-07-16 01:43:30)
> Document the bindings used for the sn65dsi86 DSI to eDP bridge.
>
> Changes in v1:
> - Rephrase the dt-binding descriptions to be more inline with existing
>bindings (Andrzej Hajda).
> - Add missing dt-binding that are parsed by corresponding
modesetting X11 driver may provide negative x/y cordinates in
mdp5_crtc_cursor_move call when rotation is enabled.
Cursor buffer can overlap down to its negative width/height.
ROI has to be recalculated for negative x/y indicating using the
lower/right corner of the cursor buffer and hotspot
> > Hm, why not add seq_file support to dev_coredump? Neither git blame
> > nor google sched any light on why seq_file wasn't picked over the
> > custom read interface ...
> >
> > Adding Johannes and Greg about this.
>
> Main reason was that this is used for devcoredump which has its own similar
modesetting X11 driver may provide negative x/y cordinates in
mdp5_crtc_cursor_move call when rotation is enabled.
Cursor buffer can overlap down to its negative width/height.
ROI has to be recalculated for negative x/y indicating using the
lower/right corner of the cursor buffer and hotspot
On 2018-06-29 17:31, Andrzej Hajda wrote:
On 27.06.2018 11:57, Sandeep Panda wrote:
Document the bindings used for the sn65dsi86 DSI to eDP bridge.
Changes in v1:
- Rephrase the dt-binding descriptions to be more inline with
existing
bindings (Andrzej Hajda).
- Add missing dt-binding
Add support for TI's sn65dsi86 dsi2edp bridge chip.
The chip converts DSI transmitted signal to eDP signal,
which is fed to the connected eDP panel.
This chip can be controlled via either i2c interface or
dsi interface. Currently in driver all the control registers
are being accessed through i2c
Document the bindings used for the sn65dsi86 DSI to eDP bridge.
Changes in v1:
- Rephrase the dt-binding descriptions to be more inline with existing
bindings (Andrzej Hajda).
- Add missing dt-binding that are parsed by corresponding driver
(Andrzej Hajda).
Changes in v2:
- Remove edp
Changes in current patchset:
- eDP panels report EDID via DP-AUX channel, so remove support for
dedicated DDC line.
Sandeep Panda (2):
drm/bridge: add support for sn65dsi86 bridge driver
dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings
On Thu, Jul 12, 2018 at 12:57 PM, Vivek Gautam
wrote:
> Hi,
>
>
> On Wed, Jul 11, 2018 at 6:21 PM, Tomasz Figa wrote:
>> On Wed, Jul 11, 2018 at 8:11 PM Rafael J. Wysocki wrote:
>>>
>>> On Wed, Jul 11, 2018 at 12:55 PM, Vivek Gautam
>>> wrote:
>>> > Hi Rafael,
>>> >
>>> >
>>> > On Wed, Jul 11,
Hi,
On Mon, Jul 16, 2018 at 12:11 PM, Vivek Gautam
wrote:
> HI Rafael,
>
>
>
> On 7/16/2018 2:21 PM, Rafael J. Wysocki wrote:
>>
>> On Thu, Jul 12, 2018 at 12:57 PM, Vivek Gautam
>> wrote:
[cut]
Although, given the PM
subsystem internals, the suspend function wouldn't be called on
On Thu, Jul 12, 2018 at 2:41 PM, Vivek Gautam
wrote:
> Hi Rafael,
>
>
> On Wed, Jul 11, 2018 at 4:06 PM, Vivek Gautam
> wrote:
>> Hi Rafael,
>>
>>
>>
>> On 7/11/2018 3:23 PM, Rafael J. Wysocki wrote:
>>>
>>> On Sunday, July 8, 2018 7:34:12 PM CEST Vivek Gautam wrote:
From: Sricharan R
HI Rafael,
On 7/16/2018 2:21 PM, Rafael J. Wysocki wrote:
On Thu, Jul 12, 2018 at 12:57 PM, Vivek Gautam
wrote:
Hi,
On Wed, Jul 11, 2018 at 6:21 PM, Tomasz Figa wrote:
On Wed, Jul 11, 2018 at 8:11 PM Rafael J. Wysocki wrote:
On Wed, Jul 11, 2018 at 12:55 PM, Vivek Gautam
wrote:
Hi
On Thu, Jul 12, 2018 at 05:08:37PM -0400, Sean Paul wrote:
> From: Jeykumar Sankaran
>
> Adds bindings for Snapdragon 845 display processing unit
>
> Changes in v2:
> - Use SoC specific compatibles for mdss and dpu
> - Use assigned-clocks to set initial clock frequency
>
> Signed-off-by:
On 7/16/2018 2:25 PM, Rafael J. Wysocki wrote:
On Thu, Jul 12, 2018 at 2:41 PM, Vivek Gautam
wrote:
Hi Rafael,
On Wed, Jul 11, 2018 at 4:06 PM, Vivek Gautam
wrote:
Hi Rafael,
On 7/11/2018 3:23 PM, Rafael J. Wysocki wrote:
On Sunday, July 8, 2018 7:34:12 PM CEST Vivek Gautam wrote:
On Mon, Jul 9, 2018 at 1:31 PM, Sean Paul wrote:
> From: Jeykumar Sankaran
>
> Qualcomm Snapdragon chipsets uses compressed format
> to optimize BW across multiple IP's. This change adds
> needed modifier support in drm for a simple 4x4 tile
> based compressed variants of base formats.
>
>
On Monday 09 July 2018 11:01 PM, Sean Paul wrote:
From: Chandan Uddaraju
For dual dsi mode, the horizontal timing needs
to be divided by half since both the dsi controllers
will be driving this panel. Adjust the pixel clock and
DSI timing accordingly.
Reviewed-by: Archit Taneja
Changes
On Monday 09 July 2018 11:01 PM, Sean Paul wrote:
From: Rajesh Yadav
postdiv_lock spinlock was used before initialization
for 10nm pll. It causes following spin_bug:
"BUG: spinlock bad magic on CPU#0".
Initialize spinlock before its usage.
Reviewed-by: Archit Taneja
On Monday 09 July 2018 11:01 PM, Sean Paul wrote:
From: Rajesh Yadav
SoCs having mdp5 or dpu have identical tree like
device hierarchy where MDSS top level wrapper manages
common power resources for all child devices.
Subclass msm_mdss so that msm_mdss includes common defines
and mdp5/dpu
On Monday 09 July 2018 11:01 PM, Sean Paul wrote:
From: Abhinav Kumar
Make the pclk_rate u64 to accommodate higher pixel clock
rates.
Changes in v4:
- fixed commit message
Signed-off-by: Abhinav Kumar
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 9 ++---
1
On Mon, Jul 16, 2018 at 02:13:30PM +0530, Sandeep Panda wrote:
> Document the bindings used for the sn65dsi86 DSI to eDP bridge.
>
> Changes in v1:
> - Rephrase the dt-binding descriptions to be more inline with existing
>bindings (Andrzej Hajda).
> - Add missing dt-binding that are parsed
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