On Wed, Sep 05, 2018 at 07:08:28PM -0700, Jeykumar Sankaran wrote:
> RM maintained a redundant definition for display topology
> to identify the no. of hw blocks needed for a display
> and their hardware dependencies. This information can be
> implicitly deduced from the msm_display_topology
On Wed, Sep 05, 2018 at 07:08:27PM -0700, Jeykumar Sankaran wrote:
> DPU, being over protective, validates every parameter of a
> module. This change traces the call stack for some of encoder
> functions affected by previous set of clean up patches and
> cleans up unwanted validations.
>
>
On Wed, Sep 05, 2018 at 07:08:10PM -0700, Jeykumar Sankaran wrote:
> MISR support is the debug feature present in Snapdragon chipsets.
> At the layer mixer and interfaces, MISR algorithm can generate CRC
> signatures of the pixel data which can be used for validating
> the frames generated. Since
On Wed, Sep 05, 2018 at 07:08:26PM -0700, Jeykumar Sankaran wrote:
> Connector states were passed around RM to update the custom
> topology connector property with chosen topology data. Now that
> we got rid of both custom properties and topology names, this
> change cleans up the mechanism to
On Wed, Sep 05, 2018 at 07:08:09PM -0700, Jeykumar Sankaran wrote:
> Based on the comments received for the patch series[1] and to
> make the review process a bit more easy, spliting up the
> patches for cleanup and resource manager refactor. This series
> cleans up and prepares the DPU for
On Wed, Sep 05, 2018 at 07:08:11PM -0700, Jeykumar Sankaran wrote:
> DPU power handler maintained PRE/POST versions of power
> ENABLE/DISABLE events to accommodate tasks which need be
> handled before/after data bus voting. But since the bus voting
> API's are deprecated and removed from the
Hi Vivek,
On Thu, Aug 30, 2018 at 11:46 PM Vivek Gautam
wrote:
>
> From: Sricharan R
>
> The smmu device probe/remove and add/remove master device callbacks
> gets called when the smmu is not linked to its master, that is without
> the context of the master device. So calling runtime apis in
Hi Tomasz,
On 9/7/2018 2:46 PM, Tomasz Figa wrote:
Hi Vivek,
On Thu, Aug 30, 2018 at 11:46 PM Vivek Gautam
wrote:
From: Sricharan R
The smmu device probe/remove and add/remove master device callbacks
gets called when the smmu is not linked to its master, that is without
the context of the
On Fri, Sep 7, 2018 at 6:38 PM Vivek Gautam wrote:
>
> Hi Tomasz,
>
>
> On 9/7/2018 2:46 PM, Tomasz Figa wrote:
> > Hi Vivek,
> >
> > On Thu, Aug 30, 2018 at 11:46 PM Vivek Gautam
> > wrote:
> >> From: Sricharan R
> >>
> >> The smmu device probe/remove and add/remove master device callbacks
>
On Fri, Sep 7, 2018 at 3:22 PM Tomasz Figa wrote:
>
> On Fri, Sep 7, 2018 at 6:38 PM Vivek Gautam
> wrote:
> >
> > Hi Tomasz,
> >
> >
> > On 9/7/2018 2:46 PM, Tomasz Figa wrote:
> > > Hi Vivek,
> > >
> > > On Thu, Aug 30, 2018 at 11:46 PM Vivek Gautam
> > > wrote:
> > >> From: Sricharan R
> >
On 2018-09-06 09:14, Jordan Crouse wrote:
On Wed, Sep 05, 2018 at 07:08:26PM -0700, Jeykumar Sankaran wrote:
Connector states were passed around RM to update the custom
topology connector property with chosen topology data. Now that
we got rid of both custom properties and topology names, this
We are moving the PDC registers to their own region in the DT and
the offsets need to be changed accordingly. Similarly move GX_DBGC
to its own domain.
Also, add the enums and other bits needed to support the expanded
devcoredump for a6xx and fix a transposed bit value for GMU.
---
Based on the comments received for the patch series[1] and to
make the review process a bit more easy, spliting up the
patches for cleanup and resource manager refactor. This series
cleans up and prepares the DPU for upcoming RM changes.
[1] https://patchwork.freedesktop.org/series/44669/
Identify slave-master encoders during initialization and enable
the encoders explicitly as the current logic has redundant and
ambiguous loops.
changes in v4:
- identify master/slave encoder while adding
adding physical encoders(Sean)
changes in v5:
- get rid of
Destination scaling(DS) is a Snapdragon hardware feature to
scale up the display ROI after layer blending. DPU driver doesn't
support programming of DS blocks yet. This change cleans up the
residual code present in catalog and RM for DS block handling.
Support for the same can be added back when
Prep changes for state based resource management.
Moves all the hw block tracking for the crtc to the state
object.
changes in v4:
- Serialize crtc state access in debugfs handlers (Sean)
- Split the crtc width query as a separate change (Sean)
changes in v5:
- mode set
RM maintained a redundant definition for display topology
to identify the no. of hw blocks needed for a display
and their hardware dependencies. This information can be
implicitly deduced from the msm_display_topology structure
available in RM reserve request. In addition to getting
rid of the
cleans up left out scalar config definitions from headers
changes in v4:
- none
changes in v5:
- none
changes in v6:
- none
Signed-off-by: Jeykumar Sankaran
Reviewed-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h| 2 --
Avoid querying RM for hw mdp block. Use the one
stored in KMS during initialization.
changes in v4:
- none
changes in v5:
- none
changes in v6:
- none
Signed-off-by: Jeykumar Sankaran
Reviewed-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 12
Support for CDM block is not present in DPU. Remove CDM
handlers from resource manager.
changes in v4:
- Introduced in the series
changes in v5:
- Remove catalog references to CDM (Sean)
changes in v6:
- none
Signed-off-by: Jeykumar Sankaran
Reviewed-by: Sean Paul
---
Mark CRTC get_mixer_width helper API static as it is
not used outside the file.
changes in v4:
- Patch introduced in the series
changes in v5:
- Simplify the inline function (Sean)
changes in v6:
- none
Signed-off-by: Jeykumar Sankaran
Reviewed-by: Sean Paul
---
Resource manager assigns hw_intf blocks for the encoder only on
modeset. If queried for hw_intf objects during init, it will be
NULL. Since hw_intf objects are needed only after encoder enable,
defer the query to encoder enable which will be triggered after
modeset.
changes in v4:
- Add
Connector states were passed around RM to update the custom
topology connector property with chosen topology data. Now that
we got rid of both custom properties and topology names, this
change cleans up the mechanism to pass connector states across
RM helpers and encoder functions.
changes in v5:
Encoder H_TILE values are not used for allocating the hw blocks.
no. of hw_intf blocks provides the info.
changes in v4:
- remove irrelevant changes (Sean)
- retain log macros (Sean)
changes in v5:
- none
changes in v6:
- none
Signed-off-by: Jeykumar Sankaran
DPU, being over protective, validates every parameter of a
module. This change traces the call stack for some of encoder
functions affected by previous set of clean up patches and
cleans up unwanted validations.
changes in v5:
- Introduced in the series
changes in v6:
- none
DPU power handler maintained PRE/POST versions of power
ENABLE/DISABLE events to accommodate tasks which need be
handled before/after data bus voting. But since the bus voting
API's are deprecated and removed from the driver, squash
the events and their clients respective event handlers
to handle
removes left out variables of previous ping pong
split topology cleanup.
changes in v4:
- none
changes in v5:
- none
changes in v6:
- none
Signed-off-by: Jeykumar Sankaran
Reviewed-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 3 ---
1 file changed, 3
In virtual encoder modeset, DPU makes RM request to assign hw blocks
for the display. It is also expected in modeset to iterate and
associate the physical encoders with their relevant hw blocks.
Ping pong blocks are already handled here but hw ctl blocks are not.
This change moves the hw_ctl
Rename hw_ctl to lm_ctl to mean the ctl associated
with the hw layer mixer block.
sed -i 's/\([*@.>]\)hw_ctl\([^s]\)/\1lm_ctl\2/g' dpu_crtc.c dpu_crtc.h
changes in v4:
- Specifiy shell command used for renaming (Sean)
changes in v5:
- none
changes in v6:
- none
DPU had the support to LOCK the hw resources in
atomic check and CLEAR the locked resources explicitly
through custom property values. Now that DPU is
stripped off of all the custom properties, the RM
handlers for this feature will be no-op's. This change
gets rid of all its references.
changes
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