Hi,
On Thu, Dec 20, 2018 at 9:30 AM Jordan Crouse wrote:
>
> Try to get the interconnect path for the GPU and vote for the maximum
> bandwidth to support all frequencies. This is needed for performance.
> Later we will want to scale the bandwidth based on the frequency to
> also optimize for
On Thu, Dec 20, 2018 at 10:46:45AM -0800, Chia-I Wu wrote:
> It gets the generic states from the adreno core.
>
> This also adds a missing NULL check in msm_gpu_open.
>
> Signed-off-by: Chia-I Wu
Thanks for the patch. We have an expanded version of the 6xx gpu state in
msm-next [1]. You can
Hi,
On Thu, Dec 20, 2018 at 9:30 AM Jordan Crouse wrote:
>
> Add documentation for the interconnect and interconnect-names bindings
> for the GPU node as detailed by bindings/interconnect/interconnect.txt.
>
> Signed-off-by: Jordan Crouse
> ---
>
>
Hi,
On Thu, Dec 20, 2018 at 9:30 AM Jordan Crouse wrote:
>
> Define an interconnect port for the GPU to set bus
> capabilities.
>
> Signed-off-by: Jordan Crouse
> ---
>
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
For going through Andy's tree once the
Ah, thanks. I was on drm-next branch. I will switch to msm-next.
On Thu, Dec 20, 2018 at 11:47 AM Jordan Crouse
wrote:
> On Thu, Dec 20, 2018 at 10:47:02AM -0800, Chia-I Wu wrote:
> > memptrs_bo is used to store msm_rbmemptrs. Size it correctly.
> >
> > Signed-off-by: Chia-I Wu
>
> Thanks
Quoting Matthias Kaehlcke (2018-12-19 15:55:25)
> Get the ref clock of the PHY from the device tree instead of
> hardcoding its name and rate.
>
> Note: This change could break old out-of-tree DTS files that
> use the 10nm PHY
>
> Signed-off-by: Matthias Kaehlcke
> Reviewed-by: Douglas Anderson
Quoting Matthias Kaehlcke (2018-12-19 15:55:24)
> Get the ref clock of the PHY from the device tree instead of
> hardcoding its name and rate.
>
> Note: This change could break old out-of-tree DTS files that
> use the 14nm PHY.
>
> Signed-off-by: Matthias Kaehlcke
> Reviewed-by: Douglas
The interconnect API provides an interface for consumer drivers to express
their bandwidth needs in the SoC. This data is aggregated and the on-chip
interconnect hardware is configured to the appropriate power/performance
profile.
MDSS is one of the interconnect consumers which uses the
From: Sravanthi Kollukuduru
Add interconnect properties such as interconnect provider specifier
, the edge source and destination ports which are required by the
interconnect API to configure interconnect path for MDSS.
Changes in v2:
- none
Changes in v3:
- Remove common
From: Sravanthi Kollukuduru
Since the upstream interconnect bus framework has landed
upstream, the existing references of custom bus scaling
needs to be cleaned up.
Changes in v2:
- Fixed build error due to partial clean up
Changes in v3:
- Condense multiple lines into a single
Add interconnect properties such as the source and the destination
ports for MDSS on SDM845.
Signed-off-by: Jayant Shekhar
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
On 12/21/2018 2:59 AM, Stephen Boyd wrote:
Quoting Rob Herring (2018-12-19 15:47:25)
On Wed, Dec 19, 2018 at 4:40 PM Doug Anderson wrote:
On Wed, Dec 19, 2018 at 12:40 PM Doug Anderson wrote:
On Wed, Dec 19, 2018 at 12:09 PM Rob Herring wrote:
...but it does have a frequency, doesn't it?
4.14-stable review patch. If anyone has any objections, please let me know.
--
[ Upstream commit 098336deb946f37a70afc0979af388b615c378bf ]
The error checks on ret for a negative error return always fails because
the return value of iommu_map_sg() is unsigned and can never be
4.19-stable review patch. If anyone has any objections, please let me know.
--
[ Upstream commit 098336deb946f37a70afc0979af388b615c378bf ]
The error checks on ret for a negative error return always fails because
the return value of iommu_map_sg() is unsigned and can never be
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