On Mon, Jan 21, 2019 at 11:13 PM Sam Ravnborg wrote:
>
> Hi Daniel et al.
>
> > >
> > > Yeah the drm_crtc_helper.h header is a bit the miniature drmP.h for legacy
> > > kms drivers. Just removing it from all the atomic drivers caused lots of
> > > fallout, I expect even more if you entirely
On Mon, Dec 17, 2018 at 03:34:09PM -0800, Tanmay Shah wrote:
> Correct definition of both formats by swapping red
> and blue channels
>
> v3: update commit message
>
> Signed-off-by: Tanmay Shah
Applied to dpu-staging, thanks!
Sean
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 4 ++--
Hi Dave,
A few fixes for v5.0.. the opp-level fix and removal of hard-coded irq
name is partially to make things smoother in v5.1 merge window to
avoid dependency on drm vs dt trees, but are otherwise sane changes.
The following changes since commit ba0ede185ef4c74bfecfe1c992be5dbcc5c5ac04:
Hi,
On Mon, Jan 21, 2019 at 9:13 AM Georgi Djakov wrote:
>
> Hi Rob,
>
> On 1/18/19 21:16, Rob Clark wrote:
> > On Fri, Jan 18, 2019 at 1:06 PM Doug Anderson wrote:
> >>
> >> Hi,
> >>
> >> On Thu, Dec 20, 2018 at 9:30 AM Jordan Crouse
> >> wrote:
> >>>
> >>> Try to get the interconnect path
On Wed, Dec 19, 2018 at 12:23:53AM +0530, Jayant Shekhar wrote:
> Remove enum dpu_iommu_domain from dpu mdss as its unused.
>
> Remove unnecessary comment for variable which is already
> removed.
>
> Signed-off-by: Jayant Shekhar
Applied to dpu-staging, thanks!
Sean
> ---
>
On Tue, Dec 18, 2018 at 05:05:48PM +0530, Jayant Shekhar wrote:
> Remove unused functions and macros from files handling
> dpu hardware interrupts.
>
> changes in v2:
> Removed clear_interrupt_status (Jordan Crouse)
> changes in v3:
> Changed commit text
>
> Signed-off-by: Jayant Shekhar
On Tue, Dec 18, 2018 at 06:50:38PM +0530, Jayant Shekhar wrote:
> Remove unused functions from dpu plane interface
> and unused variables from dpu plane state structure.
>
> Signed-off-by: Jayant Shekhar
Applied to dpu-staging, thanks!
Sean
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h |
Since the upstream interconnect bus framework has landed
upstream, the existing references of custom bus scaling
needs to be cleaned up.
Changes in v2:
- Fixed build error due to partial clean up
Changes in v3:
- Condense multiple lines into a single line (Sean Paul)
Changes in
The interconnect framework is designed to provide a
standard kernel interface to control the settings of
the interconnects on a SoC.
The interconnect API uses a consumer/provider-based model,
where the providers are the interconnect buses and the
consumers could be various drivers.
MDSS is one
Add interconnect properties such as interconnect provider specifier
, the edge source and destination ports which are required by the
interconnect API to configure interconnect path for MDSS.
Changes in v2:
- none
Changes in v3:
- Remove common property definitions (Rob Herring)
The interconnect API provides an interface for consumer drivers to express
their bandwidth needs in the SoC. This data is aggregated and the on-chip
interconnect hardware is configured to the appropriate power/performance
profile.
MDSS is one of the interconnect consumers which uses the
The interconnect API provides an interface for consumer drivers to express
their bandwidth needs in the SoC. This data is aggregated and the on-chip
interconnect hardware is configured to the appropriate power/performance
profile.
MDSS is one of the interconnect consumers which uses the
Since the upstream interconnect bus framework has landed
upstream, the existing references of custom bus scaling
needs to be cleaned up.
Changes in v2:
- Fixed build error due to partial clean up
Changes in v3:
- Condense multiple lines into a single line (Sean Paul)
Changes in
Add interconnect properties such as interconnect provider specifier
, the edge source and destination ports which are required by the
interconnect API to configure interconnect path for MDSS.
Changes in v2:
- none
Changes in v3:
- Remove common property definitions (Rob Herring)
The interconnect framework is designed to provide a
standard kernel interface to control the settings of
the interconnects on a SoC.
The interconnect API uses a consumer/provider-based model,
where the providers are the interconnect buses and the
consumers could be various drivers.
MDSS is one
On Thu, Jan 03, 2019 at 11:06:02AM -0800, Stephen Boyd wrote:
> Devices that make up DPU, i.e. graphics card, request their interrupts
> from this "virtual" interrupt chip. The interrupt chip builds upon a GIC
> SPI interrupt that raises high when any of the interrupts in the DPU's
> irq status
On Mon, Dec 17, 2018 at 02:35:03PM -0800, Jeykumar Sankaran wrote:
> Fix intf_type description in msm_disp_info to show that
> it represents drm encoder mode of the display.
>
> changes in v3:
> - introduced in the series
> changes in v4:
> - none
>
> Signed-off-by: Jeykumar Sankaran
On Mon, Dec 17, 2018 at 02:35:04PM -0800, Jeykumar Sankaran wrote:
> Bail out KMS hw init on display initialization failures with
> proper error logging.
>
> changes in v3:
> - introduced in the series
> changes in v4:
> - avoid duplicate return on errors (Sean Paul)
> - avoid
On Tue, Jan 01, 2019 at 11:15:25PM -0800, Chandan Uddaraju wrote:
This seems fine to me. Could you please:
- delete the cover letter
- move the cover letter description into the patch commit msg
- strip DPU from the subject prefix
- send it to dri-devel, maintaining the cc's you have here
With
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