Hi Bjorn
On 2021-05-10 21:20, Bjorn Andersson wrote:
In the search for causes to timing issues seen during implementation of
eDP support for SC8180x a fair amount of time was spent concluding why
the calculated mvid/nvid values where wrong.
The overall conclusion is that the ratio of MVID/NVID
On 29/05/2021 01:23, abhin...@codeaurora.org wrote:
On 2021-05-28 03:39, Dmitry Baryshkov wrote:
On 21/05/2021 15:49, Vinod Koul wrote:
For DSC to work we typically need a 2,2,1 configuration. This should
suffice for resolutions upto 4k. For more resolutions like 8k this won't
work.
Stop calling msm_dsi_phy_pll_save_state() from dsi_pll_7nm_init() and
dsi_pll_10nm_init(), as this is handled now by the generic code.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 3 ---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 3 ---
2 files changed, 6
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/msm_disp_snapshot.c | 3 +++
drivers/gpu/drm/msm/disp/msm_disp_snapshot.h | 19 ---
.../gpu/drm/msm/disp/msm_disp_snapshot_util.c | 8
3 files changed, 11 insertions(+), 19 deletions(-)
diff --git
Change msm_disp_snapshot to use dump_state API.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Kconfig | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
drivers/gpu/drm/msm/disp/msm_disp_snapshot.c | 2 +-
drivers/gpu/drm/msm/disp/msm_disp_snapshot.h |
This patchseries is an RFC for splitting Qualcomm DSI PHY from drm/msm
driver to generic PHY subsystem.
Dependencies:
- msm_disp_snapshot fix at
https://lore.kernel.org/linux-arm-msm/20210527220330.3364716-1-dmitry.barysh...@linaro.org/
- Patches 1-7 from
msm_dsi_phy_pll_restore_state() is only called from msm_dsi_phy_enable(),
so there is no need to export it. Mark it static.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi.h | 1 -
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 30 +--
2 files changed,
Move DSI PHY state saving from dsi manager to dsi_phy driver. This way
the manager does not need to know that the DSI state is not preserved
acrosss resets. Everything is handled by the DSI PHY driver.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi.h | 1 -
From: Benjamin Li
Take advantage of previously-added support for persisting PLL
registers across DSI PHY disable/enable cycles (see 328e1a6
'drm/msm/dsi: Save/Restore PLL status across PHY reset') to
support persisting across the very first DSI PHY enable at
boot.
The bootloader may have left
Add small API covering lists of register dumps. Currently this is a part
of MSM DRM driver, but is extracted as it might be usefull to other
drivers too.
Signed-off-by: Dmitry Baryshkov
---
include/linux/dump_state.h | 78 ++
lib/Kconfig| 3
On 2021-05-10 21:20, Bjorn Andersson wrote:
The eDP controller found in SC8180x is at large compatible with the
current implementation, but has its register blocks at slightly
different offsets.
Add the compatible and the new register layout.
I am not able to completely recall the history of
On 2021-05-28 03:39, Dmitry Baryshkov wrote:
On 21/05/2021 15:49, Vinod Koul wrote:
For DSC to work we typically need a 2,2,1 configuration. This should
suffice for resolutions upto 4k. For more resolutions like 8k this
won't
work.
Furthermore, we can use 1 DSC encoder in lesser resulutions,
Normal DP suspend operation contains two steps, display off followed
by dp suspend, to complete system wide suspending cycle if display is
up at that time. In this case, DP phy will be powered off at display
off. However there is an exception case that depending on the timing
of dongle plug in
Hi Bjorn
On 2021-05-19 07:51, Bjorn Andersson wrote:
On Tue 18 May 22:41 CDT 2021, abhin...@codeaurora.org wrote:
Hi Bjorn
I had a quick glance on the series and before getting to other things
wanted
to know how you are initializing two different connectors for
DP & EDP resp.
The
On 2021-05-10 21:20, Bjorn Andersson wrote:
Not all platforms has DP_P0 at offset 0x1000 from the beginning of the
DP block. So move the offsets into dss_io_data, to make it possible in
the next patch to specify alternative offsets and sizes of these
segments.
Signed-off-by: Bjorn Andersson
On 2021-05-10 21:20, Bjorn Andersson wrote:
Some bootloaders set the widebus enable bit in the INTF_CONFIG
register,
but configuration of widebus isn't yet supported ensure that the
register has a known value, with widebus disabled.
Fixes: c943b4948b58 ("drm/msm/dp: add displayPort driver
On 21/05/2021 15:49, Vinod Koul wrote:
DSC needs some configuration from device tree, add support to read and
store these params and add DSC structures in msm_drv
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 170 +
On 21/05/2021 15:49, Vinod Koul wrote:
For DSC to work we typically need a 2,2,1 configuration. This should
suffice for resolutions upto 4k. For more resolutions like 8k this won't
work.
Furthermore, we can use 1 DSC encoder in lesser resulutions, but that is
not power efficient according to
On 21/05/2021 15:49, Vinod Koul wrote:
This add the bits in RM to enable the DSC blocks
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 32 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 +
3
On 21/05/2021 15:49, Vinod Koul wrote:
We cannot enable mode_3d when we are using the DSC. So pass
configuration to detect DSC is enabled and not enable mode_3d
when we are using DSC
We add a helper dpu_encoder_helper_get_dsc_mode() to detect dsc
enabled and pass this to .setup_intf_cfg()
On 21/05/2021 15:49, Vinod Koul wrote:
Display Stream Compression (DSC) is one of the hw blocks in dpu, so add
support by adding hw blocks for DSC
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/Makefile | 1 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 26 +++
On 5/3/21 1:11 PM, Rob Herring wrote:
On Fri, Apr 23, 2021 at 01:24:40PM -0400, Jonathan Marek wrote:
Document qcom,dsi-phy-cphy-mode option, which can be used to control
whether DSI will operate in D-PHY (default) or C-PHY mode.
Given this is a standard MIPI thing, I think this needs to be a
On 07/04/2021 18:01, Dmitry Baryshkov wrote:
Move the bus clock to mdp device node,in order to facilitate bus band
width scaling on sdm845 target.
The parent device MDSS will not vote for bus bw, instead the vote will
be triggered by mdp device node. Since a minimum vote is required to
turn on
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