Re: [Freedreno] [PATCH 1/4] drm/msm: remove qcom, gpu-pwrlevels bindings

2017-02-01 Thread Jordan Crouse
On Mon, Jan 30, 2017 at 01:35:47PM -0500, Rob Clark wrote: > On Mon, Jan 30, 2017 at 1:21 PM, Eric Anholt wrote: > > Rob Clark writes: > > > >> The plan is to use the OPP bindings. For now, remove the documentation > >> for qcom,gpu-pwrlevels, and make the

Re: [Freedreno] [RFC] drm/msm/adreno: clean up gpu bindings

2017-02-02 Thread Jordan Crouse
On Thu, Jan 26, 2017 at 05:03:54PM -0500, Rob Clark wrote: > On Thu, Jan 26, 2017 at 4:09 PM, Rob Herring wrote: > > On Thu, Jan 26, 2017 at 1:51 PM, Rob Clark wrote: > >> On Thu, Jan 26, 2017 at 2:11 PM, Rob Herring wrote: > >>> On Tue,

Re: [Freedreno] [PATCH 11/11] drm/msm: Implement preemption for A5XX targets

2017-02-08 Thread Jordan Crouse
On Wed, Feb 08, 2017 at 12:30:08PM -0800, Stephen Boyd wrote: > On 02/06/2017 09:39 AM, Jordan Crouse wrote: > > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_preempt.c > > b/drivers/gpu/drm/msm/adreno/a5xx_preempt.c > > new file mode 100644 > > index 000..348ead7

[Freedreno] [PATCH 03/11] drm/msm: Add hint to DRM_IOCTL_MSM_GEM_INFO to return an object IOVA

2017-02-06 Thread Jordan Crouse
Modify the 'pad' member of struct drm_msm_gem_info to 'hint'. If the user sets 'hint' to non-zero it means that they want a IOVA for the GEM object instead of a mmap() offset. Return the iova in the 'offset' member. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/d

[Freedreno] [PATCH 04/11] drm/msm: Remove idle function hook

2017-02-06 Thread Jordan Crouse
There isn't any generic code that uses ->idle so remove it. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 4 ++-- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 4 ++-- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 9 - drivers/gp

[Freedreno] [PATCH 05/11] drm/msm: get an iova from the address space instead of an id

2017-02-06 Thread Jordan Crouse
index into a list of domains, we need to maintain a list of them. Luckily the list will be pretty small; even with dynamic address spaces we wouldn't ever see more than two or three. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 8 +- d

[Freedreno] [PATCH 01/11] drm/msm: Make sure to detach the MMU during GPU cleanup

2017-02-06 Thread Jordan Crouse
We should be detaching the MMU before destroying the address space. To do this cleanly, the detach has to happen in adreno_gpu_cleanup() because it needs access to structs in adreno_gpu.c. Plus it is better symmetry to have the attach and detach at the same code level. Signed-off-by: Jordan

[Freedreno] [PATCH 07/11] drm/msm: Remove memptrs->wptr

2017-02-06 Thread Jordan Crouse
memptrs->wptr seems to be unused. Remove it to avoid confusing the upcoming preemption code. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 --- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 - 2 files changed, 4 deletions(-) d

[Freedreno] [PATCH 06/11] drm/msm: Add a struct to pass configuration to msm_gpu_init()

2017-02-06 Thread Jordan Crouse
The amount of information that we need to pass into msm_gpu_init() is steadily increasing, so add a new struct to stabilize the function call and make it easier to add new configuration down the line. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/

[Freedreno] [PATCH 11/11] drm/msm: Implement preemption for A5XX targets

2017-02-06 Thread Jordan Crouse
Implement preemption for A5XX targets - this allows multiple ringbuffers for different priorities with automatic preemption of a lower priority ringbuffer if a higher one is ready. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/Makefile

[Freedreno] [PATCH 08/11] drm/msm: Support multiple ringbuffers

2017-02-06 Thread Jordan Crouse
specific so this code just allows for the possibility but still only defines one ringbuffer for each target family. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 9 +- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 9 +- drivers/gpu/drm/msm/

[Freedreno] [PATCH 09/11] drm/msm: Shadow current pointer in the ring until command is complete

2017-02-06 Thread Jordan Crouse
load for non-preemption targets should be minimal. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 +++-- drivers/gpu/drm/msm/msm_ringbuffer.c| 1 + drivers/gpu/drm/msm/msm_ringbuffer.h| 12 3 files chang

[Freedreno] [PATCH 10/11] drm/msm: Make the value of RB_CNTL (almost) generic

2017-02-06 Thread Jordan Crouse
but that only needs to be done once and doesn't affect A5XX so we can or in the value at init time. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 12 +++- drivers/gpu/drm/msm/msm_gpu.h | 5 + 2 files chang

[Freedreno] [PATCH 00/11] drm/msm: A5XX preemption

2017-02-06 Thread Jordan Crouse
). Jordan Jordan Crouse (11): drm/msm: Make sure to detach the MMU during GPU cleanup drm/msm: Improve the zap shader drm/msm: Add hint to DRM_IOCTL_MSM_GEM_INFO to return an object IOVA drm/msm: Remove idle function hook drm/msm: get an iova from the address space instead of an id drm/msm

[Freedreno] [PATCH 02/11] drm/msm: Improve the zap shader

2017-02-06 Thread Jordan Crouse
Simply the code, use snprintf correctly and make sure that we memset the rest of the segment if the memory size in the ELF file is larger than the file size. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a5xx_gpu.

Re: [Freedreno] [RFC] drm/msm/adreno: clean up gpu bindings

2017-01-24 Thread Jordan Crouse
On Tue, Jan 24, 2017 at 12:11:32PM -0500, Rob Clark wrote: > So, cleaning up the GPU bindings is something that has been on my TODO > list for a while, but always $bigger_fires. Existing bindings are a bit > ugly, but served a purpose when too many of the other drivers the GPU > depends on where

Re: [Freedreno] [PATCH] firmware: qcom_scm: Add set remote state API

2017-01-18 Thread Jordan Crouse
On Mon, Jan 16, 2017 at 11:56:18PM -0600, Andy Gross wrote: > This patch adds a set remote state SCM API. This will be used by the > Venus and GPU subsystems to set state on the remote processors. > > This work was based on two patch sets by Jordan Crouse and Stanimir > Varbanov.

Re: [Freedreno] [pull] drm/msm: msm-next for 4.9

2016-09-21 Thread Jordan Crouse
On Wed, Sep 21, 2016 at 03:23:33AM -0400, Rob Clark wrote: > On Wed, Sep 21, 2016 at 12:35 AM, Rob Clark <robdcl...@gmail.com> wrote: > > On Tue, Sep 20, 2016 at 10:39 AM, Jordan Crouse <jcro...@codeaurora.org> > > wrote: > >> So this isn't how I planned

Re: [Freedreno] [pull] drm/msm: msm-next for 4.9

2016-09-20 Thread Jordan Crouse
So this isn't how I planned on announcing it, but hey, I'm back. > Rob Clark (5): > drm/msm: extend the submit ioctl to pass in flags Renaming 'pipe' to 'flags' would break backwards compatibility - I'm not big fan of 'pipe' either but I would strongly recommend keeping it just to keep

Re: [Freedreno] [RFC] Initial support for the Adreno A5XX

2016-11-08 Thread Jordan Crouse
On Fri, Nov 04, 2016 at 04:44:41PM -0600, Jordan Crouse wrote: > Here is the first blast of patches for support for the fine family of Adreno > A5XX GPUs. These are designed to work against Rob's version of the Linaro > target tree with some additional 8996 clock stuff added in: &

Re: [Freedreno] [PATCH 13/16] drm/msm: gpu: Add support for the GPMU

2016-11-07 Thread Jordan Crouse
On Mon, Nov 07, 2016 at 02:58:01PM +0200, Stanimir Varbanov wrote: > Hi Jordan, > > On 11/05/2016 12:44 AM, Jordan Crouse wrote: > > Most 5XX targets have GPMU (Graphics Power Management Unit) that > > handles a lot of the heavy lifting for power management including &

Re: [Freedreno] [PATCH 04/16] drm: msm: Flush the cache immediately after allocating pages

2016-11-07 Thread Jordan Crouse
On Mon, Nov 07, 2016 at 07:19:24AM -0500, Rob Clark wrote: > On Mon, Nov 7, 2016 at 3:35 AM, Archit Taneja <arch...@codeaurora.org> wrote: > > > > > > On 11/06/2016 07:45 PM, Rob Clark wrote: > >> > >> On Fri, Nov 4, 2016 at 6:44 PM, Jord

[Freedreno] [v2 REALLY] rnndb: a5xx: Update/enhance registers

2016-11-04 Thread Jordan Crouse
Update 5XX registers in the rnndb database ahead of 5XX support for DRM. Changes: v2: Make changes per Rob Clark. Jordan ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno

[Freedreno] [PATCH] rnndb: a5xx: Update/enhance registers

2016-11-04 Thread Jordan Crouse
Add some missing registers from downstream, rename a few to be more accurate and expand the bitfields for CP_INTERRUPT_STATUS, RBBM_STATUS and RBBM_INT0. --- rnndb/adreno/a5xx.xml | 80 +++ 1 file changed, 75 insertions(+), 5 deletions(-) diff

Re: [Freedreno] [PATCH] rnndb: a5xx: Add A540 registers

2016-11-04 Thread Jordan Crouse
On Fri, Nov 04, 2016 at 04:10:15PM -0600, Jordan Crouse wrote: > Flesh out a few of the GPMU registers for A540. > --- > rnndb/adreno/a5xx.xml | 16 +--- > 1 file changed, 13 insertions(+), 3 deletions(-) > > diff --git a/rnndb/adreno/a5xx.xml b/rnndb/adreno/a5xx.x

[Freedreno] [PATCH 05/16] drm/msm: gpu: Return error on hw_init failure

2016-11-04 Thread Jordan Crouse
When the GPU hardware init function fails (like say, ME_INIT timed out) return error instead of blindly continuing on. This gives us a small chance of saving the system before it goes boom. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c

[Freedreno] [PATCH 09/16] drm/msm: gpu Add new gpu register read/write functions

2016-11-04 Thread Jordan Crouse
and write are needed. gpu_rmw() does a read/modify/write on a 32 bit register given a mask and bits to OR in. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 12 ++- drivers/gpu/drm/msm/msm_gpu.h

[Freedreno] [PATCH 01/16] drm/msm: Remove dependency on COMMON_CLK

2016-11-04 Thread Jordan Crouse
Remove an uneeded dependency on COMMON_CLK. Anything that uses COMMON_CLK is already appropriately ifdefed. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/Kco

[Freedreno] [PATCH 11/16] arm64: dts: Add Adreno GPU and GPU smmu definitions

2016-11-04 Thread Jordan Crouse
Add an initial node for the Adreno GPU and it's companion SMMU. The GPU node is mostly complete except for a bare bones power table that will be filled out more completely later. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- arch/arm64/boot/dts/qcom/msm8996.dts

[Freedreno] [PATCH 15/16] drm/msm: Add a quick and dirty PIL loader

2016-11-04 Thread Jordan Crouse
loader that will read a MDT file and get it loaded and authenticated through SCM. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 166 ++ 1 file changed, 166 insertions(+) diff --git a/drivers/gpu/drm/msm/

[Freedreno] [PATCH 10/16] drm/msm: Disable interrupts during init

2016-11-04 Thread Jordan Crouse
Disable the interrupt during the init sequence to avoid having interrupts fired for errors and other things that we are not ready to handle while initializing. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_device.c | 4 drivers/gpu/d

[Freedreno] [PATCH 12/16] drm/msm: gpu: Add A5XX target support

2016-11-04 Thread Jordan Crouse
Add support for the A5XX family of Adreno GPUs. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 820 + drivers/gpu/drm/msm/adreno/a5xx_gpu.h

[Freedreno] [PATCH 08/16] drm/msm: Remove 'src_clk' from adreno configuration

2016-11-04 Thread Jordan Crouse
request 'core_clk' and get the right thing back so zap the anachronism and directly use grp_clk[0] to control the clock rate. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/msm_gpu.c | 36 +--- drivers/gpu/drm/msm/msm_gpu.h | 2 +- 2

[Freedreno] [PATCH 13/16] drm/msm: gpu: Add support for the GPMU

2016-11-04 Thread Jordan Crouse
initalized through a shared register interface and then we mostly get out of its way and let it do its thing. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 64 +- drivers/gpu/d

[Freedreno] [RFC] Initial support for the Adreno A5XX

2016-11-04 Thread Jordan Crouse
Here is the first blast of patches for support for the fine family of Adreno A5XX GPUs. These are designed to work against Rob's version of the Linaro target tree with some additional 8996 clock stuff added in: https://github.com/freedreno/kernel-msm/tree/a5xx In addition, you will also need

[Freedreno] [PATCH 06/16] drm/msm: gpu: Add OUT_TYPE4 and OUT_TYPE7

2016-11-04 Thread Jordan Crouse
Add helper functions for TYPE4 and TYPE7 ME opcodes that replace TYPE0 and TYPE3 starting with the A5XX targets. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 30 ++ 1 file changed, 30 insertions(+) diff

[Freedreno] [PATCH 07/16] drm/msm: Add adreno_gpu_write64()

2016-11-04 Thread Jordan Crouse
oth 32 bit targets (a3xx and a4xx). When a5xx comes it will define valid target registers for the 'hi' option and everything else will just work. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 2 ++ drivers/gpu/drm/msm/adreno/a4xx_gpu.c

[Freedreno] [PATCH 04/16] drm: msm: Flush the cache immediately after allocating pages

2016-11-04 Thread Jordan Crouse
more clearly understand the relationship between shmem kmap, vmap and the swiotlb bounce buffer and we can be smarter about when and how we invalidate the caches. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/msm_gem.c | 21 - 1 file chan

[Freedreno] [PATCH 16/16] drm/msm: gpu: Use the zap shader on 5XX if we can

2016-11-04 Thread Jordan Crouse
stem crash but thats a problem that shows up immediately. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 20 ++ drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 72 ++- 2 files changed, 90 insertions(+), 2 deletion

[Freedreno] [PATCH] rnndb: a5xx: Add A540 registers

2016-11-04 Thread Jordan Crouse
Flesh out a few of the GPMU registers for A540. --- rnndb/adreno/a5xx.xml | 16 +--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/rnndb/adreno/a5xx.xml b/rnndb/adreno/a5xx.xml index 17b3361..6e43330 100644 --- a/rnndb/adreno/a5xx.xml +++ b/rnndb/adreno/a5xx.xml @@

[Freedreno] [v2] rnndb: a5xx: Update/enhance registers

2016-11-04 Thread Jordan Crouse
Updated version of the a5xx registers. Changelog: v2: Remove CP_INTERRUPT_STATUS bitfield per Rob Clark Jordan ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno

[Freedreno] [PATCH 0/1] rnndb: a5xx: Update/enhance registers

2016-10-24 Thread Jordan Crouse
Hi all. I know it is a bit fancy to send a cover email for a single but I thought some introductions were in order. This is the first of I hope many patches enhancing, improving and expanding Adreno support upstream including the brand spanking new Adreno A5XX family. I'll be available as much as

[Freedreno] [PATCH 3/3] drm/msm: gpu Add new gpu register read/write functions

2016-11-22 Thread Jordan Crouse
and write are needed. gpu_rmw() does a read/modify/write on a 32 bit register given a mask and bits to OR in. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 12 ++- drivers/gpu/drm/msm/msm_gpu.h

[Freedreno] [PATCH 2/3] drm/msm: gpu: Return error on hw_init failure

2016-11-22 Thread Jordan Crouse
When the GPU hardware init function fails (like say, ME_INIT timed out) return error instead of blindly continuing on. This gives us a small chance of saving the system before it goes boom. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c

[Freedreno] [PATCH 0/3] drm/msm cleanups

2016-11-22 Thread Jordan Crouse
Here are a few foundational patches to clean up some of the MSM code and get ready for new and awesome things down the line. Jordan Crouse (3): drm/msm: gpu: Cut down the list of "generic" registers to the ones we use drm/msm: gpu: Return error on hw_init failure dr

[Freedreno] [PATCH 1/3] drm/msm: gpu: Cut down the list of "generic" registers to the ones we use

2016-11-22 Thread Jordan Crouse
There are very few register accesses in the common code. Cut down the list of common registers to just those that are used. This saves const space and saves us the effort of maintaining registers for A3XX and A4XX that don't exist or are unused. Signed-off-by: Jordan Crouse <j

[Freedreno] [PATCH 03/12] drm/msm: gpu Add new gpu register read/write functions

2016-11-28 Thread Jordan Crouse
and write are needed. gpu_rmw() does a read/modify/write on a 32 bit register given a mask and bits to OR in. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 12 ++- drivers/gpu/drm/msm/msm_gpu.h

[Freedreno] [PATCH 01/12] drm/msm: gpu: Cut down the list of "generic" registers to the ones we use

2016-11-28 Thread Jordan Crouse
There are very few register accesses in the common code. Cut down the list of common registers to just those that are used. This saves const space and saves us the effort of maintaining registers for A3XX and A4XX that don't exist or are unused. Signed-off-by: Jordan Crouse <j

[Freedreno] [PATCH 11/12] drm/msm: Add a quick and dirty PIL loader

2016-11-28 Thread Jordan Crouse
loader that will read a MDT file and get it loaded and authenticated through SCM. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 166 ++ 1 file changed, 166 insertions(+) diff --git a/drivers/gpu/drm/msm/

[Freedreno] [PATCH 06/12] drm/msm: Remove 'src_clk' from adreno configuration

2016-11-28 Thread Jordan Crouse
request 'core_clk' and get the right thing back so zap the anachronism and directly use grp_clk[0] to control the clock rate. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/msm_gpu.c | 36 +--- drivers/gpu/drm/msm/msm_gpu.h | 2 +- 2

[Freedreno] [PATCH 09/12] drm/msm: gpu: Add support for the GPMU

2016-11-28 Thread Jordan Crouse
initalized through a shared register interface and then we mostly get out of its way and let it do its thing. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 64 +- drivers/gpu/d

[Freedreno] [PATCH 00/12] Adreno A5XX support

2016-11-28 Thread Jordan Crouse
All, here is initial kernel support for the Adreno A5XX family of GPUs found on the QTI Snapdragon 820 and 821 among others. This stack turns on the A5XX hardware and initializes the GPMU (Graphics Power Management Unit) which is a microcontroller to assist with more independent power management.

[Freedreno] [PATCH 08/12] drm/msm: gpu: Add A5XX target support

2016-11-28 Thread Jordan Crouse
Add support for the A5XX family of Adreno GPUs. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 823 + drivers/gpu/drm/msm/adreno/a5xx_gpu.h

[Freedreno] [PATCH 04/12] drm/msm: Add adreno_gpu_write64()

2016-11-28 Thread Jordan Crouse
oth 32 bit targets (a3xx and a4xx). When a5xx comes it will define valid target registers for the 'hi' option and everything else will just work. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 2 ++ drivers/gpu/drm/msm/adreno/a4xx_gpu.c

[Freedreno] [PATCH 12/12] drm/msm: gpu: Use the zap shader on 5XX if we can

2016-11-28 Thread Jordan Crouse
stem crash but thats a problem that shows up immediately. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 72 ++- 1 file changed, 70 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.

[Freedreno] [PATCH 02/12] drm/msm: gpu: Return error on hw_init failure

2016-11-28 Thread Jordan Crouse
When the GPU hardware init function fails (like say, ME_INIT timed out) return error instead of blindly continuing on. This gives us a small chance of saving the system before it goes boom. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c

[Freedreno] [PATCH 07/12] drm/msm: Disable interrupts during init

2016-11-28 Thread Jordan Crouse
Disable the interrupt during the init sequence to avoid having interrupts fired for errors and other things that we are not ready to handle while initializing. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_device.c | 4 drivers/gpu/d

[Freedreno] [PATCH 05/12] drm/msm: gpu: Add OUT_TYPE4 and OUT_TYPE7

2016-11-28 Thread Jordan Crouse
Add helper functions for TYPE4 and TYPE7 ME opcodes that replace TYPE0 and TYPE3 starting with the A5XX targets. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 30 ++ 1 file changed, 30 insertions(+) diff

[Freedreno] [PATCH 10/12] firmware: qcom_scm: Add qcom_scm_gpu_zap_resume()

2016-11-28 Thread Jordan Crouse
Add an interface to trigger the remote processor to reinitialize the GPU zap shader on power-up. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/firmware/qcom_scm-32.c | 5 + drivers/firmware/qcom_scm-64.c | 15 +++ drivers/firmware/qcom_scm.c

Re: [Freedreno] [PATCH 12/12] drm/msm: gpu: Use the zap shader on 5XX if we can

2016-12-06 Thread Jordan Crouse
On Mon, Dec 05, 2016 at 11:57:12AM -0800, Bjorn Andersson wrote: > On Mon 28 Nov 11:28 PST 2016, Jordan Crouse wrote: > > > The A5XX GPU powers on in "secure" mode. In secure mode the GPU can > > only render to buffers that are marked as secure and inaccessible > &

Re: [Freedreno] [PATCH 11/12] drm/msm: Add a quick and dirty PIL loader

2016-12-06 Thread Jordan Crouse
On Mon, Dec 05, 2016 at 11:57:43AM -0800, Bjorn Andersson wrote: > > + if (of_property_read_u32(pdev->dev.of_node, "qcom,pas-id", _id)) { > > This is constant, so define it in the driver. Little bit concerned it might not always be constant but I suppose we can cross that bridge when we get to

Re: [Freedreno] [PATCH 10/12] firmware: qcom_scm: Add qcom_scm_gpu_zap_resume()

2017-01-13 Thread Jordan Crouse
On Fri, Jan 13, 2017 at 11:12:41AM -0600, Andy Gross wrote: > On Mon, Nov 28, 2016 at 12:28:35PM -0700, Jordan Crouse wrote: > > Add an interface to trigger the remote processor to reinitialize the GPU > > zap shader on power-up. > > > > Signed-off-by: Jordan Cro

Re: [Freedreno] [PATCH 10/12] firmware: qcom_scm: Add qcom_scm_gpu_zap_resume()

2017-01-13 Thread Jordan Crouse
On Fri, Jan 13, 2017 at 11:12:41AM -0600, Andy Gross wrote: > On Mon, Nov 28, 2016 at 12:28:35PM -0700, Jordan Crouse wrote: > > Add an interface to trigger the remote processor to reinitialize the GPU > > zap shader on power-up. > > > > Signed-off-by: Jordan Cro

[Freedreno] [PATCH] arm64: dts: Add Adreno GPU and GPU smmu definitions

2016-12-02 Thread Jordan Crouse
Add an initial node for the Adreno GPU and it's companion SMMU. The GPU node is mostly complete except for a bare bones power table that will be filled out more completely later. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- arch/arm64/boot/dts/qcom/msm8996.dts

[Freedreno] [PATCH 1/3] drm/msm: Ensure that the hardware write pointer is valid

2016-12-20 Thread Jordan Crouse
rb->size / 4 and thus result in an out of bounds address to CP_RB_WPTR. The easiest way to fix this is to mask WPTR when writing it to the hardware; it makes the hardware happy and the rest of the ringbuffer math appears to work and there isn't any point in upsetting anything. Signed-off-by: Jord

[Freedreno] [PATCH 0/3] drm/msm: 4.10 fixes

2016-12-20 Thread Jordan Crouse
Here is a short trio of drm/msm fixes suitable for 4.10. The first fixes a hang that occurs when the ring is completely filled, the other two can be triggered through the API and cause mild distress. Jordan Crouse (3): drm/msm: Ensure that the hardware write pointer is valid drm/msm: Put

[Freedreno] [PATCH 2/3] drm/msm: Put back the vaddr in submit_reloc()

2016-12-20 Thread Jordan Crouse
The error cases in submit_reloc() need to put back the virtual address of the bo before failling. Add a single failure path for the function. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/msm_gem_submit.c | 15 +-- 1 file changed, 9 insertions

[Freedreno] [PATCH 3/3] drm/msm: Verify that MSM_SUBMIT_BO_FLAGS are set

2016-12-20 Thread Jordan Crouse
For every submission buffer object one of MSM_SUBMIT_BO_WRITE and MSM_SUBMIT_BO_READ must be set (and nothing else). If we allowed zero then the buffer object would never get queued to be unreferenced. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/msm_gem_su

[Freedreno] [PATCH 2/6] drm/msm: gpu: Use the zap shader on 5XX if we can

2017-04-12 Thread Jordan Crouse
stem crash but thats a problem that shows up immediately. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 72 ++- 1 file changed, 70 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.

[Freedreno] [PATCH 0/6] drm: msm: A5XX zap shader

2017-04-12 Thread Jordan Crouse
the changes that Bjorn requested and a bit more clean up to rely on the device tree less as is our current plan of action. I am not at all oppposed to squashing these into one big change or two moderate changes if it makes life easier. Jordan Crouse (6): drm/msm: Add a quick and dirty PIL loader drm

[Freedreno] [PATCH 3/6] drm/msm: Improve the zap shader

2017-04-12 Thread Jordan Crouse
Simply the code use snprintf correctly and make sure that we memset the rest of the segment if the memory size in the ELF file is larger than the file size. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 70 +---

[Freedreno] [PATCH 4/6] drm/msm: Create a child device for the zap shader

2017-04-12 Thread Jordan Crouse
Currently we abuse the platform device engine to create a platform device for the zap shader subnode so that we can isolate the reserved memory away from the parent GPU device. It is much safer to create and register a simple child device and use that instead. Signed-off-by: Jordan Crouse <j

[Freedreno] [PATCH 6/6] drm/msm: Document the zap-shader subnode for the GPU

2017-04-12 Thread Jordan Crouse
The 'zap-shader' subnode is used to define a phandle for the PIL memory region that is required to load GPU secure firwmare images (known as the "zap shader"). Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- Documentation/devicetree/bindings/display/msm/gpu.txt | 13

[Freedreno] [PATCH 1/6] drm/msm: Add a quick and dirty PIL loader

2017-04-12 Thread Jordan Crouse
loader that will read a MDT file and get it loaded and authenticated through SCM. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 166 ++ 1 file changed, 166 insertions(+) diff --git a/drivers/gpu/drm/msm/

[Freedreno] [PATCH 5/6] drm/msm: Move zap shader firmware name to the device table

2017-04-12 Thread Jordan Crouse
The zap shader firmware name is not platform specific. Move it to the device table instead. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 24 drivers/gpu/drm/msm/adreno/adreno_device.c | 1 + drivers/gpu/d

Re: [Freedreno] [PATCH 3/3] drm/msm: Fix compilation error when CONFIG_DEBUG_FS undefined

2017-03-06 Thread Jordan Crouse
warning: (near initialization > for ‘funcs.base’) [enabled by default] > make[5]: *** [drivers/gpu/drm/msm/adreno/a5xx_gpu.o] Error 1 > make[4]: *** [drivers/gpu/drm/msm] Error 2 > make[4]: *** Waiting for unfinished jobs > > Fixes: b5f103ab98c7 ("drm/msm: gpu

[Freedreno] [PATCH 3/7] iommu/arm-smmu: Add support for TTBR1

2017-03-07 Thread Jordan Crouse
/unmap operations will automatically use the appropriate pagetable based on the specified iova and the existing mask. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/iommu/arm-smmu.c | 19 - drivers/iommu/io-pgtable-arm.c

[Freedreno] [PATCH 5/7] iommu/arm-smmu: add support for TTBR0 attribute

2017-03-07 Thread Jordan Crouse
From: Jeremy Gebben <jgeb...@codeaurora.org> Add support to return the value of the TTBR0 register in response to a request via DOMAIN_ATTR_TTBR0. Signed-off-by: Jeremy Gebben <jgeb...@codeaurora.org> Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/iom

[Freedreno] [PATCH 1/4] drm/msm: Fix wrong pointer check in a5xx_destroy

2017-03-07 Thread Jordan Crouse
Instead of checking for a5xx_gpu->gpmu_iova during destroy we accidently check a5xx_gpu->gpmu_bo. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/dr

[Freedreno] [PATCH 0/4] drm/msm: Fixes for 4.11

2017-03-07 Thread Jordan Crouse
Hey Rob, here are a handful of things that might be fixable for 4.11 but if not consider them for -next. Jordan Jordan Crouse (4): drm/msm: Fix wrong pointer check in a5xx_destroy drm/msm: Don't increase priv->num_aspaces until we know that it fits drm/msm: Pass interrupt sta

[Freedreno] [PATCH 2/4] drm/msm: Don't increase priv->num_aspaces until we know that it fits

2017-03-07 Thread Jordan Crouse
priv->num_aspaces is increased and then checked to see if it still fits in the priv->aspace array. If it doesn't, we warn and exit but priv->num_aspaces remains incremented. Don't incremement the count until we know that it fits in the array. Signed-off-by: Jordan Crouse <jcro...@co

[Freedreno] [PATCH 4/4] drm/msm: Support 64 bit iova in RD_CMDSTREAM_ADDR

2017-03-07 Thread Jordan Crouse
Output the upper 32 bits of a 64 bit iova in the RD_CMDSTREAM_ADDR section while maintaining backwards compatibility for tools that only understand 32 bit iovas. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/msm_rd.c | 4 ++-- 1 file changed, 2 insertions

[Freedreno] [v2] [PATCH 00/11] drm/msm: A5XX preemption

2017-03-07 Thread Jordan Crouse
Here is v2 of the preemption series - Changes: * Refactored API in DRM_IOCTL_MSM_GEM_INFO (Thanks Emil Velikov) * Removed preemption worker and fixed atomics (Thanks Stephen Boyd) * Various fixes and improvements based on testing Thanks! Jordan Jordan Crouse (11): drm/msm: Make sure

[Freedreno] [PATCH 07/11] drm/msm: Remove memptrs->wptr

2017-03-07 Thread Jordan Crouse
memptrs->wptr seems to be unused. Remove it to avoid confusing the upcoming preemption code. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 --- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 - 2 files changed, 4 deletions(-) d

[Freedreno] [PATCH 0/7] RFC: iommu/arm-smmu-v2: Dynamic domains

2017-03-07 Thread Jordan Crouse
an Jeremy Gebben (2): iommu: introduce TTBR0 domain attribute iommu/arm-smmu: add support for TTBR0 attribute Jordan Crouse (4): iommu: Add DOMAIN_ATTR_ENABLE_TTBR1 iommu/arm-smmu: Add support for TTBR1 iommu: Add dynamic domains iommu/arm-smmu: add support for dynamic domains Mitchel Humphe

[Freedreno] [PATCH 7/7] iommu/arm-smmu: add support for dynamic domains

2017-03-07 Thread Jordan Crouse
s restored at the end of the switch operation. Signed-off-by: Jeremy Gebben <jgeb...@codeaurora.org> Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/iommu/arm-smmu.c | 157 --- 1 file changed, 136 insertions(+), 21 deletions(-)

[Freedreno] [PATCH 6/7] iommu: Add dynamic domains

2017-03-07 Thread Jordan Crouse
-dynamic domains. The domains will share configuration (pagetable format, context bank, etc). Dynamic domains do not modify the hardware directly - they are typically a wrapper for the pagetable memory and facilitate using the other IOMMU APIs to map and unmap buffers. Signed-off-by: Jordan Crouse <j

[Freedreno] [PATCH 2/7] iommu: Add DOMAIN_ATTR_ENABLE_TTBR1

2017-03-07 Thread Jordan Crouse
safely. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- include/linux/iommu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 436dc21..d537cc9 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -114,6

[Freedreno] [PATCH 4/7] iommu: introduce TTBR0 domain attribute

2017-03-07 Thread Jordan Crouse
format. The domain must be attached before TTBR0 may be queried. Signed-off-by: Jeremy Gebben <jgeb...@codeaurora.org> Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- include/linux/iommu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/iommu.h b/include/linux/iom

[Freedreno] [PATCH 01/11] drm/msm: Make sure to detach the MMU during GPU cleanup

2017-03-07 Thread Jordan Crouse
We should be detaching the MMU before destroying the address space. To do this cleanly, the detach has to happen in adreno_gpu_cleanup() because it needs access to structs in adreno_gpu.c. Plus it is better symmetry to have the attach and detach at the same code level. Signed-off-by: Jordan

[Freedreno] [PATCH 05/11] drm/msm: get an iova from the address space instead of an id

2017-03-07 Thread Jordan Crouse
index into a list of domains, we need to maintain a list of them. Luckily the list will be pretty small; even with dynamic address spaces we wouldn't ever see more than two or three. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 8 +- d

[Freedreno] [PATCH 02/11] drm/msm: Improve the zap shader

2017-03-07 Thread Jordan Crouse
Simply the code, use snprintf correct and make sure that we memset the rest of the segment if the memory size in the ELF file is larger than the file size. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 +- drivers/gpu/drm/msm/

[Freedreno] [PATCH 08/11] drm/msm: Support multiple ringbuffers

2017-03-07 Thread Jordan Crouse
specific so this code just allows for the possibility but still only defines one ringbuffer for each target family. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 9 +- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 9 +- drivers/gpu/drm/msm/

[Freedreno] [PATCH 09/11] drm/msm: Shadow current pointer in the ring until command is complete

2017-03-07 Thread Jordan Crouse
load for non-preemption targets should be minimal. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 +++-- drivers/gpu/drm/msm/msm_ringbuffer.c| 1 + drivers/gpu/drm/msm/msm_ringbuffer.h| 12 3 files chang

[Freedreno] [PATCH 10/11] drm/msm: Make the value of RB_CNTL (almost) generic

2017-03-07 Thread Jordan Crouse
but that only needs to be done once and doesn't affect A5XX so we can or in the value at init time. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 12 +++- drivers/gpu/drm/msm/msm_gpu.h | 5 + 2 files chang

[Freedreno] [PATCH 06/11] drm/msm: Add a struct to pass configuration to msm_gpu_init()

2017-03-07 Thread Jordan Crouse
The amount of information that we need to pass into msm_gpu_init() is steadily increasing, so add a new struct to stabilize the function call and make it easier to add new configuration down the line. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/

[Freedreno] [PATCH 5/6] drm/msm: gpu: Use OPP tables if we can

2017-03-07 Thread Jordan Crouse
If a OPP table is defined for the GPU device in the device tree use that in lieu of the downstream style GPU frequency table. If we do use the downstream table convert it to a OPP table so that we can take advantage of the OPP lookup facilities later. Signed-off-by: Jordan Crouse <j

[Freedreno] [PATCH 2/6] drm/msm: Reference count address spaces

2017-03-07 Thread Jordan Crouse
their addresses. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c | 2 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 2 +- drivers/gpu/drm/msm/msm_drv.h | 3 ++- drivers/gpu/drm/msm/msm

[Freedreno] [PATCH 6/6] msm/drm: gpu: Dynamically locate the clocks from the device tree

2017-03-07 Thread Jordan Crouse
Instead of using a fixed list of clock names use the clock-names list in the device tree to discover and get the list of clocks that we need. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/msm_gpu.c | 76 ++- drivers/g

[Freedreno] [PATCH 2/6] drm/msm: Pass the MMU domain index in struct msm_file_private

2017-03-07 Thread Jordan Crouse
Pass the index of the MMU domain in struct msm_file_private instead of assuming gpu->id throughout the submit path. Signed-off-by: Jordan Crouse <jcro...@codeaurora.org> --- drivers/gpu/drm/msm/msm_drv.c| 2 ++ drivers/gpu/drm/msm/msm_drv.h| 6 +- drivers/gp

  1   2   3   4   5   >