On Mon, Jan 30, 2017 at 01:35:47PM -0500, Rob Clark wrote:
> On Mon, Jan 30, 2017 at 1:21 PM, Eric Anholt wrote:
> > Rob Clark writes:
> >
> >> The plan is to use the OPP bindings. For now, remove the documentation
> >> for qcom,gpu-pwrlevels, and make the
On Thu, Jan 26, 2017 at 05:03:54PM -0500, Rob Clark wrote:
> On Thu, Jan 26, 2017 at 4:09 PM, Rob Herring wrote:
> > On Thu, Jan 26, 2017 at 1:51 PM, Rob Clark wrote:
> >> On Thu, Jan 26, 2017 at 2:11 PM, Rob Herring wrote:
> >>> On Tue,
Modify the 'pad' member of struct drm_msm_gem_info to 'hint'. If the
user sets 'hint' to non-zero it means that they want a IOVA for the
GEM object instead of a mmap() offset. Return the iova in the 'offset'
member.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/d
There isn't any generic code that uses ->idle so remove it.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 4 ++--
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 4 ++--
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 9 -
drivers/gp
index into a list of domains, we need to
maintain a list of them. Luckily the list will be pretty small;
even with dynamic address spaces we wouldn't ever see more than
two or three.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 8 +-
d
We should be detaching the MMU before destroying the address
space. To do this cleanly, the detach has to happen in
adreno_gpu_cleanup() because it needs access to structs
in adreno_gpu.c. Plus it is better symmetry to have
the attach and detach at the same code level.
Signed-off-by: Jordan
memptrs->wptr seems to be unused. Remove it to avoid
confusing the upcoming preemption code.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ---
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 -
2 files changed, 4 deletions(-)
d
The amount of information that we need to pass into msm_gpu_init()
is steadily increasing, so add a new struct to stabilize the function
call and make it easier to add new configuration down the line.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/
but that only needs to be done once and doesn't
affect A5XX so we can or in the value at init time.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 12 +++-
drivers/gpu/drm/msm/msm_gpu.h | 5 +
2 files chang
Simply the code, use snprintf correctly and make sure that we memset
the rest of the segment if the memory size in the ELF file is larger
than the file size.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.
On Tue, Jan 24, 2017 at 12:11:32PM -0500, Rob Clark wrote:
> So, cleaning up the GPU bindings is something that has been on my TODO
> list for a while, but always $bigger_fires. Existing bindings are a bit
> ugly, but served a purpose when too many of the other drivers the GPU
> depends on where
On Mon, Jan 16, 2017 at 11:56:18PM -0600, Andy Gross wrote:
> This patch adds a set remote state SCM API. This will be used by the
> Venus and GPU subsystems to set state on the remote processors.
>
> This work was based on two patch sets by Jordan Crouse and Stanimir
> Varbanov.
So this isn't how I planned on announcing it, but hey, I'm back.
> Rob Clark (5):
> drm/msm: extend the submit ioctl to pass in flags
Renaming 'pipe' to 'flags' would break backwards compatibility - I'm not big
fan of 'pipe' either but I would strongly recommend keeping it just to keep
On Fri, Nov 04, 2016 at 04:44:41PM -0600, Jordan Crouse wrote:
> Here is the first blast of patches for support for the fine family of Adreno
> A5XX GPUs. These are designed to work against Rob's version of the Linaro
> target tree with some additional 8996 clock stuff added in:
&
On Mon, Nov 07, 2016 at 02:58:01PM +0200, Stanimir Varbanov wrote:
> Hi Jordan,
>
> On 11/05/2016 12:44 AM, Jordan Crouse wrote:
> > Most 5XX targets have GPMU (Graphics Power Management Unit) that
> > handles a lot of the heavy lifting for power management including
&
Update 5XX registers in the rnndb database ahead of 5XX support for DRM.
Changes:
v2: Make changes per Rob Clark.
Jordan
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
Add some missing registers from downstream, rename a few to be more
accurate and expand the bitfields for CP_INTERRUPT_STATUS, RBBM_STATUS
and RBBM_INT0.
---
rnndb/adreno/a5xx.xml | 80 +++
1 file changed, 75 insertions(+), 5 deletions(-)
diff
Remove an uneeded dependency on COMMON_CLK. Anything that uses
COMMON_CLK is already appropriately ifdefed.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/Kco
Add an initial node for the Adreno GPU and it's companion
SMMU. The GPU node is mostly complete except for a bare
bones power table that will be filled out more completely
later.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
arch/arm64/boot/dts/qcom/msm8996.dts
loader that will read a MDT file and get
it loaded and authenticated through SCM.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 166 ++
1 file changed, 166 insertions(+)
diff --git a/drivers/gpu/drm/msm/
Disable the interrupt during the init sequence to avoid having
interrupts fired for errors and other things that we are not
ready to handle while initializing.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 4
drivers/gpu/d
Add support for the A5XX family of Adreno GPUs.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 820 +
drivers/gpu/drm/msm/adreno/a5xx_gpu.h
request 'core_clk' and
get the right thing back so zap the anachronism and directly
use grp_clk[0] to control the clock rate.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/msm_gpu.c | 36 +---
drivers/gpu/drm/msm/msm_gpu.h | 2 +-
2
oth 32 bit
targets (a3xx and a4xx). When a5xx comes it will define valid target
registers for the 'hi' option and everything else will just work.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 2 ++
drivers/gpu/drm/msm/adreno/a4xx_gpu.c
stem crash but thats a problem
that shows up immediately.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 20 ++
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 72 ++-
2 files changed, 90 insertions(+), 2 deletion
and write are needed.
gpu_rmw() does a read/modify/write on a 32 bit register given a mask
and bits to OR in.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 12 ++-
drivers/gpu/drm/msm/msm_gpu.h
When the GPU hardware init function fails (like say, ME_INIT timed
out) return error instead of blindly continuing on. This gives us
a small chance of saving the system before it goes boom.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a3xx_gpu.c
Here are a few foundational patches to clean up some of the MSM code
and get ready for new and awesome things down the line.
Jordan Crouse (3):
drm/msm: gpu: Cut down the list of "generic" registers to the ones we use
drm/msm: gpu: Return error on hw_init failure
dr
and write are needed.
gpu_rmw() does a read/modify/write on a 32 bit register given a mask
and bits to OR in.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 12 ++-
drivers/gpu/drm/msm/msm_gpu.h
There are very few register accesses in the common code. Cut down
the list of common registers to just those that are used. This
saves const space and saves us the effort of maintaining registers
for A3XX and A4XX that don't exist or are unused.
Signed-off-by: Jordan Crouse <j
loader that will read a MDT file and get
it loaded and authenticated through SCM.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 166 ++
1 file changed, 166 insertions(+)
diff --git a/drivers/gpu/drm/msm/
request 'core_clk' and
get the right thing back so zap the anachronism and directly
use grp_clk[0] to control the clock rate.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/msm_gpu.c | 36 +---
drivers/gpu/drm/msm/msm_gpu.h | 2 +-
2
initalized through a shared register
interface and then we mostly get out of its way and let it do
its thing.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 64 +-
drivers/gpu/d
All, here is initial kernel support for the Adreno A5XX family of
GPUs found on the QTI Snapdragon 820 and 821 among others.
This stack turns on the A5XX hardware and initializes the GPMU
(Graphics Power Management Unit) which is a microcontroller
to assist with more independent power management.
Add support for the A5XX family of Adreno GPUs.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 823 +
drivers/gpu/drm/msm/adreno/a5xx_gpu.h
oth 32 bit
targets (a3xx and a4xx). When a5xx comes it will define valid target
registers for the 'hi' option and everything else will just work.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 2 ++
drivers/gpu/drm/msm/adreno/a4xx_gpu.c
stem crash but thats a problem
that shows up immediately.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 72 ++-
1 file changed, 70 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.
Disable the interrupt during the init sequence to avoid having
interrupts fired for errors and other things that we are not
ready to handle while initializing.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 4
drivers/gpu/d
Add helper functions for TYPE4 and TYPE7 ME opcodes that replace
TYPE0 and TYPE3 starting with the A5XX targets.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 30 ++
1 file changed, 30 insertions(+)
diff
Add an interface to trigger the remote processor to reinitialize the GPU
zap shader on power-up.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/firmware/qcom_scm-32.c | 5 +
drivers/firmware/qcom_scm-64.c | 15 +++
drivers/firmware/qcom_scm.c
On Mon, Dec 05, 2016 at 11:57:12AM -0800, Bjorn Andersson wrote:
> On Mon 28 Nov 11:28 PST 2016, Jordan Crouse wrote:
>
> > The A5XX GPU powers on in "secure" mode. In secure mode the GPU can
> > only render to buffers that are marked as secure and inaccessible
> &
On Mon, Dec 05, 2016 at 11:57:43AM -0800, Bjorn Andersson wrote:
> > + if (of_property_read_u32(pdev->dev.of_node, "qcom,pas-id", _id)) {
>
> This is constant, so define it in the driver.
Little bit concerned it might not always be constant but I suppose we can cross
that bridge when we get to
On Fri, Jan 13, 2017 at 11:12:41AM -0600, Andy Gross wrote:
> On Mon, Nov 28, 2016 at 12:28:35PM -0700, Jordan Crouse wrote:
> > Add an interface to trigger the remote processor to reinitialize the GPU
> > zap shader on power-up.
> >
> > Signed-off-by: Jordan Cro
On Fri, Jan 13, 2017 at 11:12:41AM -0600, Andy Gross wrote:
> On Mon, Nov 28, 2016 at 12:28:35PM -0700, Jordan Crouse wrote:
> > Add an interface to trigger the remote processor to reinitialize the GPU
> > zap shader on power-up.
> >
> > Signed-off-by: Jordan Cro
Add an initial node for the Adreno GPU and it's companion
SMMU. The GPU node is mostly complete except for a bare
bones power table that will be filled out more completely
later.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
arch/arm64/boot/dts/qcom/msm8996.dts
rb->size / 4 and thus result in an out of bounds address to CP_RB_WPTR.
The easiest way to fix this is to mask WPTR when writing it to the
hardware; it makes the hardware happy and the rest of the ringbuffer
math appears to work and there isn't any point in upsetting anything.
Signed-off-by: Jord
Here is a short trio of drm/msm fixes suitable for 4.10. The first
fixes a hang that occurs when the ring is completely filled, the
other two can be triggered through the API and cause mild distress.
Jordan Crouse (3):
drm/msm: Ensure that the hardware write pointer is valid
drm/msm: Put
The error cases in submit_reloc() need to put back the virtual
address of the bo before failling. Add a single failure path
for the function.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/msm_gem_submit.c | 15 +--
1 file changed, 9 insertions
For every submission buffer object one of MSM_SUBMIT_BO_WRITE
and MSM_SUBMIT_BO_READ must be set (and nothing else). If we
allowed zero then the buffer object would never get queued to
be unreferenced.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/msm_gem_su
stem crash but thats a problem
that shows up immediately.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 72 ++-
1 file changed, 70 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.
the changes that Bjorn requested and a bit
more clean up to rely on the device tree less as is our current plan of action.
I am not at all oppposed to squashing these into one big change or two moderate
changes if it makes life easier.
Jordan Crouse (6):
drm/msm: Add a quick and dirty PIL loader
drm
Simply the code use snprintf correctly and make sure that we memset
the rest of the segment if the memory size in the ELF file is larger
than the file size.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 70 +---
Currently we abuse the platform device engine to create a platform
device for the zap shader subnode so that we can isolate the
reserved memory away from the parent GPU device.
It is much safer to create and register a simple child device and use
that instead.
Signed-off-by: Jordan Crouse <j
The 'zap-shader' subnode is used to define a phandle for the
PIL memory region that is required to load GPU secure firwmare images
(known as the "zap shader").
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
Documentation/devicetree/bindings/display/msm/gpu.txt | 13
loader that will read a MDT file and get
it loaded and authenticated through SCM.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 166 ++
1 file changed, 166 insertions(+)
diff --git a/drivers/gpu/drm/msm/
The zap shader firmware name is not platform specific. Move it
to the device table instead.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 24
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
drivers/gpu/d
warning: (near initialization
> for ‘funcs.base’) [enabled by default]
> make[5]: *** [drivers/gpu/drm/msm/adreno/a5xx_gpu.o] Error 1
> make[4]: *** [drivers/gpu/drm/msm] Error 2
> make[4]: *** Waiting for unfinished jobs
>
> Fixes: b5f103ab98c7 ("drm/msm: gpu
/unmap operations will automatically use the appropriate
pagetable based on the specified iova and the existing mask.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/iommu/arm-smmu.c | 19 -
drivers/iommu/io-pgtable-arm.c
From: Jeremy Gebben <jgeb...@codeaurora.org>
Add support to return the value of the TTBR0 register in response
to a request via DOMAIN_ATTR_TTBR0.
Signed-off-by: Jeremy Gebben <jgeb...@codeaurora.org>
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/iom
Instead of checking for a5xx_gpu->gpmu_iova during destroy we
accidently check a5xx_gpu->gpmu_bo.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/dr
an
Jeremy Gebben (2):
iommu: introduce TTBR0 domain attribute
iommu/arm-smmu: add support for TTBR0 attribute
Jordan Crouse (4):
iommu: Add DOMAIN_ATTR_ENABLE_TTBR1
iommu/arm-smmu: Add support for TTBR1
iommu: Add dynamic domains
iommu/arm-smmu: add support for dynamic domains
Mitchel Humphe
s restored
at the end of the switch operation.
Signed-off-by: Jeremy Gebben <jgeb...@codeaurora.org>
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/iommu/arm-smmu.c | 157 ---
1 file changed, 136 insertions(+), 21 deletions(-)
-dynamic domains. The domains will share configuration
(pagetable format, context bank, etc). Dynamic domains do not
modify the hardware directly - they are typically a
wrapper for the pagetable memory and facilitate using the other
IOMMU APIs to map and unmap buffers.
Signed-off-by: Jordan Crouse <j
safely.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
include/linux/iommu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 436dc21..d537cc9 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -114,6
format. The domain must be
attached before TTBR0 may be queried.
Signed-off-by: Jeremy Gebben <jgeb...@codeaurora.org>
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
include/linux/iommu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/iommu.h b/include/linux/iom
We should be detaching the MMU before destroying the address
space. To do this cleanly, the detach has to happen in
adreno_gpu_cleanup() because it needs access to structs
in adreno_gpu.c. Plus it is better symmetry to have
the attach and detach at the same code level.
Signed-off-by: Jordan
index into a list of domains, we need to
maintain a list of them. Luckily the list will be pretty small;
even with dynamic address spaces we wouldn't ever see more than
two or three.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 8 +-
d
-by: Jordan Crouse <jcro...@codeaurora.org>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 64 ++-
drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 17
drivers/gpu/drm/msm/adreno/a5xx_preempt.
-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 3af29cae..6361193 100644
--- a/drivers/gpu/d
.
- multiple ringbuffer preemption - provide for multiple ringbuffers,
allow the user to select a ringbuffer to submit on and preempt
between the different priorities. You've seen some of this code
before but some of our newer features have cleaned things up
significantly.
Jordan Crouse
There are some use cases wherein we need to turn off hardware clock
gating before reading certain registers. Modify the A5XX HWCG function
to allow user to enable or disable clock gating at will.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.
The 0xf400 and 0xf800 ranges are in the RBBM_SECVID block which may
be protected from CPU access. Skip dumping them since they are minimally
useful for debugging and they aren't worth a system hang.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a5xx
Fix a typo in msm_ioctl_gem_submit - check args->flags for the
MSM_SUBMIT_NO_IMPLICIT flag instead of args->fence.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/msm_gem_submit.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/dri
Nearly all of the buffer allocations for kernel allocate an buffer object,
virtual address and GPU iova at the same time. Make a helper function to
handle the details.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 22 +++-
d
On A5XX GPU hardware clock gating needs to be turned off before
reading certain GPU registers via AHB. Turn off HWCG before calling
adreno_show() to safely dump all the registers without a system hang.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/
In order to manage ringbuffer priority to its fullest userspace
should know how many ringbuffers it has to work with. Add a
parameter to return the number of active rings.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++
include/ua
*gpu)
> }
>
> /* Set up a child device to "own" the zap shader */
This now incorrect comment can be zapped (pun intended).
> -static int a5xx_zap_shader_dev_init(struct device *parent, struct device
> *dev)
> -{
> - struct device_node *node;
> - int ret;
&g
ial buffer overflow issue")
> Signed-off-by: Dan Carpenter <dan.carpen...@oracle.com>
Indeed. Thanks for the catch.
Acked-by: Jordan Crouse <jcro...@codeaurora.org>
> diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
> b/drivers/gpu/drm/msm/msm_gem_submit.c
> index 6
e6d38 ("drm/msm: gpu: Enable zap shader for A5XX")
> Signed-off-by: Arnd Bergmann <a...@arndb.de>
Seems reasonable to me if Bjorn agrees.
Acked-by: Jordan Crouse <jcro...@codeaurora.org>
> ---
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 +++-
> 1 file changed, 3 inser
Hey Rob, here is a late breaking overflow fix suitable for sending up to Linus
for 4.12 if you are so inclined.
Kasin Li (1):
drm/msm: Fix potential buffer overflow issue
drivers/gpu/drm/msm/msm_gem_submit.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
--
1.9.1
From: Kasin Li <dong...@codeaurora.org>
In function submit_create, if nr_cmds or nr_bos is assigned with
negative value, the allocated buffer may be small than intended.
Using this buffer will lead to buffer overflow issue.
Signed-off-by: Kasin Li <dong...@codeaurora.org>
Signed-of
;
> + drm_gem_private_object_init(dev, obj, size);
> +
> + msm_obj->pages = get_pages(obj);
> + pages = get_pages(obj);
> + if (IS_ERR(pages)) {
> + ret = PTR_ERR(pages);
> + goto fail;
> +
ned-off-by: Rob Clark <robdcl...@gmail.com>
Acked-by: Jordan Crouse <jcro...@codeaurora.org>
> ---
> drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 10 --
> 1 file changed, 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
> b/driv
On Tue, Jun 13, 2017 at 02:49:45PM -0400, Rob Clark wrote:
> No functional change, that will come later. But this will make it
> easier to deal with dynamically created address spaces (ie. per-
> process pagetables for gpu).
>
> Signed-off-by: Rob Clark <robdcl...@gmail.com&
more sense.
Acked-by: Jordan Crouse <jcro...@codeaurora.org>
> ---
> drivers/gpu/drm/msm/msm_gem.c | 138
> +-
> drivers/gpu/drm/msm/msm_gem.h | 4 +-
> 2 files changed, 99 insertions(+), 43 deletions(-)
>
> diff --git a/driver
specific
so this code just allows for the possibility but still only defines
one ringbuffer for each target family.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 9 +-
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 9 +-
drivers/gpu/drm/msm/
Implement preemption for A5XX targets - this allows multiple
ringbuffers for different priorities with automatic preemption
of a lower priority ringbuffer if a higher one is ready.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/Makefile
The ioctl array is sparsely populated but the compiler will make sure
that it is sufficiently sized for all the values that we have so we
can safely use ARRAY_SIZE() instead of having a constantly changing
#define in the uapi header.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.
if we did this is where it would
go so there is no harm in laying down the basis for the future.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/msm_drv.c| 99 +---
drivers/gpu/drm/msm/msm_drv.h| 8 ++-
dri
but that only needs to be done once and doesn't
affect A5XX so we can or in the value at init time.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 12 +++-
drivers/gpu/drm/msm/msm_gpu.h | 5 +
2 files chang
memptrs->wptr seems to be unused. Remove it to avoid
confusing the upcoming preemption code.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ---
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 -
2 files changed, 4 deletions(-)
d
There isn't any generic code that uses ->idle so remove it.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 4 ++--
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 4 ++--
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 9 -
drivers/gp
On Thu, Oct 05, 2017 at 11:08:12AM +0100, Jean-Philippe Brucker wrote:
> Hi Jordan,
>
> On 04/10/17 20:43, Jordan Crouse wrote:
> > Trying to start back up the conversation about multiple address
> > spaces for IOMMU devices. If you will remember Jean-Philippe posted
On Mon, Oct 16, 2017 at 11:27:47AM -0400, Rob Clark wrote:
> Previously, in an effort to defer initializing the gpu until firmware
> was available (ie. rootfs mounted), the gpu was not loaded at when the
> subdevice was bound. Which resulted that clks/etc were requested in a
> place that devm
/TTBR1 virtual address range of 36
bits the memory map will look like this:
TTBR0 [0x:0x0007]
TTBR1 [0xFFF8:0x]
The map/unmap operations will automatically use the appropriate
pagetable for the given iova.
Signed-off-by: Jordan Crouse
Now that the priority must be set in the submitqueue we can check
at create time that the requested priority is valid.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/msm_gem_submit.c | 8 +---
drivers/gpu/drm/msm/msm_submitqueue.
uffers for processing relocs.
Also remove unused member valid from the struct
msm_gem_submit.
Signed-off-by: Sushmita Susheelendra <ssush...@codeaurora.org>
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/msm_gem_submit.c | 58 +-
T_NONE. This leads to a
GPU stall.
Introduce a new intermediate state PREEMPT_ABORT and
change preempt_trigger() to use gpu's current ring instead of the
ring retrieved from get_next_ring() while in this state.
Signed-off-by: Sharat Masetty <smase...@codeaurora.org>
Signed-off-by: Jordan
the submission.
Print the header for all buffers but only dump the contents for
buffers marked as READ.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/msm_rd.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/g
Instead of passing a mostly unused struct to MSM_DRM_SUBMITQEUUE_CLOSE
we only need to pass the u32 value of the queue ID.
Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
drivers/gpu/drm/msm/msm_drv.c | 4 ++--
drivers/gpu/drm/msm/msm_gpu.h | 1 -
include/uapi/drm/msm_drm.h
1 - 100 of 1060 matches
Mail list logo