this new function.
>
> Signed-off-by: Sharat Masetty
> Reviewed-by: Jordan Crouse
> Signed-off-by: Sai Prakash Ranjan
Rob - this should be safe to pull with msm-next regardless of the merge status
of the iommu side of things. Hopefully everything will be pulled for 5.11 but if
it isn&
On Mon, Oct 26, 2020 at 05:24:03PM +0530, Sai Prakash Ranjan wrote:
> From: Sharat Masetty
>
> The last level system cache can be partitioned to 32 different
> slices of which GPU has two slices preallocated. One slice is
> used for caching GPU buffers and the other slice is used for
> caching th
programming sequence
accordingly.
[1] https://patchwork.freedesktop.org/series/83037/
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 46 +--
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
2 files changed, 37 insertions(+), 10 deletions(-)
diff --git a
On Tue, Oct 27, 2020 at 12:38:02PM +0530, Sai Prakash Ranjan wrote:
> On 2020-10-27 00:24, Jordan Crouse wrote:
> >This is an extension to the series [1] to enable the System Cache (LLC)
> >for
> >Adreno a6xx targets.
> >
> >GPU targets with an MMU-500 attached
;
> Fixes: 8907afb476ac ("drm/msm: Allow a5xx to mark the RPTR shadow as
> privileged")
> Signed-off-by: Marijn Suijten
> Tested-by: AngeloGioacchino Del Regno
>
Way better. Thanks for doing this.
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno
later for even more
extensive GPU side page fault debugging capabilities.
Jordan Crouse (3):
iommu/arm-smmu: Add support for driver IOMMU fault handlers
drm/msm: Add an adreno-smmu-priv callback to get pagefault info
drm/msm: Improve the a6xx page fault handler
drivers/gpu/drm/msm/adreno
Use the new adreno-smmu-priv fault info function to get more SMMU
debug registers and print the current TTBR0 to debug per-instance
pagetables and figure out which GPU block generated the request.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 +-
drivers/gpu/drm
*ERROR* timeout waiting for space in
> ringbuffer 0
>
> in the resume path.
>
> Fixes: d3a569fccfa0 ("drm/msm: a6xx: Use WHERE_AM_I for eligible targets")
> Signed-off-by: Rob Clark
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 ++
ged")
> Signed-off-by: Rob Clark
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12 +++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> b/drivers/gpu/drm/msm/adreno/
On Thu, Nov 12, 2020 at 09:19:04PM +0530, Akhil P Oommen wrote:
> So far a530v2 gpu has support for detecting its supported opps
> based on a fuse value called speed-bin. This patch makes this
> support generic across gpu families. This is in preparation to
> extend speed-bin support to a6x family.
; Cc: David Airlie
> Cc: Daniel Vetter
> Cc: linux-arm-...@vger.kernel.org
> Cc: dri-de...@lists.freedesktop.org
> Cc: freedreno@lists.freedesktop.org
> Signed-off-by: Lee Jones
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
> 1 file change
On Mon, Nov 16, 2020 at 07:40:03PM +0530, Akhil P Oommen wrote:
> On 11/12/2020 10:05 PM, Jordan Crouse wrote:
> >On Thu, Nov 12, 2020 at 09:19:04PM +0530, Akhil P Oommen wrote:
> >>So far a530v2 gpu has support for detecting its supported opps
> >>based on a fuse v
On Sat, Nov 14, 2020 at 11:30:10AM -0800, Rob Clark wrote:
> From: Rob Clark
>
> In situations where the GPU is mostly idle, all or nearly all buffer
> objects will be in the inactive list. But if the system is under memory
> pressure (from something other than GPU), we could still get a lot of
On Sat, Nov 14, 2020 at 10:17:12AM -0500, Jonathan Marek wrote:
> This makes it possible to use the non-coherent cached MSM_BO_CACHED mode,
> which otherwise doesn't provide any method for cleaning/invalidating the
> cache to sync with the device.
>
> Signed-off-by: Jonathan Marek
> ---
> driver
On Sat, Nov 14, 2020 at 11:39:45AM -0800, Rob Clark wrote:
> On Sat, Nov 14, 2020 at 10:58 AM Jonathan Marek wrote:
> >
> > On 11/14/20 1:46 PM, Rob Clark wrote:
> > > On Sat, Nov 14, 2020 at 8:24 AM Christoph Hellwig wrote:
> > >>
> > >> On Sat, Nov 14, 2020 at 10:17:12AM -0500, Jonathan Marek w
later for even more
extensive GPU side page fault debugging capabilities.
v2: Fix comment wording and function pointer check per Rob Clark
Jordan Crouse (3):
iommu/arm-smmu: Add support for driver IOMMU fault handlers
drm/msm: Add an adreno-smmu-priv callback to get pagefault info
drm/msm
Use the new adreno-smmu-priv fault info function to get more SMMU
debug registers and print the current TTBR0 to debug per-instance
pagetables and figure out which GPU block generated the request.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 +-
drivers/gpu/drm
On Fri, Nov 27, 2020 at 06:19:44PM +0530, Akhil P Oommen wrote:
> So far a530v2 gpu has support for detecting its supported opps
> based on a fuse value called speed-bin. This patch makes this
> support generic across gpu families. This is in preparation to
> extend speed-bin support to a6x family.
On Wed, Dec 02, 2020 at 08:53:51PM +0530, Akhil P Oommen wrote:
> On 11/30/2020 10:32 PM, Jordan Crouse wrote:
> >On Fri, Nov 27, 2020 at 06:19:44PM +0530, Akhil P Oommen wrote:
> >>So far a530v2 gpu has support for detecting its supported opps
> >>based on a fuse v
On Mon, Dec 07, 2020 at 04:12:07PM +0530, Akhil P Oommen wrote:
> Some GPUs support different max frequencies depending on the platform.
> To identify the correct variant, we should check the gpu speedbin
> fuse value. Add support for this speedbin detection to a6xx family
> along with the required
ioacchino Del Regno
>
Yep, I can see how this would be not ideal.
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21 -
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +
> 2 files changed, 17 insertions(+), 9 deletions(-)
&
On Mon, Jan 11, 2021 at 09:54:12AM +0530, Sai Prakash Ranjan wrote:
> Hi Rob,
>
> On 2021-01-08 22:16, Rob Clark wrote:
> >On Fri, Jan 8, 2021 at 6:05 AM Sai Prakash Ranjan
> > wrote:
> >>
> >>On 2021-01-08 19:09, Konrad Dybcio wrote:
> Konrad, can you please test this below change without yo
ong with the required fuse details for a618 gpu.
Reviewed-by: Jordan Crouse
> Signed-off-by: Akhil P Oommen
> ---
> Changes from v2:
> 1. Made the changes a6xx specific to save space.
> Changes from v1:
> 1. Added the changes to support a618 sku to the series.
>
een made when porting:
> 4 is the value that's supposed to be passed, but
> log2(4) = 2. Changing the value to 16 (= 2^4) fixes
> the issue.
I like keeping it in human readable values because its easier to visually
identify how many registers are saved without doing math.
Reviewed-
On Wed, Jan 13, 2021 at 07:33:38PM +0100, AngeloGioacchino Del Regno wrote:
> From: Konrad Dybcio
>
> Port over the command from downstream to prevent undefined
> behaviour.
Reviewed-by: Jordan Crouse
> Signed-off-by: Konrad Dybcio
> Signed-off-by: AngeloGi
On Wed, Jan 13, 2021 at 07:33:39PM +0100, AngeloGioacchino Del Regno wrote:
> From: Konrad Dybcio
>
> Port over the command from downstream to prevent undefined
> behaviour.
Reviewed-by: Jordan Crouse
> Signed-off-by: Konrad Dybcio
> Signed-off-by: AngeloGi
65ca5a2cb ("drm/msm: Add A6XX device support")
Because that was my ugly.
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 25 ++---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 8
> drivers/gpu/drm/msm/adreno/a6xx_g
> Cc: sta...@vger.kernel.org # v5.9
The joys of not having a global mutex locking everything.
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> b/
On Wed, Jan 27, 2021 at 03:39:46PM -0800, Eric Anholt wrote:
> Now that the bug is fixed in the minimal way for stable, go make the
> code table-driven.
>
> Signed-off-by: Eric Anholt
There shouldn't be too many more OOB bits, but this is a good cleanup
regardless.
Reviewed-
On Thu, Jan 28, 2021 at 11:17:16AM -0800, Eric Anholt wrote:
> On Thu, Jan 28, 2021 at 10:52 AM Jordan Crouse wrote:
> >
> > On Wed, Jan 27, 2021 at 03:39:44PM -0800, Eric Anholt wrote:
> > > We were using the same force-poweron bit in the two codepaths, so they
> &g
On Mon, Feb 01, 2021 at 08:20:44AM -0800, Rob Clark wrote:
> On Mon, Feb 1, 2021 at 3:16 AM Will Deacon wrote:
> >
> > On Fri, Jan 29, 2021 at 03:12:59PM +0530, Sai Prakash Ranjan wrote:
> > > On 2021-01-29 14:35, Will Deacon wrote:
> > > > On Mon, Jan 11, 2021 at 07:45:04PM +0530, Sai Prakash Ran
Most a6xx targets have security issues that were fixed with new versions
of the microcode(s). Make sure that we are booting with a safe version of
the microcode for the target and print a message and error if not.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 67
Most a6xx targets have security issues that were fixed with new versions
of the microcode(s). Make sure that we are booting with a safe version of
the microcode for the target and print a message and error if not.
v2: Add more informative error messages and fix typos
Signed-off-by: Jordan Crouse
nks. I feel silly that I missed that.
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> i
On Thu, Feb 11, 2021 at 06:50:28PM +0530, Akhil P Oommen wrote:
> On 2/10/2021 6:22 AM, Jordan Crouse wrote:
> >Most a6xx targets have security issues that were fixed with new versions
> >of the microcode(s). Make sure that we are booting with a safe version of
> >the microco
On Wed, Feb 17, 2021 at 07:14:16PM +0530, Akhil P Oommen wrote:
> On 2/17/2021 8:36 AM, Rob Clark wrote:
> >On Tue, Feb 16, 2021 at 12:10 PM Jonathan Marek wrote:
> >>
> >>Ignore nvmem_cell_get() EOPNOTSUPP error in the same way as a ENOENT error,
> >>to fix the case where the kernel was compiled
solid base that we can expand on later for even more
extensive GPU side page fault debugging capabilities.
v3: Always clear FSR even if the target driver is going to handle resume
v2: Fix comment wording and function pointer check per Rob Clark
Jordan Crouse (3):
iommu/arm-smmu: Add support for
Use the new adreno-smmu-priv fault info function to get more SMMU
debug registers and print the current TTBR0 to debug per-instance
pagetables and figure out which GPU block generated the request.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 +-
drivers/gpu/drm
jcrouse at codeaurora.org ha started bouncing. Redirect to a
more permanent address.
Signed-off-by: Jordan Crouse
---
.mailmap | 1 +
1 file changed, 1 insertion(+)
diff --git a/.mailmap b/.mailmap
index 85b93cdefc87..8c489cb1d1ce 100644
--- a/.mailmap
+++ b/.mailmap
@@ -165,6 +165,7 @@ Johan
requirements to accept firmware 0.99.
Ugh, my ugly. .95 is the actual version that fixed it but since .99 is what is
going into the l-f repo it is fine to use that as a baseline.
Acked-by: Jordan Crouse
> Fixes: 8490f02a3ca4 ("drm/msm: a6xx: Make sure the SQE microcode is safe"
On Wed, Mar 24, 2021 at 06:23:52PM -0700, Rob Clark wrote:
> From: Rob Clark
>
> They were reading a counter that was configured to ALWAYS_COUNT (ie.
> cycles that the GPU is doing something) rather than ALWAYS_ON. This
> isn't the thing that userspace is looking for.
Ack
e of this. For
> example, after a suspend userspace needs to recalibrate it's offset
> between CPU and GPU time.
>
Acked-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++
> drivers/gpu/drm/msm/msm_drv.c | 1 +
>
ffer
> space to become available sees partial progress, rather than not
> seeing rptr advance at all until the GPU gets to the end of the
> submit that it is currently chewing on.
Acked-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/g
On Fri, Apr 23, 2021 at 03:08:17PM -0400, Jonathan Marek wrote:
> No one knows what this is for anymore, so just remove it.
Acked-by: Jordan Crouse
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/msm_gem.c | 15 +++
> 1 file changed, 3 insertions(+
s was stil in there.
Acked-by: Jordan Crouse
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++--
> drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +-
> drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 4 ++--
> drivers/gpu/drm/msm/adreno/a
On Fri, Apr 23, 2021 at 03:08:19PM -0400, Jonathan Marek wrote:
> Use the same logic as the userspace mapping.
>
> This fixes msm_rd with cached BOs.
>
Acked-by: Jordan Crouse
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/msm_gem.c | 19 +++-
On Fri, Apr 23, 2021 at 03:08:21PM -0400, Jonathan Marek wrote:
> There shouldn't be any reason to ever use uncached over writecombine,
> so just use writecombine for MSM_BO_UNCACHED.
Extremely correct.
>
> Note: userspace never used MSM_BO_UNCACHED anyway
>
Acked-by: Jord
On Tue, Jun 01, 2021 at 03:47:24PM -0700, Rob Clark wrote:
> From: Rob Clark
>
> For collecting devcoredumps with the SMMU stalled after an iova fault,
> we need to skip the parts of the GPU state which are normally collected
> with the hw crashdumper, since with the SMMU stalled the hw would be
On Tue, Jun 01, 2021 at 03:47:25PM -0700, Rob Clark wrote:
> From: Rob Clark
>
> Wire up support to stall the SMMU on iova fault, and collect a devcore-
> dump snapshot for easier debugging of faults.
>
> Currently this is a6xx-only, but mostly only because so far it is the
> only one using adre
ent translation.
>
> This will be used on the GPU side to "freeze" the GPU while we snapshot
> useful state for devcoredump.
>
Acked-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 33 ++
>
e
> only one using adreno-smmu-priv.
Acked-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 19 +++-
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 38 +++-
> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 42 +
On Wed, May 30, 2018 at 08:19:47PM +0530, Rajesh Yadav wrote:
> dpu_io_util.h is moved from standard include path
> to driver folder, correct the include path in code.
>
> Signed-off-by: Rajesh Yadav
If the previous patch doesn't compile without this fix you should squash them.
> ---
> drivers
On Thu, May 31, 2018 at 12:52:03PM +0530, Sharat Masetty wrote:
> This is needed for hardware revisions which do not rely on the generic
> suspend, resume handlers for power management.
>
> Signed-off-by: Sharat Masetty
> ---
> drivers/gpu/drm/msm/msm_gpu.c | 23 +++
> driver
On Thu, May 31, 2018 at 04:01:51PM +0530, Sharat Masetty wrote:
> This patch adds a simple helper function to help write 64 bit payloads
> to the ringbuffer.
>
> Signed-off-by: Sharat Masetty
> ---
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12
> drivers/gpu/drm/msm/adreno/a5xx_pow
On Mon, May 28, 2018 at 12:38:41PM +0530, Souptick Joarder wrote:
> On Mon, May 21, 2018 at 10:59 PM, Souptick Joarder
> wrote:
> > Use new return type vm_fault_t for fault handler. For
> > now, this is just documenting that the function returns
> > a VM_FAULT value rather than an errno. Once all
Convert some MASK/SHIFT "registers" into bitmasks, correct the bit positions
for GMU_SPTPRAC_PWR_CLK_STATUS and add a few more definitions.
---
rnndb/adreno/a6xx.xml | 134 ++
rnndb/adreno/a6xx_gmu.xml | 4 +-
2 files changed, 79 insertions(+), 59 deletion
Add a helper function to parse the clock names and set up
the bulk data so we can take advantage of the bulk clock
functions instead of rolling our own. This is added
as a helper function so the upcoming a6xx GMU code can
also take avantage of it.
Signed-off-by: Jordan Crouse
---
drivers/gpu
From: Sharat Masetty
Add initial register headers for A6XX targets.
Signed-off-by: Sharat Masetty
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 1784 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 382 +
2 files changed, 2166 insertions
new files]
*** BLURB HERE ***
Jordan Crouse (2):
drm/msm: Add a helper function to parse clock names
drm/msm: Add A6XX device support
Sharat Masetty (1):
drm/msm: Add generated headers for A6XX
drivers/gpu/drm/msm/Makefile |3 +
drivers/gpu/drm/msm/adreno/a6xx.xml.h
HFI (hardware firmware interface)
queue that the CPU uses to communicate with the GMU.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/Makefile |3 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 1174
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 162
On Fri, Jun 08, 2018 at 11:56:04AM +0530, Sharat Masetty wrote:
> This series re-factors the devfreq code a bit in preparation for the upcoming
> A6x related devfreq changes. The code applies cleanly on 4.17 and has been
> verified on DB820C.
>
> V2: Addressed code review comme
of missing firmware.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 23 +-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 0c0eaad68065
, fix issues
identified by smatch]
[v2 - addressed comments from Lucas Stach; added pm_runtime_get_supplier calls
for accesses to the GMU IOMMU; moved to SPDX headers for new files]
Jordan Crouse (4):
drm/msm: Remove pm_runtime operations from msm_iommu
drm/msm: Add a helper function to parse clock
ned-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_iommu.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index b23d33622f37..ccd93ac6a4d8 100644
--- a/drivers/gpu/drm/msm/msm_iommu.c
+++ b/drivers/gpu/drm/msm/msm_iommu.
Add a helper function to parse the clock names and set up
the bulk data so we can take advantage of the bulk clock
functions instead of rolling our own. This is added
as a helper function so the upcoming a6xx GMU code can
also take advantage of it.
Signed-off-by: Jordan Crouse
---
drivers/gpu
HFI (hardware firmware interface)
queue that the CPU uses to communicate with the GMU.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/Makefile |3 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 1172
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 162
From: Sharat Masetty
Add initial register headers for A6XX targets.
Signed-off-by: Sharat Masetty
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 1784 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 382 +
2 files changed, 2166 insertions
On Tue, Jun 12, 2018 at 06:17:44PM -0700, Jeykumar Sankaran wrote:
> Subclass drm private state for DPU for handling driver
> specific data. Adds atomic private object and private object
> lock to dpu kms. Provides helper function to retrieve DPU
> private data from current atomic state.
>
> Signe
On Tue, Jun 12, 2018 at 06:17:47PM -0700, Jeykumar Sankaran wrote:
> Switch to state based resource management. This patch
> overhauls the resource manager and HW allocation methods by
> maintaining the global resource pool and allocated hw
> blocks in respective drm component states.
>
> Global r
On Thu, Jun 14, 2018 at 12:30:35PM +0530, Vivek Gautam wrote:
> Hi Jordan,
>
> On Mon, Jun 11, 2018 at 11:56 PM, Jordan Crouse
> wrote:
> > Now that the IOMMU is the master of it's own power we don't need to bring
> > up the GPU to do IOMMU operations. Thi
On Fri, Jun 15, 2018 at 11:05:57PM -0700, Abhinav Kumar wrote:
> Before adding a DSI node to the private list check if the
> node has a valid device connected to it through an endpoint.
>
> This is required in cases where the chipset supports multiple
> DSI hosts but only one of them is being used
f-by: Thomas Zimmermann
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a5xx_debugfs.c | 4 ++--
> drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +-
> drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 2 +-
> drivers/gpu/drm/msm/msm_gem_submit.c | 4 ++--
> 4 fil
On Mon, Jun 18, 2018 at 03:11:44PM -0700, abhin...@codeaurora.org wrote:
> Hi Jordan
>
> Thanks for the review.
>
> Comments inline.
>
> Abhinav
> On 2018-06-18 07:23, Jordan Crouse wrote:
> >On Fri, Jun 15, 2018 at 11:05:57PM -0700, Abhinav Kumar wrote:
>
rse ]
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c | 57 ++
drivers/gpu/drm/msm/msm_drv.h | 4 +++
drivers/gpu/drm/msm/msm_gpu.c | 58 ++-
drivers/gpu/drm/msm/msm_gpu.h | 2 +-
4 files changed, 72 insertions(+),
of missing firmware.
[v2 - fix compile error caused by adreno_load_fw declared static in
adreno_gpu ]
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 23 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.c| 2 +-
drivers/gpu/drm/msm/adreno
From: Sharat Masetty
Add initial register headers for A6XX targets.
Signed-off-by: Sharat Masetty
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 1784 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 382 +
2 files changed, 2166 insertions
HFI (hardware firmware interface)
queue that the CPU uses to communicate with the GMU.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/Makefile |3 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 1172
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 162
ned-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_iommu.c | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index b23d33622f37..e80c79b3bb5c 100644
--- a/drivers/gpu/drm/msm/msm_iommu.c
+++ b/drivers/g
r new files]
Jordan Crouse (4):
drm/msm: Remove pm_runtime operations from msm_iommu
drm/msm: Add a helper function to parse clock names
drm/msm/adreno: Load the firmware before bringing up the hardware
drm/msm: Add A6XX device support
Sharat Masetty (1):
drm/msm: Add generated headers for
On Fri, Jun 22, 2018 at 09:51:28AM -0400, Sean Paul wrote:
> On Wed, May 30, 2018 at 10:50 AM Rajesh Yadav wrote:
> >
> > From: Jordan Crouse
> >
> > Remove unused code from dpu_io_util.c. The functions are only
> > used inside of the msm driver so remove the EX
On Thu, Jun 28, 2018 at 02:28:55PM -0400, Sean Paul wrote:
> This time the iomap/iounmap helper functions. Move map into dpu and
> refactor it to reflect their actual use. iounmap wasn't useful, so
> delete it and call iounmap directly.
>
> Signed-off-by: Sean Paul
> ---
> drivers/gpu/drm/msm/di
printf call.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/drm_print.c | 9 +
include/drm/drm_print.h | 2 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/drm_print.c b/drivers/gpu/drm/drm_print.c
index 03d1f98e5ac7..8fd489248a50 100644
--- a/drivers/gpu/drm
be cleaner for the caller as suggested by Chris Wilson
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/i915/i915_gpu_error.c | 34 +++
include/linux/ascii85.h | 39 +++
2 files changed, 43 insertions(+), 30 deletions(-)
create mode 100
Add support for drm_puts() to use seq_puts() to help speed up
up print time for constant strings.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/drm_print.c | 6 ++
include/drm/drm_print.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/drm_print.c b/drivers/gpu
Do a bit of cleanup to prepare for upcoming changes to pass the
hanging task comm and cmdline to the crash dump function.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_gpu.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm
Add a drm printer suitable for use with the read callback for
devcoredump or other suitable buffer based output format that
isn't otherwise covered by seq_file.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/drm_print.c | 74 +
include/drm/drm_pr
#x27;crash' debugfs node.
Add documentation for the crash dump output.
v2: Convert output to yaml, use ascii85 to dump ringbuffer contents.
Jordan Crouse (13):
include: Move ascii85 functions from i915 to linux/ascii85.h
drm: drm_printer: Add printer for devcoredump
drm: Add drm_puts(
a previously captured state from a GPU hang.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 11 +--
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 12 +---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 18 +
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 30
drivers
ger set of GPU information.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 15 +++
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 14 +++
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 22 ++
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 54
Add a put function for the coredump printer to bypass printf()
for constant strings for a speed boost.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/drm_print.c | 42 +
include/drm/drm_print.h | 2 ++
2 files changed, 44 insertions(+)
diff --git a
captured on the next hang.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/Kconfig | 1 +
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 36
For hangs, dump copy out the contents of the buffer objects attached to the
guilty submission and print them in the crash dump report.
Signed-off-by: Jordan Crouse
---
Documentation/gpu/drm-msm-crash-dump.txt | 7 +++
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 58
Add the contents of each ringbuffer to the GPU state and dump the
data in the crash file encoded with ascii85. To save space only
the used portions of the ringbuffer are dumped.
Signed-off-by: Jordan Crouse
---
Documentation/gpu/drm-msm-crash-dump.txt | 5 +++
drivers/gpu/drm/msm/adreno
ff-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 8 +-
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 8 +-
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 236 ++--
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 23 +--
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 4
Convert the format of the 'show' debugfs file and the crash
dump to a format resembling YAML. This should be easier to
parse and be more flexible for future changes and expansions.
Signed-off-by: Jordan Crouse
---
Documentation/gpu/drm-msm-crash-dump.txt | 46 +++
On Fri, Jun 29, 2018 at 10:47:31PM +0200, Arnd Bergmann wrote:
> On Fri, Jun 29, 2018 at 8:48 PM, Kees Cook wrote:
> > In the quest to remove all stack VLA usage from the kernel[1], this
> > switches to using a kasprintf()ed buffer. Return paths are updated
> > to free the allocation.
> >
> > [1]
4A2FQpadafLfEzK6CC=qpxydaacu1rq...@mail.gmail.com
Thanks for doing this.
Acked-by: Jordan Crouse
> Signed-off-by: Kees Cook
> ---
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 7 +--
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 28 +
> 2 files change
On Tue, Jul 03, 2018 at 03:48:12PM -0400, Sean Paul wrote:
> Signed-off-by: Sean Paul
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 182 +++
> 1 file changed, 182 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> b/arch/arm64/boot/dts/qcom/sdm845.dts
ested by Bjorn Andersson and add a new drm_print
facility to facilitate that. Remove the now obsolete 'crash' debugfs node.
Add documentation for the crash dump output.
v2: Convert output to yaml, use ascii85 to dump ringbuffer contents.
Jordan Crouse (13):
include: Move ascii85 functio
Add a put function for the coredump printer to bypass printf()
for constant strings for a speed boost.
v2: Add EXPORT_SYMBOL for _drm_puts_coredump
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/drm_print.c | 43 +
include/drm/drm_print.h | 2 ++
2
1 - 100 of 1244 matches
Mail list logo
