Re: [Freetel-codec2] FreeDV Tx power PAPR- SM1000

On Mon, Jun 22, 2020 at 4:55 AM glen english wrote: > One thing to consider- accurate PAPR measurement (by a receiver) is > hard at low SNR. That is one of the nice things about FEC based PAPR reduction, the receiver doesn't need to measure PAPR yet it exploits the PAPR reduction regardless.

Re: [Freetel-codec2] LPCNET on Xilinx FPGA

Hi Steve Yeah I am really impressed with it (as much as codec2). alright I'll start digging through it and understanding LPCnet computational requirements. the idea being we'd end up with a codec2 and LPCnet co-processor on a SPI interface etc. or we end up with an SM2000- using a ZYNQ,

Re: [Freetel-codec2] FreeDV Tx power PAPR- SM1000

Hi Greg RRR One thing to consider- accurate PAPR measurement (by a receiver)  is hard at low SNR. Tone reservation is probably the lowest cost means for this setup. And backward compatible. Remapping as I described this morning is probabaly reasonable, also- --given that LDPC encode is

Re: [Freetel-codec2] LPCNET on Xilinx FPGA

Hee, There's also nMigen https://www.youtube.com/watch?v=85ZCTuekjGA Although the guy never finishes anything :-) The ride was interesting. On Sun, Jun 21, 2020 at 11:15 PM glen english wrote: > Hi Steve > > oh yeah. Undergrad thesis. good for students to have a real project. > --and the

Re: [Freetel-codec2] FreeDV Tx power PAPR- SM1000

On Sun, Jun 21, 2020 at 9:51 PM glen english wrote: > I was giving some thought to how PAPR reduction might be implemented > within the current framework, taking into account the limited capability > of the SM1000 processor. One thing to perhaps consider is the ease at which a sufficiently

Re: [Freetel-codec2] LPCNET on Xilinx FPGA

Hi Steve oh yeah. Undergrad thesis. good for students to have a real project. --and the thesis is a useful metric Verilog. yuk. The other option is HLS. C++ >> VHDL. You need to somewhat know what you are doing, because what you do affects how much of a mess it makes at the low level

Re: [Freetel-codec2] LPCNET on Xilinx FPGA

Hi Glenn, Having just become the owner of an ADALM Pluto, which also has an (albeit small) Xilinx FPGA on board, I'm very interested in this. I've only just begun dipping my toe into the ecosystem, so I'm not expecting that I'll be able to contribute immediately to these efforts (my hello-world

Re: [Freetel-codec2] LPCNET on Xilinx FPGA

FYI Codec2 (2400 I think) Encoder in FPGA Thesis: https://etd.ohiolink.edu/!etd.send_file?accession=miami158819886466373=inline Github: https://github.com/santhiyaskumar/FPGA_Codec2Encoder ___ Freetel-codec2 mailing list

Re: [Freetel-codec2] LPCNET on Xilinx FPGA

Hi Don There is MUCH documentation  on using the FPGA fabric  for RNNs. https://www.xilinx.com/support/documentation/application_notes/xapp1332-neural-networks.pdf There are a couple of options and the FP options is easily synthesised. The xilinx native DSP block DSP48E1 multiplier/adder 

[Freetel-codec2] LPCNET on Xilinx FPGA

Hi Jeroen    ,  David I'm interested in assisting where I can in the whole freeDV sphere. I've recently gone over the last year of forum posts to see what I have missed in detail. I'd like to be able to implement LPC122, 203 (and Codec2)  on a small , cheap FPGA for use with FreeDV . I am

Re: [Freetel-codec2] FreeDV Tx power PAPR- SM1000

actually the majority of SSB generators ARE reasonably phase coherent over a relatively moderate passband with respect to their total passband. The group delay 'ears' are on the edges of the filter. staying between 600 and 2200 Hz should be OK for a 2400 Hz wide traditional lattice sideband

Re: [Freetel-codec2] FreeDV Tx power PAPR- SM1000

Hi Glen and all, There's something I don't understand here: In the SM1000 we have control of all the amplitudes AND phases of all the audio carriers. Thus we may be able to do something to reduce the peak levels that an IDEAL SSB generator will produce. This is where I have a problem, the

Re: [Freetel-codec2] VHF/UHF data physical layer testing

Hi, Have you seen the Ham Radio Mesh network: http://usercontent.arednmesh.org/K/5/K5DLQ/livemap2.html So, there's quite a "market" out there for better solutions. Though, these are all built on mass produced affordable hardware and all that is modified (sorta) is the software. (basically just

Re: [Freetel-codec2] FreeDV Tx power PAPR- SM1000

Alan it already goes through an SSB generator, and is already bandwidth constrained. The bandwidth expansion because of an excess  PAPR event occurs where the signal cannot be faithfully reproduced- that is stages beyond the sideband modulator- mostly the power amplifier, but in reality all

Re: [Freetel-codec2] FreeDV Tx power PAPR- SM1000

Hi David and Glen, Just how is this going to be effective when the audio signal is passed through an SSB generator? You will also have to, in the maths, factor this in. Am I wrong here? Alan VK2ZIW On Mon, 22 Jun 2020 07:49:45 +1000, glen english wrote > I was giving some thought to how PAPR

[Freetel-codec2] VHF/UHF data physical layer testing

Some good progress on support for VHF/UHF data using Codec 2 modems: http://www.rowetel.com/?p=7207 - David On 22/6/20 7:24 am, David Rowe wrote: > Hi Glen, > > Sounds like you are quite experienced and have had some fun times with > LDPC work in the past. Thanks for your offer but I think

Re: [Freetel-codec2] FreeDV Tx power PAPR- SM1000

I was giving some thought to how PAPR reduction might be implemented within the current framework, taking into account the limited capability of the SM1000 processor. If we approach this on trying to constrain the  statistical likelihood of a PAPR event  (where the peak power exceeds some

Re: [Freetel-codec2] Generating LDPC Codes

David, I have quite a bit of code in this area from modem stuff from years ago. Mostly based on David Mackay's work from memory. I can dig it all out. I generated : LDPC matrix generator, parametizable. C++ encoder, C encoder, encoders with precalculated LUTs that I used on STM32L0 at 16