https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84064
--- Comment #2 from Jeffrey A. Law ---
I wasn't ever happy with the discrepancy between the computation of TO_ALLOCATE
in the layout code and ALLOCATE within ix86_expand_prologue. It seemed ripe to
fall into this kind of problem. sigh.
If
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83776
Aldy Hernandez changed:
What|Removed |Added
CC||aldyh at gcc dot gnu.org
--- Comment
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84047
--- Comment #6 from Martin Sebor ---
I posted a patch for a similar issue reported in bug 83776
(https://gcc.gnu.org/ml/gcc-patches/2018-01/msg02144.html). It handles
MEM_REFs and diagnoses the test case in comment #0 (I must have missed that
That or just use -mfpu=auto (as in -mcpu=cortex-r52 -mfpu=auto
-mfloat-abi=(softfp|hard)).
Best regards,
Thomas
On 26/01/18 16:44, Alexander Fedotov wrote:
Thank you Thomas
So in order to set dp+Neon for armv8-r I should to use switch
"neon-fp-armv8". Not an fpv5-d16. Right ?
On Fri, Jan
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84063
Martin Sebor changed:
What|Removed |Added
Keywords||diagnostic
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84047
--- Comment #5 from Aldy Hernandez ---
Created attachment 43259
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=43259=edit
proposed UNTESTED patch
(In reply to Jakub Jelinek from comment #4)
> I don't think we want to be adding new cases
On Mon, 2017-12-11 at 17:24 -0500, Jason Merrill wrote:
> On Wed, Nov 22, 2017 at 10:36 AM, David Malcolm
> wrote:
Original post:
https://gcc.gnu.org/ml/gcc-patches/2017-11/msg02048.html
> > PR c++/81610 and PR c++/80567 report problems where the C++
> > frontend
> >
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80567
David Malcolm changed:
What|Removed |Added
Status|NEW |UNCONFIRMED
Version|7.0
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84070
Dominique d'Humieres changed:
What|Removed |Added
Status|UNCONFIRMED |WAITING
Last reconfirmed|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81610
David Malcolm changed:
What|Removed |Added
Summary|bogus fix-it hint for a |[8 Regression] bogus fix-it
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84070
Bug ID: 84070
Summary: Incorrect assignment to allocatable character variable
Product: gcc
Version: 7.2.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78969
Martin Sebor changed:
What|Removed |Added
Last reconfirmed|2017-05-23 00:00:00 |2018-1-26
Known to fail|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84047
Jakub Jelinek changed:
What|Removed |Added
CC||jakub at gcc dot gnu.org
--- Comment #4
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84065
Jakub Jelinek changed:
What|Removed |Added
Priority|P3 |P4
CC|
On 01/22/2018 09:33 AM, Jakub Jelinek wrote:
On Tue, Jan 16, 2018 at 03:20:24PM -0700, Martin Sebor wrote:
gcc/ChangeLog:
PR tree-optimization/83896
* tree-ssa-strlen.c (get_string_len): Rename...
(get_string_cst_length): ...to this. Return HOST_WIDE_INT.
Avoid
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84047
Aldy Hernandez changed:
What|Removed |Added
Status|UNCONFIRMED |NEW
Last reconfirmed|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84069
Bug ID: 84069
Summary: missing strlen optimization after constant memcpy with
offset
Product: gcc
Version: 8.0
Status: UNCONFIRMED
Severity: normal
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83845
rsandifo at gcc dot gnu.org changed:
What|Removed |Added
URL|
nu
--host=x86_64-pc-linux-gnu --target=aarch64-unknown-linux-gnu
--with-ld=/usr/bin/aarch64-unknown-linux-gnu-ld
--with-as=/usr/bin/aarch64-unknown-linux-gnu-as --disable-libstdcxx-pch
--prefix=/repo/gcc-trunk//binary-trunk-257087-checking-yes-rtl-df-extra-aarch64
Thread model: posix
gcc version 8.0.1
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83846
rsandifo at gcc dot gnu.org changed:
What|Removed |Added
URL|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82249
--- Comment #8 from Jason Merrill ---
Author: jason
Date: Fri Jan 26 17:10:24 2018
New Revision: 257101
URL: https://gcc.gnu.org/viewcvs?rev=257101=gcc=rev
Log:
PR c++/84036 - ICE with variadic capture.
PR c++/82249
*
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84036
--- Comment #4 from Jason Merrill ---
Author: jason
Date: Fri Jan 26 17:10:24 2018
New Revision: 257101
URL: https://gcc.gnu.org/viewcvs?rev=257101=gcc=rev
Log:
PR c++/84036 - ICE with variadic capture.
PR c++/82249
*
On Tue, Jan 23, 2018 at 02:49:03PM +, Kyrill Tkachov wrote:
> Hi all,
>
> This patch fixes the testsuite failures gcc.target/aarch64/subs_compare_1.c
> and subs_compare_2.c The tests check that we combine a sequence like:
> sub w2, w0, w1
> cmp w0, w1
>
> into
>
My recent patch for 82249 caused a substitution here to return a
TREE_VEC rather than an EXPR_PACK_EXPANSION; fixed by pulling out the
expansion in that case.
Tested x86_64-pc-linux-gnu, applying to trunk.
commit 577e646e8472e6bc226168fb96d0884663b0c2cd
Author: Jason Merrill
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84045
Jakub Jelinek changed:
What|Removed |Added
CC||jason at gcc dot gnu.org
--- Comment #3
Hi.
This fixes detection of ifunc target capability.
I'm going to install the patch.
Martin
gcc/testsuite/ChangeLog:
2018-01-26 Martin Liska
* lib/target-supports.exp: Return a value, otherwise -Wreturn-type
warning is seen.
---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81601
--- Comment #24 from Aldy Hernandez ---
(In reply to Jakub Jelinek from comment #23)
> What would create those BIT_FIELD_REFs so early though? They should stay as
> COMPONENT_REFs.
I thought you'd never ask... why our friend fold_truth_andor_1
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83896
Martin Sebor changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83896
--- Comment #5 from Martin Sebor ---
Author: msebor
Date: Fri Jan 26 16:47:22 2018
New Revision: 257100
URL: https://gcc.gnu.org/viewcvs?rev=257100=gcc=rev
Log:
PR tree-optimization/83896 - ice in get_string_len on a call to strlen with
Thank you Thomas
So in order to set dp+Neon for armv8-r I should to use switch
"neon-fp-armv8". Not an fpv5-d16. Right ?
On Fri, Jan 26, 2018 at 12:52 PM, Thomas Preudhomme
wrote:
> Hi Alexander,
>
> As mentioned in [1], Arm Cortex-R52 can have either single
I've applied this patch to openacc-gcc-7-branch which privatizes
reduction variables inside independent loops which are guaranteed to be
assigned worker or vector partitioning during oaccdevlow. Without this
patch, the inner-reduction.c test case would generate bogus results.
This patch is an
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84045
Jakub Jelinek changed:
What|Removed |Added
CC||jakub at gcc dot gnu.org
--- Comment #2
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81601
--- Comment #23 from Jakub Jelinek ---
What would create those BIT_FIELD_REFs so early though? They should stay as
COMPONENT_REFs.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81601
Aldy Hernandez changed:
What|Removed |Added
Assignee|aldyh at gcc dot gnu.org |unassigned at gcc dot
gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83954
--- Comment #8 from Dan Bonachea ---
(In reply to Jan Hubicka from comment #7)
> This should silence the warning.
> Index: lto-symtab.c
> ===
> --- lto-symtab.c(revision
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84046
Jakub Jelinek changed:
What|Removed |Added
Status|WAITING |RESOLVED
CC|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83956
Jason Merrill changed:
What|Removed |Added
Status|UNCONFIRMED |ASSIGNED
Last reconfirmed|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84044
--- Comment #8 from Jan Hubicka ---
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84044
>
> --- Comment #7 from rguenther at suse dot de ---
> On Fri, 26 Jan 2018, marxin at gcc dot gnu.org wrote:
>
> >
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81763
--- Comment #46 from Manuel Lauss ---
Created attachment 43257
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=43257=edit
reducest testcase
reduced testcase for Jakub's patch in comment #36 and the build failure it
causes in comment #42:
There's another latent bug in loop unrolling edge/region removal code
which doesn't deal with removing edges in already removed regions.
The following fixes this.
Bootstrapped on x86_64-unknown-linux-gnu, testing in progress.
Richard.
2018-01-26 Richard Biener
Hello!
It turned out that *andndi3_doubleword pattern needs earlyclobber on
the output operand of its (=r,r,rm) alternative to prevent partial
regs of the first split instruction from clobbering input operands of
the second insn.The patch also adds a couple of alternatives with
matching input and
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83983
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Target|hppa-unknown-linux-gnu |hppa-unknown-linux-gnu,
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84019
--- Comment #6 from Jakub Jelinek ---
The code in question is:
const struct real_format *const fmt =
REAL_MODE_FORMAT (TYPE_MODE (TREE_TYPE (type)));
const int prec = fmt->p;
const mp_rnd_t rnd =
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81038
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Target|powerpc*-*-*, i?86-*-*, |powerpc*-*-*, i?86-*-*,
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84048
--- Comment #3 from dave.anglin at bell dot net ---
On 2018-01-26 2:15 AM, ebotcazou at gcc dot gnu.org wrote:
> Did you upgrade binutils?
Yes.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81763
--- Comment #45 from uros at gcc dot gnu.org ---
Author: uros
Date: Fri Jan 26 15:36:32 2018
New Revision: 257096
URL: https://gcc.gnu.org/viewcvs?rev=257096=gcc=rev
Log:
PR target/81763
* config/i386/i386.md
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84067
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Status|UNCONFIRMED |NEW
Known to work|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84036
Jason Merrill changed:
What|Removed |Added
Status|NEW |ASSIGNED
Assignee|unassigned
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82514
Jason Merrill changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84059
--- Comment #2 from Martin Liška ---
Created attachment 43256
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=43256=edit
Untested patch
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81440
Eric Gallager changed:
What|Removed |Added
Status|NEW |ASSIGNED
--- Comment #9 from Eric
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84040
Jakub Jelinek changed:
What|Removed |Added
Status|NEW |ASSIGNED
Assignee|unassigned
On 26 January 2018 at 16:13, Richard Biener wrote:
> On Fri, Jan 26, 2018 at 3:57 PM, Christophe Lyon
> wrote:
>> On 26 January 2018 at 11:25, Richard Biener wrote:
>>> On Thu, 25 Jan 2018, Richard Biener wrote:
>>>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82123
Eric Gallager changed:
What|Removed |Added
Status|NEW |ASSIGNED
--- Comment #8 from Eric
The problem here was that when substituting the local class we first
substitute its context, and we weren't finding the rebuilt function
we're inside of, so we tried to create new instantiations of the
closure and call operator, leading to chaos.
The core of this patch is the change to
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84067
Bug ID: 84067
Summary: [8 regression] gcc.dg/wmul-1.c regression on aarch64
after r257077
Product: gcc
Version: 8.0
Status: UNCONFIRMED
Severity: normal
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82514
--- Comment #6 from Jason Merrill ---
Author: jason
Date: Fri Jan 26 15:25:23 2018
New Revision: 257093
URL: https://gcc.gnu.org/viewcvs?rev=257093=gcc=rev
Log:
PR c++/82514 - ICE with local class in generic lambda.
* pt.c
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80867
--- Comment #10 from Richard Biener ---
I suggest the following (pre-approved if it works):
Index: tree-vect-stmts.c
===
--- tree-vect-stmts.c (revision 257091)
+++
On Fri, Jan 26, 2018 at 4:04 PM, Richard Sandiford
wrote:
> Richard Biener writes:
>> On Fri, Jan 26, 2018 at 3:21 PM, Richard Sandiford
>> wrote:
>>> I hadn't realised that on big-endian targets,
Kyrill Tkachov writes:
> On 26/01/18 13:31, Richard Sandiford wrote:
>> sve/extract_[12].c were relying on the target-independent optimisation
>> that removes a redundant vec_select, so that we don't end up with
>> things like:
>>
>> dup v0.4s, v0.4s[0]
>>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81122
--- Comment #10 from Ben Woodard ---
Also note: https://connect.microsoft.com/VisualStudio/feedback/details/742775
My reading of:
https://wg21.link/lwg2381
is that if the first part of the number includes a '.' then the portion after
the 'p'
On Fri, Jan 26, 2018 at 3:57 PM, Christophe Lyon
wrote:
> On 26 January 2018 at 11:25, Richard Biener wrote:
>> On Thu, 25 Jan 2018, Richard Biener wrote:
>>
>>> On Thu, 25 Jan 2018, Marc Glisse wrote:
>>>
>>> > On Thu, 25 Jan 2018, Richard Biener
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84040
Jakub Jelinek changed:
What|Removed |Added
CC||jakub at gcc dot gnu.org
--- Comment #3
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81122
--- Comment #9 from Jonathan Wakely ---
(In reply to Heinz Kohl from comment #8)
> o.k., it looks like a flawy definition.
Yes, that's why it's being fixed by the standards committee. I don't want to
change our implementation yet, until the
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80867
--- Comment #9 from kelvin at gcc dot gnu.org ---
I've been investigating this and have identified the origin of the problem.
The ICE occurs because tree-vect-stmts.c: vectorizable_call () is calling
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81122
--- Comment #8 from Heinz Kohl ---
o.k., it looks like a flawy definition.
First of all, it would be nice, if you would refer my error message to the
right instance.
It's unclear, what's to do in the meantime.
An idea might
Richard Biener writes:
> On Fri, Jan 26, 2018 at 3:21 PM, Richard Sandiford
> wrote:
>> I hadn't realised that on big-endian targets, VEC_UNPACK*HI_EXPR unpacks
>> the low-numbered lanes and VEC_UNPACK*LO_EXPR unpacks the high-numbered
>>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83008
--- Comment #31 from sergey.shalnov at intel dot com ---
Richard,
Thank you for your latest patch. This patch is exactly that
I’ve discussed in this issue request.
I tested it with SPEC20[06|17] and see no performance/stability degradation.
On Fri, Jan 26, 2018 at 3:21 PM, Richard Sandiford
wrote:
> I hadn't realised that on big-endian targets, VEC_UNPACK*HI_EXPR unpacks
> the low-numbered lanes and VEC_UNPACK*LO_EXPR unpacks the high-numbered
> lanes. This meant that both the SVE patterns and the
On 26 January 2018 at 11:25, Richard Biener wrote:
> On Thu, 25 Jan 2018, Richard Biener wrote:
>
>> On Thu, 25 Jan 2018, Marc Glisse wrote:
>>
>> > On Thu, 25 Jan 2018, Richard Biener wrote:
>> >
>> > > --- gcc/match.pd (revision 257047)
>> > > +++ gcc/match.pd (working
On Thu, Jan 25, 2018 at 05:58:37PM -0200, Alexandre Oliva wrote:
> > This looks wrong. The proposal has not been accepted yet, so you
> > really can't know if DW_LLE_view_pair will be like that or whether it
> > will have value of 9. Unfortunately, the DWARF standard doesn't specify a
> > vendor
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84003
Richard Biener changed:
What|Removed |Added
Known to work||8.0
Known to fail|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84003
--- Comment #5 from Richard Biener ---
Author: rguenth
Date: Fri Jan 26 14:50:25 2018
New Revision: 257091
URL: https://gcc.gnu.org/viewcvs?rev=257091=gcc=rev
Log:
2018-01-26 Richard Biener
PR
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84061
Richard Biener changed:
What|Removed |Added
Priority|P3 |P2
Status|UNCONFIRMED
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878
--- Comment #11 from Nathan Sidwell ---
fixed on gcc-7 branch r257089.
Ping^2
http://gcc.gnu.org/ml/gcc-patches/2018-01/msg00727.html
On Wed, Jan 17, 2018 at 05:47:12PM +0100, Jakub Jelinek wrote:
> I'd like to ping this patch.
> As I wrote, it isn't a full solution for all the __VA_OPT__ issues,
> but it isn't even clear to me how exactly it should behave, but
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84048
Jakub Jelinek changed:
What|Removed |Added
Priority|P3 |P4
CC|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81122
--- Comment #7 from Jonathan Wakely ---
(In reply to Ben Woodard from comment #5)
> The example code in: http://en.cppreference.com/w/cpp/io/manip/fixed
> suggests that this should work. Probably either the behavior or the library
> or the
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83989
Jakub Jelinek changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81122
--- Comment #6 from Jonathan Wakely ---
(In reply to Ben Woodard from comment #4)
> Without this Is there a way to read and write floats and doubles accurately
> without the rounding that converting to/from base 10 ends up introducing?
> How are
Hi all,
I'm committing this to trunk after a discussion with James.
There's really not that much aarch64-specific change, it can be considered
obvious from that perspective.
Thanks,
Kyrill
On 19/01/18 10:58, Kyrill Tkachov wrote:
Ping.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84049
--- Comment #3 from Jakub Jelinek ---
What's expensive on for-6.C?
#pragma omp parallel for with 10 iterations each, doing #pragma omp atomic in
there.
For capping the number of threads, you can always just export
OMP_NUM_THREADS=32
or something
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81122
--- Comment #5 from Ben Woodard ---
The example code in: http://en.cppreference.com/w/cpp/io/manip/fixed
suggests that this should work. Probably either the behavior or the library or
the example on cppreference should change.
The SVE tests are split into code-quality compile tests and runtime
tests. A lot of the former are geared towards LP64. It would be
possible (but tedious!) to mark up every line that is expected to work
only for LP64, but I think it would be a constant source of problems.
Since the code has not
On Sun, Jan 7, 2018 at 7:11 PM, H.J. Lu wrote:
> On Tue, Oct 24, 2017 at 10:58 AM, H.J. Lu wrote:
>> On Tue, Oct 24, 2017 at 10:40 AM, Andi Kleen wrote:
>>> "H.J. Lu" writes:
--- /dev/null
+++
On Sun, Jan 7, 2018 at 7:13 PM, H.J. Lu wrote:
> On Fri, Dec 8, 2017 at 5:02 AM, H.J. Lu wrote:
>> On Tue, Oct 24, 2017 at 5:31 AM, H.J. Lu wrote:
>>> PLT should be avoided with shadow stack in 32-bit mode if more than 2
>>>
Hi Richard,
> On Tue, Jan 16, 2018 at 8:20 PM, Andrew Roberts
> wrote:
>> Boot strap on Darwin x86_64 with llvm now seems broken as of last 8.0.0
>> snapshot, it still is working fine with 7.2.0.
>> I've added bug: 83903
>>
>> x86_64, armv6, armv7, aarch64 all seem fine
I hadn't realised that on big-endian targets, VEC_UNPACK*HI_EXPR unpacks
the low-numbered lanes and VEC_UNPACK*LO_EXPR unpacks the high-numbered
lanes. This meant that both the SVE patterns and the handling of
fully-masked loops were wrong.
The patch deals with that by making sure that all
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84065
Dominique d'Humieres changed:
What|Removed |Added
Status|UNCONFIRMED |NEW
Last reconfirmed|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84066
Bug ID: 84066
Summary: Wrong shadow stack register size is saved for x32
Product: gcc
Version: 8.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83990
--- Comment #13 from Jakub Jelinek ---
Comment on attachment 43254
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=43254
Lost location fix
As use use it multiple time, perhaps do location_t loc = gimple_location
(stmt);
early and use loc
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83990
--- Comment #12 from Martin Jambor ---
Created attachment 43254
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=43254=edit
Lost location fix
I'm testing this patch which does what Jakub suggested in comment #4. With the
patch,
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84064
Jakub Jelinek changed:
What|Removed |Added
CC||jakub at gcc dot gnu.org
--- Comment #1
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84044
--- Comment #7 from rguenther at suse dot de ---
On Fri, 26 Jan 2018, marxin at gcc dot gnu.org wrote:
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84044
>
> --- Comment #5 from Martin Liška ---
> (In reply to Richard Biener from comment
Hi Richard,
On 26/01/18 13:31, Richard Sandiford wrote:
sve/extract_[12].c were relying on the target-independent optimisation
that removes a redundant vec_select, so that we don't end up with
things like:
dup v0.4s, v0.4s[0]
...use s0...
But that optimisation rightly doesn't trigger
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84065
Bug ID: 84065
Summary: [8 regression] string_1.f90 fails since r256944
Product: gcc
Version: 8.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81122
--- Comment #4 from Ben Woodard ---
Without this Is there a way to read and write floats and doubles accurately
without the rounding that converting to/from base 10 ends up introducing? How
are you supposed to use istreams like
Subreg reads should be equivalent to storing the inner register to
memory and loading the appropriate memory bytes back, with subreg
writes doing the reverse. For the reasons explained in the comments,
this isn't what happens for big-endian SVE if we simply reinterpret
one vector register as
This patch deals with cases in which a CONST_VECTOR contains a
repeating bit pattern that is wider than one element but narrower
than 128 bits. The current code:
* treats the repeating pattern as a single element
* uses the associated LD1R to load and replicate it (such as LD1RD
for 64-bit
> On Fri, 26 Jan 2018, Jan Hubicka wrote:
>
> > > On Thu, 25 Jan 2018, Jan Hubicka wrote:
> > >
> > > > Hi,
> > > > the testcase triggers invalid warning on type mismatch because array
> > > > of pointers to complete type has different alias set from array of
> > > > pointers
> > > > to
101 - 200 of 295 matches
Mail list logo