[PATCH] [MIPS] Remove unnecessary moves around dpadd and dpsub

Unnecessary moves around dpadd and dpsub are caused by different pseudos being assigned to the input-output operands which correspond to the same register. This forces the same pseudo to the input-output operands, which removes unnecesary moves. Tested on mips-mti-linux-gnu. gcc/ChangeLog:

Re: [PATCH] find_partition_fixes: remove unused bbs_in_cold_partition variable

On 10/16/19 8:26 AM, Ilya Leoshkevich wrote: > Bootstrapped and regtested on x86_64-redhat-linux. > I noticed this while looking into PR92007. > > gcc/ChangeLog: > > 2019-10-16 Ilya Leoshkevich > > * cfgrtl.c (find_partition_fixes): Remove bbs_in_cold_partition. OK. Thanks, Jeff

Re: Improving GCC's line table information to help GDB

On 10/16/19 11:17 AM, Luis Machado wrote: Hi Maciej, On 10/16/19 11:11 AM, Maciej W. Rozycki wrote: Hi Luis, Is there a better way to force the compiler to output such a line table transition without having to resort to a dummy jump? Is there a safer way to add such transitions without

Re: Improving GCC's line table information to help GDB

On 10/16/19 5:59 AM, Richard Biener wrote: I think that adding an extra jump is unwanted. Instead - if you disregard the single-source-line case - there's always the jump and the label we jump to which might/should get different source locations. Like in one of the above cases: main () {

[PATCH] V6, #17 of 17: Add stack protection test

This is a new test for the stack protection code that was added in V6 patch #4. Along with the other patches, I have done bootstraps on a little endian power8 system, and there were no regressions in the test suite. I have built both Spec 2006 and Spec 2017 with all of these patches installed

[PATCH] V6, #16 of 17: Wrong subject, should have been update @pcrel

Note, patch #16 had the wrong subject line. It should have been that modifies @pcrel to use an explicit (0),1. Sorry about that. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797

[PATCH] V6, #16 of 17: New test for stack protection

This patch adds an explicit (0),1 to labels used with the @pcrel syntax. The intention is make sure that the user does not use an instruction that assumes PC-relative instructions can take a base register (as I did in the V4 patches). This was V5 patch #15. This patch is optional. If it is not

[Bug testsuite/92125] New: New test gcc.dg/ipa/pr91088.c introduced in r277054 fails

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92125 Bug ID: 92125 Summary: New test gcc.dg/ipa/pr91088.c introduced in r277054 fails Product: gcc Version: 10.0 Status: UNCONFIRMED Severity: normal

[PATCH] V6, #15 of 17: Add PC-relative tests

This patch adds PC-relative tests for the various types, and verifies that expected instructions are generated. This is the same as V5 patch #14. Along with the other patches, I have done bootstraps on a little endian power8 system, and there were no regressions in the test suite. I have built

Re: [PATCH 3/4] Factor out duplicate code in gimplify_scan_omp_clauses

Hi Julian! On 2019-10-06T15:32:36-0700, Julian Brown wrote: > This patch factors out some code in gimplify_scan_omp_clauses into two > new outlined functions. Yay for such simplification, and yay for documenting what's going on! > Previously approved here: > >

[PATCH] V6, #14 of 17: Add prefixed load/store tests with large offsets

This patch adds a bunch of tests for each of the types to verify that it generates the appropriate instructions for addresses that do not fit in a 16-bit offset. This patch is essentially V5 patch #13. Along with the other patches, I have done bootstraps on a little endian power8 system, and

[PATCH] V6, #13 of 17: Add test for prefix pre-modify

This patch adds a test to make sure the GCC compiler does not try to issue a pre-modify prefixed address load/store since the prefixed instructions do not support an update form. This patch was in V5 patch #12 but it was split out. Along with the other patches, I have done bootstraps on a little

[Bug tree-optimization/92115] [10 Regression] ICE in gimple_cond_get_ops_from_tree, at gimple-expr.c:577

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92115 --- Comment #4 from Arseny Solokha --- (In reply to Ilya Leoshkevich from comment #3) > Arseny, how did you find this? Did you just run the regtest? I wonder why > didn't I see it during my test runs. My test harness continuously compiles a

[PATCH] V6, #12 of 17: Add prefix test for DS/DQ instructions

This patch adds a new test that makes sure the appropriate prefixed instruction is generated if a memory is attempted for DS-format or DQ-format instructions where the offset does not fit the DS or DQ constraints. This patch was in V5 patch #12 and was split out in this patch. Along with the

[Bug libstdc++/92124] New: std::vector copy-assigning when it should move-assign.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92124 Bug ID: 92124 Summary: std::vector copy-assigning when it should move-assign. Product: gcc Version: 9.2.0 Status: UNCONFIRMED Severity: normal Priority: P3

[PATCH] find_partition_fixes: remove unused bbs_in_cold_partition variable

Bootstrapped and regtested on x86_64-redhat-linux. I noticed this while looking into PR92007. gcc/ChangeLog: 2019-10-16 Ilya Leoshkevich * cfgrtl.c (find_partition_fixes): Remove bbs_in_cold_partition. --- gcc/cfgrtl.c | 2 -- 1 file changed, 2 deletions(-) diff --git

[PATCH] V6, #11 of 17: Add PADDI tests

This patch adds 3 tests for the PADDI instruction. This was originally part of V5 patch #12, but it was split out. 2019-10-15 Michael Meissner * gcc.target/powerpc/paddi-1.c: New test to test using PLI to load up a large DImode constant. *

[PATCH] V6, #10 of 17: Update target-supports.exp

This patch adds 2 new target supports options for the testsuite. One is for whether prefixed instructins with 34-bit offsets are supported. The other is whether PC-relative instructions are supported. This was originally part of V5 patch #12, but it was split out to be a separate patch. Along

[Bug target/70010] powerpc: -flto forgets 'no-vsx' function attributes

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70010 Peter Bergner changed: What|Removed |Added Status|NEW |RESOLVED

[PATCH] V6, #9 of 17: Change defaults on Linux 64-bit to enable -mpcrel

This patch changes the default for Linux 64-bit to enable -mpcrel and -mprefixed-addr by default when you use -mcpu=future. Other OS targets do not enable these switches by default. This is the same as V5 patch #11. Along with the other patches, I have done bootstraps on a little endian power8

Re: Improving GCC's line table information to help GDB

Hi Maciej, On 10/16/19 11:11 AM, Maciej W. Rozycki wrote: Hi Luis, Is there a better way to force the compiler to output such a line table transition without having to resort to a dummy jump? Is there a safer way to add such transitions without worrying about the optimizer getting rid of them

[PATCH] V6, #8 of 17: Use PADDI to add 34-bit constants

This patch uses the PADDI instruction to add 34-bit constants that can't be done with a single ADDI or ADDIS instruction. This patch is the same as V5 patch #10. Along with the other patches, I have done bootstraps on a little endian power8 system, and there were no regressions in the test

Re: Improving GCC's line table information to help GDB

Hi Luis, > Is there a better way to force the compiler to output such a line table > transition without having to resort to a dummy jump? Is there a safer > way to add such transitions without worrying about the optimizer getting > rid of them later on? Should we even worry about preserving

[PATCH] V6, #7 of 17: Use PADDI/PLI to load up 32-bit SImode constants

This patch uses PADDI (PLI) to load up 32-bit SImode constants that can't be loaded with either a single ADDI or ADDIS instruction. This patch is the same as V5 patch #9. Along with the other patches, I have done bootstraps on a little endian power8 system, and there were no regressions in the

[Bug fortran/92122] [coarrays, polymophism] Error 'must be a scalar of type LOCK_TYPE'

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92122 Tobias Burnus changed: What|Removed |Added Keywords|rejects-valid |ice-on-valid-code --- Comment #1 from

[PATCH] V6, #6 of 17: Use PADDI/PLI to load up 34-bit DImode constants

This patch uses PADDI (PLI) to load up 34-bit DImode constants. This is the same patch as V5 patch #8. Along with the other patches, I have done bootstraps on a little endian power8 system, and there were no regressions in the test suite. I have built both Spec 2006 and Spec 2017 with all of

[PATCH] V6, #5 of 17: Add prefixed instruction support to vector extract optimizations

This patch updates the support for optimizing vector extracts to know about prefixed addressing. There are two parts to the patch: 1) If a vector extract with a constant element number extracts an element from a vector residing in memory that uses a prefixed address (either numeric or

[Bug tree-optimization/92056] [10 Regression] ice in expr_object_size, at tree-object-si ze.c:675 with -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92056 --- Comment #5 from Jakub Jelinek --- Seems a bug introduced in r120581, COND_EXPR really needs to be handled like a PHI node, which is handled as: for (i = 0; i < gimple_phi_num_args (stmt); i++) { tree rhs =

Re: [PATCH V2] rs6000: -flto forgets 'no-vsx' function attributes (PR target/70010)

Segher Boessenkool writes: > Hi! > >> the callee explicitly disables some isa_flags the caller is using. > > No trailing spaces please. Updated. > >> + /* The callee's options must be a subset of the caller's options, i.e. >> + a vsx function may inline an altivec function, but a

[Bug tree-optimization/92056] [10 Regression] ice in expr_object_size, at tree-object-si ze.c:675 with -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92056 Jakub Jelinek changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassigned

[PATCH] V6, #4 of 17: Add prefixed instruction support to stack protect insns

This patch fixes the stack protection insns to support stacks larger than 16-bits on the 'future' system using prefixed loads and stores. This rewrites V5 patch #5. In earlier patches, I had had a variant of this patch, but I was asked to restrict the protect insns to use non-prefixed insns,

[PATCH] V6, #3 of 17: Update lwa_operand for prefixed PLWA

This patch allows using load SImode with sign extend to DImode to generate the PLWA instruction on the 'future' machine if the offset for the load has the bottom 2 bits being non-zero. The normal LWA instruction is a DS format instruction, and it needs the bottom 2 bits to be 0. This patch was

[PATCH] V6, #2 of 17: Minor code reformat

This patch tweaks the code formatting that I noticed in making the previous patch for some of the 128-bit mode move instructions. Originally this was part of V5 patch #2, but it has been moved to a separate patch. Along with the other patches, I have done bootstraps on a little endian power8

[Bug target/92071] [10 regression][ARM] ice in gen_movsi, at config/arm/arm.md:5378

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92071 Wilco changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/70010] powerpc: -flto forgets 'no-vsx' function attributes

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70010 --- Comment #7 from Jiu Fu Guo --- Author: guojiufu Date: Wed Oct 16 13:35:41 2019 New Revision: 277065 URL: https://gcc.gnu.org/viewcvs?rev=277065=gcc=rev Log: In PR70010, a function is marked with target(no-vsx) to disable VSX code

[PATCH] V6, #1 of 17: Use ADJUST_INSN_LENGTH for prefixed instructions

This patch uses the target hook ADJUST_INSN_LENGTH to change the length of instructions that contain prefixed memory/add instructions. There are 2 new insn attributes: 1) num_insns: If non-zero, returns the number of machine instructions in an insn. This simplifies the calculations in

Re: [gomp4.1] Start of structure element mapping support

Hi Jakub! Stumbled over this while reviewing Julian's "Factor out duplicate code in gimplify_scan_omp_clauses": On 2015-07-31T18:16:10+0200, Jakub Jelinek wrote: > This patch is the start of implementation of struct element mapping. Not quite the same, but similar code is still present in GCC

[PATCH] Relax integer condition reduction, simplify vect_is_simple_reduction

It happens we cannot have different typed data and index for integer condition reductions right now, for whatever reason. The following makes that work, even for double data and integer index. There's hope this enables some relevant amount of extra vectorization. Actually this is fallout from

[Bug fortran/92123] New: [F2018/array-descriptor] Scalar allocatable/pointer with array descriptor (via bind(C)): ICE with select rank or error scalar variable with POINTER or ALLOCATABLE in procedur

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92123 Bug ID: 92123 Summary: [F2018/array-descriptor] Scalar allocatable/pointer with array descriptor (via bind(C)): ICE with select rank or error scalar variable with POINTER or

[Bug tree-optimization/92033] ICE during dom with -march=armv8.2-a+sve

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92033 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|ASSIGNED|RESOLVED

Re: [ C++ ] [ PATCH ] [ RFC ] p1301 - [[nodiscard("should have a reason")]]

On Tue, 2019-10-15 at 20:31 -0400, JeanHeyd Meneide wrote: > Attached is a patch for p1301 that improves in the way Jason Merrill > specified earlier > (https://gcc.gnu.org/ml/gcc-patches/2019-09/msg00858.html), but it > keeps segfaulting on my build of GCC. I don't know what changes I've > made

PowerPC future machine patches, version 6

This is version 6 of the patches for the PowerPC 'future' machine. There are currently 17 patches in this series. Compared to the V5 patches, the following changes have been made: 1) The length calculation for memory references involving prefixed addresses has been moved to the target hook

[Bug fortran/92122] New: [coarrays, polymophism] Error 'must be a scalar of type LOCK_TYPE'

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92122 Bug ID: 92122 Summary: [coarrays, polymophism] Error 'must be a scalar of type LOCK_TYPE' Product: gcc Version: 10.0 Status: UNCONFIRMED Keywords:

[Bug tree-optimization/92056] [10 Regression] ice in expr_object_size, at tree-object-si ze.c:675 with -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92056 Jakub Jelinek changed: What|Removed |Added CC||jakub at gcc dot gnu.org --- Comment #3

[Bug middle-end/92120] OpenMP 5 – implicit mapping of this->member variable access – "this[:1]" shall be mapped

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92120 --- Comment #2 from Jakub Jelinek --- For OpenMP 5 there is quite a lot of mapping related changes that need to be implemented, first of all, the C/C++ array section support needs to be rewritten because the rules changed there too much and the

Re: [PATCH][ARM] Switch to default sched pressure algorithm

Hi Christophe, > I've noticed that your patch caused a regression: > FAIL: gcc.dg/tree-prof/pr77698.c scan-rtl-dump-times alignments > "internal loop alignment added" 1 That's just a testism - it only tests for loop alignment and doesn't consider the possibility of the loop being jumped into

[Bug c++/57025] Solaris g++ defines __STDC_VERSION__=199901L

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=57025 --- Comment #10 from ro at CeBiTec dot Uni-Bielefeld.DE --- > --- Comment #9 from Alan Coopersmith --- > And I got here this week due to the discussion on >

[Bug fortran/81827] Large compile time with derived-type rrays

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81827 --- Comment #24 from Paul Thomas --- (In reply to Luke Robison from comment #23) > (In reply to Luke Robison from comment #22) > > (In reply to Luke Robison from comment #21) > > > (1) Changing some or all of the "type(levelNN)" definitions to >

[Bug rtl-optimization/92007] [9/10 Regression] ICE: verify_flow_info failed (error: EH edge crosses section boundary in bb 7)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92007 --- Comment #11 from Segher Boessenkool --- Well, it apparently has found new jump threading opportunities after partition_blocks. Are such changes useful? Does it happen often?

[Bug rtl-optimization/92007] [9/10 Regression] ICE: verify_flow_info failed (error: EH edge crosses section boundary in bb 7)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92007 --- Comment #10 from Ilya Leoshkevich --- > Question is how to figure out which to do when. I would always do the former before reload, and always the latter after reload. However, I have a concern regarding this approach: in more complicated

Re: [SVE] PR86753

Richard Biener writes: > On Tue, Oct 15, 2019 at 8:07 AM Prathamesh Kulkarni > wrote: >> >> On Wed, 9 Oct 2019 at 08:14, Prathamesh Kulkarni >> wrote: >> > >> > On Tue, 8 Oct 2019 at 13:21, Richard Sandiford >> > wrote: >> > > >> > > Leaving the main review to Richard, just some comments... >>

Re: Add expr_callee_abi

Richard Biener writes: > On October 14, 2019 2:53:36 PM GMT+02:00, Richard Sandiford > wrote: >>Richard Biener writes: >>> On Fri, Oct 11, 2019 at 4:39 PM Richard Sandiford >>> wrote: This turned out to be useful for the SVE PCS support, and is a >>natural tree-level analogue

[Bug other/92121] Error using GCC 4.9.4 -- arch/x86/Makefile:166: *** CONFIG_RETPOLINE=y,

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92121 --- Comment #3 from Jonathan Wakely --- (It looks like the kernel is simply telling you that you cannot enable retpoline support when using GCC 4.9.4, which seems self-explanatory, and not a GCC bug).

[Bug other/92121] Error using GCC 4.9.4 -- arch/x86/Makefile:166: *** CONFIG_RETPOLINE=y,

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92121 Andrew Pinski changed: What|Removed |Added Status|WAITING |RESOLVED Last reconfirmed|2019-10-16

[Bug other/92121] Error using GCC 4.9.4 -- arch/x86/Makefile:166: *** CONFIG_RETPOLINE=y,

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92121 Jonathan Wakely changed: What|Removed |Added Status|UNCONFIRMED |WAITING Last reconfirmed|

[committed][AArch64] Add partial SVE vector modes

This patch adds extra vector modes that represent a half, quarter or eighth of what an SVE vector can hold. This is useful for describing the memory vector involved in an extending load or truncating store. It might also be useful in future for representing "unpacked" SVE registers, i.e.

[committed][AArch64] Improve poly_int handling in aarch64_layout_frame

I'd used known_lt when converting these conditions to poly_int, but on reflection that was a bad choice. The code isn't just doing a range check; it specifically needs constants that will fit in a certain encoding. Tested on aarch64-linux-gnu and aarch64_be-elf, applied as r277061. Richard

[Bug other/92121] New: Error using GCC 4.9.4 -- arch/x86/Makefile:166: *** CONFIG_RETPOLINE=y,

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92121 Bug ID: 92121 Summary: Error using GCC 4.9.4 -- arch/x86/Makefile:166: *** CONFIG_RETPOLINE=y, Product: gcc Version: 4.9.4 Status: UNCONFIRMED Severity: normal

[committed][AArch64] Add an assert to aarch64_layout_frame

This patch adds an assert that all the individual *_adjust allocations add up to the full frame size. With that safety net, it seemed slightly clearer to use crtl->outgoing_args_size as the final adjustment where appropriate, to match what's used in the comments. This is a bit overkill on its

[committed][AArch64] Use frame reference in aarch64_layout_frame

Using the full path "cfun->machine->frame" in aarch64_layout_frame led to awkward formatting in some follow-on patches, so it seemed worth using a local reference instead. Tested on aarch64-linux-gnu and aarch64_be-elf, applied as r277059. Richard 2019-10-16 Richard Sandiford gcc/

Re: [PATCH] Use __is_same_as for std::is_same and std::is_same_v

On 16/10/19 10:43 +0100, Jonathan Wakely wrote: On 16/10/19 10:42 +0100, Jonathan Wakely wrote: On 12/10/19 18:15 +0200, Romain Geissler wrote: Le sam. 12 oct. 2019 à 17:44, Romain Geissler a écrit : It looks like this creates the following error when I try to bootstrap clang 9.0.0 using

[PATCH] Fix -fdebug-types-section ICE, PR91887

The following makes sure we correctly identify a parm DIE created early in a formal parameter pack during late annotation. Bootstrapped on x86_64-unknown-linux-gnu, testing in progress. OK? Thanks, Richard. 2019-10-16 Richard Biener PR debug/91887 * dwarf2out.c

[Bug middle-end/92120] OpenMP 5 – implicit mapping of this->member variable access – "this[:1]" shall be mapped

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92120 Tobias Burnus changed: What|Removed |Added Keywords||openmp CC|

[Bug tree-optimization/92119] [10 Regression] ICE: SIGSEGV in contains_struct_check (tree.h:3380) with -Os -fno-tree-dce -fno-tree-dse -ftree-slp-vectorize

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92119 Richard Biener changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug middle-end/92120] New: OpenMP 5 – implicit mapping of this->member variable access – "this[:1]" shall be mapped

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92120 Bug ID: 92120 Summary: OpenMP 5 – implicit mapping of this->member variable access – "this[:1]" shall be mapped Product: gcc Version: 10.0 Status: UNCONFIRMED

[Bug tree-optimization/92119] [10 Regression] ICE: SIGSEGV in contains_struct_check (tree.h:3380) with -Os -fno-tree-dce -fno-tree-dse -ftree-slp-vectorize

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92119 --- Comment #2 from Richard Biener --- Author: rguenth Date: Wed Oct 16 10:05:21 2019 New Revision: 277057 URL: https://gcc.gnu.org/viewcvs?rev=277057=gcc=rev Log: 2019-10-16 Richard Biener PR tree-optimization/92119 *

[PATCH] Fix PR92119

Committed as obvious. Richard. 2019-10-16 Richard Biener PR tree-optimization/92119 * tree-vect-patterns.c (vect_recog_rotate_pattern): Guard against missing bswap lhs. Index: gcc/tree-vect-patterns.c

[Bug tree-optimization/92119] [10 Regression] ICE: SIGSEGV in contains_struct_check (tree.h:3380) with -Os -fno-tree-dce -fno-tree-dse -ftree-slp-vectorize

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92119 Richard Biener changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Last reconfirmed|

[Bug tree-optimization/92033] ICE during dom with -march=armv8.2-a+sve

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92033 --- Comment #4 from rsandifo at gcc dot gnu.org --- Author: rsandifo Date: Wed Oct 16 09:50:44 2019 New Revision: 277056 URL: https://gcc.gnu.org/viewcvs?rev=277056=gcc=rev Log: Deal with incoming POLY_INT_CST ranges (PR92033) This patch

Urgent - Regarding SMS Count

Hi Team, Please kindly confirm the attached monthly sms counts and get back to us asap as we are about to release the payment for September sms push, to release October SMS payment in few days to come as well. Download link http://emaila.drbatras.com/gtrack?clientid=283=

Re: [PATCH V2] rs6000: -flto forgets 'no-vsx' function attributes (PR target/70010)

Hi! On Wed, Oct 16, 2019 at 04:50:21PM +0800, Jiufu Guo wrote: > In PR70010, a function is marked with target(no-vsx) to disable VSX code > generation. To avoid VSX code generation, this function should not be > inlined into VSX function. > > In previous implementation, target of non-vsx is

Re: [PATCH] Use __is_same_as for std::is_same and std::is_same_v

On 16/10/19 10:42 +0100, Jonathan Wakely wrote: On 12/10/19 18:15 +0200, Romain Geissler wrote: Le sam. 12 oct. 2019 à 17:44, Romain Geissler a écrit : It looks like this creates the following error when I try to bootstrap clang 9.0.0 using the latest gcc and libstdc++ from trunk. Note that

Re: [PATCH] Use __is_same_as for std::is_same and std::is_same_v

On 12/10/19 18:15 +0200, Romain Geissler wrote: Le sam. 12 oct. 2019 à 17:44, Romain Geissler a écrit : It looks like this creates the following error when I try to bootstrap clang 9.0.0 using the latest gcc and libstdc++ from trunk. Note that with g++, there is no problem, however it looks

Re: [PATCH] Fix PR91975, tame PRE some more

On Mon, 7 Oct 2019, Richard Biener wrote: > > The following tries to address the issue that PRE is quite happy > to introduce new IVs in loops just because it can compute some > constant value on the loop entry edge. In principle there's > already code that should work against that but it

Re: [PATCH 2/4] Use gomp_map_val for OpenACC host-to-device address translation

Hi! On 2019-10-06T15:32:35-0700, Julian Brown wrote: > This patch uses gomp_map_val for OpenACC host-to-device address > translation instead of open-coding the device address calculation. (As has been discussed before.) (And then, also see "'GOACC_parallel_keyed'

[Bug tree-optimization/60206] IVOPT has no idea of inline asm

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=60206 Hongtao.liu changed: What|Removed |Added CC||crazylht at gmail dot com --- Comment #9

[Bug debug/91968] DW_AT_low_pc missing for DW_TAG_label with LTO

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91968 Richard Biener changed: What|Removed |Added Status|ASSIGNED|RESOLVED Known to work|

[Bug tree-optimization/92119] New: [10 Regression] ICE: SIGSEGV in contains_struct_check (tree.h:3380) with -Os -fno-tree-dce -fno-tree-dse -ftree-slp-vectorize

mpression algorithms: zlib zstd gcc version 10.0.0 20191016 (experimental) (GCC)

[Bug tree-optimization/53947] [meta-bug] vectorizer missed-optimizations

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53947 Bug 53947 depends on bug 91790, which changed state. Bug 91790 Summary: ICE: verify_ssa failed (error: definition in block 2 follows the use) https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91790 What|Removed

[Bug tree-optimization/91790] ICE: verify_ssa failed (error: definition in block 2 follows the use)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91790 --- Comment #4 from Richard Biener --- Author: rguenth Date: Wed Oct 16 09:25:34 2019 New Revision: 277055 URL: https://gcc.gnu.org/viewcvs?rev=277055=gcc=rev Log: 2019-10-16 Richard Biener Backport from mainline 2019-10-04

[Bug tree-optimization/91790] ICE: verify_ssa failed (error: definition in block 2 follows the use)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91790 Richard Biener changed: What|Removed |Added Status|ASSIGNED|RESOLVED Known to work|

[Bug c++/91606] [9 regression] Optimization leads to invalid code

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91606 --- Comment #15 from Richard Biener --- Author: rguenth Date: Wed Oct 16 09:25:34 2019 New Revision: 277055 URL: https://gcc.gnu.org/viewcvs?rev=277055=gcc=rev Log: 2019-10-16 Richard Biener Backport from mainline 2019-10-04

[Bug debug/91968] DW_AT_low_pc missing for DW_TAG_label with LTO

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91968 --- Comment #6 from Richard Biener --- Author: rguenth Date: Wed Oct 16 09:25:34 2019 New Revision: 277055 URL: https://gcc.gnu.org/viewcvs?rev=277055=gcc=rev Log: 2019-10-16 Richard Biener Backport from mainline 2019-10-04

[Bug tree-optimization/91812] [7/8/9 Regression] GCC ignores volatile modifier

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91812 --- Comment #9 from Richard Biener --- Author: rguenth Date: Wed Oct 16 09:25:34 2019 New Revision: 277055 URL: https://gcc.gnu.org/viewcvs?rev=277055=gcc=rev Log: 2019-10-16 Richard Biener Backport from mainline 2019-10-04

[Bug lto/91772] [8/9 Regression] ICE in add_dwarf_attr, at dwarf2out.c:4412 since r259749

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91772 --- Comment #7 from Richard Biener --- Author: rguenth Date: Wed Oct 16 09:25:34 2019 New Revision: 277055 URL: https://gcc.gnu.org/viewcvs?rev=277055=gcc=rev Log: 2019-10-16 Richard Biener Backport from mainline 2019-10-04

[Bug c++/91606] [9 regression] Optimization leads to invalid code

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91606 Richard Biener changed: What|Removed |Added Status|ASSIGNED|RESOLVED Known to work|

[Bug c++/91369] Implement P0784R7: constexpr new

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91369 --- Comment #16 from Jonathan Wakely --- I'll commit a patch to add std::construct_at today or tomorrow.

[Bug c++/91369] Implement P0784R7: constexpr new

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91369 --- Comment #15 from Jonathan Wakely --- That's not valid, because operator new is not a constexpr function. You have to use a new-expression (that resolves to one of the standard operator new allocation functions), or std::allocator::allocate,

[Bug tree-optimization/92115] [10 Regression] ICE in gimple_cond_get_ops_from_tree, at gimple-expr.c:577

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92115 --- Comment #3 from Ilya Leoshkevich --- Thanks again, Jakub. Arseny, how did you find this? Did you just run the regtest? I wonder why didn't I see it during my test runs.

[Bug middle-end/92118] warning with [-Wmaybe-uninitialized] in -O1

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92118 Andrew Pinski changed: What|Removed |Added Component|c |middle-end Severity|normal

Re: Improving GCC's line table information to help GDB

On Tue, Oct 15, 2019 at 9:58 PM Luis Machado wrote: > > Hi, > > I'd like to get some feedback from the compiler's side before > implementing a fix for this line numbering problem. I also want to make > sure i fix it in the right tool. > > This is related to this bug report in GDB's bugzilla: >

Re: [PATCH] OpenACC reference count consistency checking

Hi! On 2019-10-03T09:35:05-0700, Julian Brown wrote: > This patch provides self-checking for consistency of the OpenACC > reference-counting implementation in libgomp. Earlier submissions included description what exactly this is doing,

[Bug c/92118] New: warning with [-Wmaybe-uninitialized] in -O1

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92118 Bug ID: 92118 Summary: warning with [-Wmaybe-uninitialized] in -O1 Product: gcc Version: 10.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: c

[PATCH V2] rs6000: -flto forgets 'no-vsx' function attributes (PR target/70010)

Hi, In PR70010, a function is marked with target(no-vsx) to disable VSX code generation. To avoid VSX code generation, this function should not be inlined into VSX function. In previous implementation, target of non-vsx is treated as subset target with vsx, even user set no-vsx attribute.

[Bug c/92117] New: Warning from -Wbad-function-cast when casting from bool to int

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92117 Bug ID: 92117 Summary: Warning from -Wbad-function-cast when casting from bool to int Product: gcc Version: 5.4.0 Status: UNCONFIRMED Severity: normal

[Bug fortran/92113] [8 regression] r276673 causes segfault in gfortran.dg/pr51434.f90

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92113 Richard Biener changed: What|Removed |Added Known to work||8.3.0 Target Milestone|---

[Bug middle-end/92110] too many -Warray-bounds warnings for a loop buffer overflow

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92110 Richard Biener changed: What|Removed |Added Keywords||diagnostic

[Bug tree-optimization/92111] [10 Regression] ICE during GIMPLE pass: dom

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92111 Richard Biener changed: What|Removed |Added Keywords||lto CC|

Re: [PATCH][AArch64] Fix symbol offset limit

Wilco Dijkstra writes: > Hi Richard, >> Sure, the "extern array of unknown size" case isn't about section anchors. >> But this part of my message (snipped above) was about the other case >> (objects of known size), and applied to individual objects as well as >> section anchors. >> >> What I was

[Bug tree-optimization/92115] [10 Regression] ICE in gimple_cond_get_ops_from_tree, at gimple-expr.c:577

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92115 --- Comment #2 from Richard Biener --- (In reply to Jakub Jelinek from comment #1) > Created attachment 47044 [details] > gcc10-pr92115.patch > > Untested fix. The other two spots in the same file seems to be dealing with > integer conditions

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