Hi Tamar,
On Wed, 15 May 2024 at 11:28, Tamar Christina
wrote:
> Hi All,
>
> This converts the single alternative patterns to the new compact syntax
> such
> that when I add the new alternatives it's clearer what's being changed.
>
> Note that this will spew out a bunch of warnings from geninsn
Hi Andrew,
On Fri, May 3, 2024 at 8:50 PM Andrew Pinski
wrote:
> This patch adds Qualcomm's new oryon-1 core; this is enough
> to recongize the core and later on will add the tuning structure.
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-cores.def (oryon-1): New entry.
> *
Hi Srinath,
On 3/10/20 6:19 PM, Srinath Parvathaneni wrote:
Hello Kyrill,
This patch addresses all the comments in patch version v2.
(version v2)
https://gcc.gnu.org/pipermail/gcc-patches/2020-February/540417.html
Hello,
This patch is part of MVE ACLE intrinsics framework.
The
Hi Srinath,
On 3/10/20 6:19 PM, Srinath Parvathaneni wrote:
Hello Kyrill,
This patch addresses all the comments in patch version v2.
(version v2)
https://gcc.gnu.org/pipermail/gcc-patches/2020-February/540416.html
Hello,
This patch is part of MVE ACLE intrinsics framework.
This
Hi Srinath,
On 3/10/20 6:19 PM, Srinath Parvathaneni wrote:
Hello Kyrill,
This patch addresses all the comments in patch version v2.
(version v2)
https://gcc.gnu.org/pipermail/gcc-patches/2020-February/540415.html
Hello,
This patch creates the required framework for MVE ACLE
On 3/11/20 5:59 PM, Kyrill Tkachov wrote:
Hi Delia,
On 3/11/20 5:49 PM, Delia Burduv wrote:
This patch fixes a bug introduced by my earlier patch (
https://gcc.gnu.org/pipermail/gcc-patches/2020-March/541680.html ).
It introduces a new scalar builtin type that was missing in the original
Hi Delia,
On 3/11/20 5:49 PM, Delia Burduv wrote:
This patch fixes a bug introduced by my earlier patch (
https://gcc.gnu.org/pipermail/gcc-patches/2020-March/541680.html ).
It introduces a new scalar builtin type that was missing in the original
patch.
Bootstrapped cleanly on
c__lse):
The scratch register need not be early-clobber. Document the reason
why we cannot use ST.
From-SVN: r265703
On 2/27/20, 12:06 PM, "Kyrill Tkachov" wrote:
Hi Sebastian,
On 2/27/20 4:53 PM, Pop, Sebastian wrote:
>
> Hi,
>
Hi Jakub,
On 3/11/20 7:22 AM, Jakub Jelinek wrote:
Hi!
abs_hwi asserts that the argument is not HOST_WIDE_INT_MIN and as the
(invalid) testcase shows, the function can be called with such an offset.
The following patch is IMHO minimal fix, absu_hwi unlike abs_hwi
allows even
that value and
Hi all,
The two affected SVE2 patterns in this patch output a movprfx'ed
instruction in their second alternative
but don't set the "movprfx" attribute, which will result in the wrong
instruction length being assumed by the midend.
This patch fixes that in the same way as the other SVE
.
(neon_vld4): Likewise.
(neon_vld4qa): Likewise.
(neon_vld4qb): Likewise.
(neon_vld4_dup): Likewise.
(neon_vld2_dupv8bf): New.
(neon_vld3_dupv8bf): Likewise.
(neon_vld4_dupv8bf): Likewise.
Kyrill
Thanks,
Delia
On 3/4/20 5:20 PM, Kyrill Tkachov wrote:
Hi Delia,
On 3/4/20
new iterators.
(neon_vst3qa): Used new iterators.
(neon_vst3qb): Used new iterators.
(neon_vst4): Used new iterators.
(neon_vst4): Used new iterators.
(neon_vst4qa): Used new iterators.
(neon_vst4qb): Used new iterators.
Thanks,
Delia
On 3/4/20 5:20 PM, Kyrill Tkachov
On 3/5/20 11:22 AM, Kyrill Tkachov wrote:
Hi Delia,
On 3/4/20 5:20 PM, Delia Burduv wrote:
Hi,
This is the latest version of the patch.
Thanks,
Delia
On 2/21/20 11:41 AM, Kyrill Tkachov wrote:
Hi Delia,
On 2/19/20 5:23 PM, Delia Burduv wrote:
Hi,
Here is the latest version
Hi Delia,
On 3/4/20 5:20 PM, Delia Burduv wrote:
Hi,
This is the latest version of the patch.
Thanks,
Delia
On 2/21/20 11:41 AM, Kyrill Tkachov wrote:
Hi Delia,
On 2/19/20 5:23 PM, Delia Burduv wrote:
Hi,
Here is the latest version of the patch. It just has some minor
formatting changes
, Kyrill Tkachov wrote:
Hi Delia,
On 2/19/20 5:25 PM, Delia Burduv wrote:
Hi,
Here is the latest version of the patch. It just has some minor
formatting changes that were brought up by Richard Sandiford in the
AArch64 patches
Thanks,
Delia
On 1/22/20 5:29 PM, Delia Burduv wrote:
> Ping.
&g
Hi Delia,
On 3/4/20 2:05 PM, Delia Burduv wrote:
Hi,
The previous version of this patch shared part of its code with the
store intrinsics patch
(https://gcc.gnu.org/ml/gcc-patches/2020-03/msg00145.html) so I removed
any duplicated code. This patch now depends on the previously mentioned
store
On 3/4/20 2:14 PM, Tamar Christina wrote:
Hi Kyrill,
Ok for backporting this patch to GCC 8 and GCC 9?
Ok assuming bootstrap and test shows no problems.
Thanks,
Kyrill
Thanks,
Tamar
-Original Message-
From: gcc-patches-ow...@gcc.gnu.org
On Behalf Of Kyrill Tkachov
Sent
Hi Dennis,
On 3/2/20 5:41 PM, Dennis Zhang wrote:
Hi all,
On 17/01/2020 16:46, Dennis Zhang wrote:
> Hi all,
>
> This patch is part of a series adding support for Armv8.6-A features.
> It depends on Arm BFMode patch
> https://gcc.gnu.org/ml/gcc-patches/2019-12/msg01448.html
>
> This patch
Hi Sebastian,
On 2/27/20 4:53 PM, Pop, Sebastian wrote:
Hi,
is somebody already working on backporting -moutline-atomics to gcc
8.x and 9.x branches?
I'm not aware of such work going on.
Thanks,
Kyrill
Thanks,
Sebastian
Hi Mihail,
On 2/20/20 4:15 PM, Mihail Ionescu wrote:
Hi,
This patch adds a new multilib for armv8.1-m.main+mve with hard float
abi. For
armv8.1-m.main+mve soft and softfp, the v8-M multilibs will be reused.
The following mappings are also updated:
"-mfloat-abi=hard
Hi Mihail,
On 2/27/20 2:44 PM, Mihail Ionescu wrote:
Hi Kyrill,
On 02/27/2020 11:09 AM, Kyrill Tkachov wrote:
Hi Mihail,
On 2/27/20 10:27 AM, Mihail Ionescu wrote:
Hi,
This patch adds support for the bf16 vector create, get, set,
duplicate and reinterpret intrinsics.
ACLE documents
Hi Joel,
On 2/27/20 2:31 PM, Joel Hutton wrote:
The message for conflicting mcpu and march previously printed the
architecture of the CPU instead of the CPU name, as well as omitting the
extensions to the march string. This patch corrects both errors. This
patch fixes PR target/87612.
before:
Hi Mihail,
On 2/27/20 10:27 AM, Mihail Ionescu wrote:
Hi,
This patch adds support for the bf16 vector create, get, set,
duplicate and reinterpret intrinsics.
ACLE documents are at https://developer.arm.com/docs/101028/latest
ISA documents are at https://developer.arm.com/docs/ddi0596/latest
Hi Dennis,
On 2/25/20 5:18 PM, Dennis Zhang wrote:
Hi Kyrill,
On 25/02/2020 12:18, Kyrill Tkachov wrote:
Hi Dennis,
On 2/25/20 11:54 AM, Dennis Zhang wrote:
Hi all,
On 07/01/2020 12:12, Dennis Zhang wrote:
> Hi all,
>
> This patch is part of a series adding support for Armv8.6-A
Hi Christophe,
On 2/24/20 2:16 PM, Christophe Lyon wrote:
Ping?
I'd also like to backport this and the main patch (svn r279463,
r10-5505-ge24f6408df1e4c5e8c09785d7b488c492dfb68b3)
to the gcc-9 branch.
I found the problem addressed by this patch while validating the
backport to gcc-9: although
Hi Dennis,
On 2/25/20 11:54 AM, Dennis Zhang wrote:
Hi all,
On 07/01/2020 12:12, Dennis Zhang wrote:
> Hi all,
>
> This patch is part of a series adding support for Armv8.6-A features.
> It depends on the patch enabling Arm BFmode
> https://gcc.gnu.org/ml/gcc-patches/2019-12/msg01448.html
>
>
it deliberate that this pattern name has a '*' prefix? doloop_end
is a named expansion pattern according to md.texi.
R.
21.02.2020 18:30, Kyrill Tkachov wrote:
+;; Originally expanded by 'doloop_end'.
+(define_insn "doloop_end_internal"
We usually prefer to name these patterns with
Hi Andrea,
On 2/19/20 1:01 PM, Andrea Corallo wrote:
Hi all,
Second version of the patch here addressing comments.
This patch enables the Armv8.1-M Mainline LOB (low overhead branch)
extension
low overhead loops (LOL) feature by using the 'loop-doloop' pass.
Given the following function:
Hi Delia,
On 2/19/20 5:25 PM, Delia Burduv wrote:
Hi,
Here is the latest version of the patch. It just has some minor
formatting changes that were brought up by Richard Sandiford in the
AArch64 patches
Thanks,
Delia
On 1/22/20 5:29 PM, Delia Burduv wrote:
> Ping.
>
> I will change the tests
On 2/21/20 11:51 AM, Kyrill Tkachov wrote:
Hi Mihail,
On 2/19/20 4:27 PM, Mihail Ionescu wrote:
Hi Christophe,
On 01/23/2020 09:34 AM, Christophe Lyon wrote:
> On Mon, 20 Jan 2020 at 19:01, Mihail Ionescu
> wrote:
>>
>> Hi,
>>
>> This patch fixes the scalar s
Hi Mihail,
On 2/19/20 4:27 PM, Mihail Ionescu wrote:
Hi Christophe,
On 01/23/2020 09:34 AM, Christophe Lyon wrote:
> On Mon, 20 Jan 2020 at 19:01, Mihail Ionescu
> wrote:
>>
>> Hi,
>>
>> This patch fixes the scalar shifts tests added in:
>>
Hi Dennis,
On 2/11/20 12:03 PM, Dennis Zhang wrote:
Hi all,
On 16/12/2019 13:45, Dennis Zhang wrote:
> Hi all,
>
> This patch is part of a series adding support for Armv8.6-A features.
> It depends on the Arm Armv8.6-A CLI patch,
> https://gcc.gnu.org/ml/gcc-patches/2019-11/msg02195.html.
> It
. The changes are minor, so let me know if
there is anything else to fix or if it can be committed.
Thank you,
Delia
On 1/30/20 2:55 PM, Kyrill Tkachov wrote:
Hi Delia,
On 1/28/20 4:44 PM, Delia Burduv wrote:
Ping.
*From
On 2/14/20 4:34 PM, Srinath Parvathaneni wrote:
Hello Kyrill,
In this patch (v2) all the review comments mentioned in previous patch
(v1) are
addressed.
(v1) https://gcc.gnu.org/ml/gcc-patches/2019-12/msg01401.html
#
Hello,
This patch is part of MVE ACLE intrinsics
Hi Srinath,
On 2/14/20 4:34 PM, Srinath Parvathaneni wrote:
Hello Kyrill,
In this patch (v2) all the review comments mentioned in previous patch
(v1) are
addressed.
(v1) https://gcc.gnu.org/ml/gcc-patches/2019-12/msg01395.html
#
Hello,
This patch is part of MVE ACLE
Hi Srinath,
On 2/14/20 4:26 PM, Srinath Parvathaneni wrote:
Hi Kyrill,
> This patch series depends on upstream patches "Armv8.1-M Mainline
Security Extension" [4],
> "CLI and multilib support for Armv8.1-M Mainline MVE extensions" [5]
and "support for Armv8.1-M
> Mainline scalar shifts"
Hi Stam,
On 2/10/20 1:35 PM, Stam Markianos-Wright wrote:
On 2/3/20 11:20 AM, Stam Markianos-Wright wrote:
>
>
> On 1/27/20 3:54 PM, Stam Markianos-Wright wrote:
>>
>> On 1/16/20 4:05 PM, Stam Markianos-Wright wrote:
>>>
>>>
>>> On 1/10/20 6:48 PM, Stam Markianos-Wright wrote:
On 2/3/20 5:18 PM, Mihail Ionescu wrote:
Hi all,
I've regenerated arm-tables.opt in config/arm to replace the improperly
generated arm-tables.opt file from "[PATCH, GCC/ARM, 2/10] Add command
line support for Armv8.1-M Mainline"
(9722215a027b68651c3c7a8af9204d033197e9c0).
2020-02-03
On 2/4/20 1:49 PM, Christophe Lyon wrote:
On Mon, 3 Feb 2020 at 18:20, Mihail Ionescu
wrote:
>
> Hi,
>
> We noticed that the profile for armv8.1-m.main was not set in
arm-cpus.in
> , which led to TARGET_ARM_ARCH_PROFILE and _ARM_ARCH_PROFILE not being
> defined properly.
>
>
>
>
Hi Delia,
On 1/28/20 4:44 PM, Delia Burduv wrote:
Ping.
*From:* Delia Burduv
*Sent:* 22 January 2020 17:26
*To:* gcc-patches@gcc.gnu.org
*Cc:* ni...@redhat.com ; Richard Earnshaw
; Ramana Radhakrishnan
; Kyrylo
On 1/30/20 2:42 PM, Stam Markianos-Wright wrote:
On 1/28/20 10:35 AM, Kyrill Tkachov wrote:
Hi Stam,
On 1/8/20 3:18 PM, Stam Markianos-Wright wrote:
On 12/10/19 5:03 PM, Kyrill Tkachov wrote:
Hi Stam,
On 11/15/19 5:26 PM, Stam Markianos-Wright wrote:
Pinging with more correct
Hi Stam,
On 1/8/20 3:18 PM, Stam Markianos-Wright wrote:
On 12/10/19 5:03 PM, Kyrill Tkachov wrote:
Hi Stam,
On 11/15/19 5:26 PM, Stam Markianos-Wright wrote:
Pinging with more correct maintainers this time :)
Also would need to backport to gcc7,8,9, but need to get this approved
first
On 12/18/19 1:23 PM, Mihail Ionescu wrote:
Hi Kyrill,
On 12/11/2019 05:50 PM, Kyrill Tkachov wrote:
> Hi Mihail,
>
> On 11/14/19 1:54 PM, Mihail Ionescu wrote:
>> Hi,
>>
>> This patch adds the new scalar shift instructions for Armv8.1-M
>> Mainline
Hi Richard, Wilco,
On 1/17/20 8:43 AM, Richard Sandiford wrote:
Wilco Dijkstra writes:
> Testing shows the setting of 32:16 for jump alignment has a
significant codesize
> cost, however it doesn't make a difference in performance. So set
jump-align
> to 4 to get 1.6% codesize improvement.
On 1/14/20 1:50 PM, Christophe Lyon wrote:
On Mon, 13 Jan 2020 at 14:49, Kyrill Tkachov
wrote:
Hi Christophe,
On 12/17/19 3:31 PM, Kyrill Tkachov wrote:
On 12/17/19 2:33 PM, Christophe Lyon wrote:
On Tue, 17 Dec 2019 at 11:34, Kyrill Tkachov
wrote:
Hi Christophe,
On 11/18/19 9:00 AM
On 12/18/19 1:26 PM, Mihail Ionescu wrote:
Hi Kyrill,
On 12/17/2019 10:26 AM, Kyrill Tkachov wrote:
Hi Mihail,
On 12/16/19 6:29 PM, Mihail Ionescu wrote:
Hi Kyrill,
On 11/12/2019 09:55 AM, Kyrill Tkachov wrote:
Hi Mihail,
On 10/23/19 10:26 AM, Mihail Ionescu wrote:
[PATCH, GCC/ARM, 4
Hi Christophe,
On 12/17/19 3:31 PM, Kyrill Tkachov wrote:
On 12/17/19 2:33 PM, Christophe Lyon wrote:
On Tue, 17 Dec 2019 at 11:34, Kyrill Tkachov
wrote:
Hi Christophe,
On 11/18/19 9:00 AM, Christophe Lyon wrote:
On Wed, 13 Nov 2019 at 15:46, Christophe Lyon
wrote:
On Tue, 12 Nov 2019
Hi Stam,
On 1/10/20 6:47 PM, Stam Markianos-Wright wrote:
Hi all,
This patch is part 2 of Bfloat16_t enablement in the ARM back-end.
This new type is constrained using target hooks TARGET_INVALID_CONVERSION,
TARGET_INVALID_UNARY_OP, TARGET_INVALID_BINARY_OP so that it may only
be used
Hi Stam,
On 1/10/20 6:45 PM, Stam Markianos-Wright wrote:
Hi all,
This is a respin of patch:
https://gcc.gnu.org/ml/gcc-patches/2019-12/msg01448.html
which has now been split into two (similar to the Aarch64 version).
This is patch 1 of 2 and adds Bfloat type support to the ARM back-end.
It
On 1/8/20 11:26 AM, Matthew Malcomson wrote:
Hi everyone,
I'm writing this email to summarise & publicise the state of this patch
series, especially the difficulties around approval for GCC 10 mentioned
on IRC.
The main obstacle seems to be that no maintainer feels they have enough
Hi all,
This patch adds initial entries for notable features that went in to GCC
10 on the arm and aarch64 front.
The list is by no means complete so if you'd like your contribution
called please shout or post a follow-up patch.
It is, nevertheless, a decent start at the relevant sections in
Hi Dennis,
On 12/12/19 5:30 PM, Dennis Zhang wrote:
Hi all,
On 22/11/2019 14:33, Dennis Zhang wrote:
> Hi all,
>
> This patch is part of a series adding support for Armv8.6-A features.
> It enables options including -march=armv8.6-a, +i8mm and +bf16.
> The +i8mm and +bf16 features are optional
Hi Srinath,
On 11/14/19 7:13 PM, Srinath Parvathaneni wrote:
Hello,
This patch supports following MVE ACLE intrinsics with binary operand.
vsubq_n_f16, vsubq_n_f32, vbrsrq_n_f16, vbrsrq_n_f32, vcvtq_n_f16_s16,
vcvtq_n_f32_s32, vcvtq_n_f16_u16, vcvtq_n_f32_u32, vcreateq_f16,
vcreateq_f32.
Hi Srinath,
On 11/14/19 7:13 PM, Srinath Parvathaneni wrote:
Hello,
This patch supports following MVE ACLE intrinsics with unary operand.
vctp16q, vctp32q, vctp64q, vctp8q, vpnot.
Please refer to M-profile Vector Extension (MVE) intrinsics [1] for
more details.
[1]
Hi Srinath,
On 11/14/19 7:13 PM, Srinath Parvathaneni wrote:
Hello,
This patch supports following MVE ACLE intrinsics with unary operand.
vmvnq_n_s16, vmvnq_n_s32, vrev64q_s8, vrev64q_s16, vrev64q_s32,
vcvtq_s16_f16, vcvtq_s32_f32,
vrev64q_u8, vrev64q_u16, vrev64q_u32, vmvnq_n_u16,
Hi Srinath,
On 11/14/19 7:12 PM, Srinath Parvathaneni wrote:
Hello,
This patch supports MVE ACLE intrinsics vcvtq_f16_s16, vcvtq_f32_s32,
vcvtq_f16_u16, vcvtq_f32_u32n
vrndxq_f16, vrndxq_f32, vrndq_f16, vrndq_f32, vrndpq_f16, vrndpq_f32,
vrndnq_f16, vrndnq_f32,
vrndmq_f16, vrndmq_f32,
Hi Srinath,
On 11/14/19 7:12 PM, Srinath Parvathaneni wrote:
Hello,
This patch is part of MVE ACLE intrinsics framework.
The patch supports the use of emulation for the double-precision
arithmetic
operations for MVE. This changes are to support the MVE ACLE
intrinsics which
operates on
On 11/14/19 7:12 PM, Srinath Parvathaneni wrote:
Hello,
This patch supports MVE ACLE intrinsics vst4q_s8, vst4q_s16,
vst4q_s32, vst4q_u8,
vst4q_u16, vst4q_u32, vst4q_f16 and vst4q_f32.
In this patch arm_mve_builtins.def file is added to the source code in
which the
builtins for MVE ACLE
Hi Srinath,
On 11/14/19 7:12 PM, Srinath Parvathaneni wrote:
Hello,
This patch is part of MVE ACLE intrinsics framework.
This patches add support to update (read/write) the APSR (Application
Program Status Register)
register and FPSCR (Floating-point Status and Control Register)
register for
On 11/14/19 7:12 PM, Srinath Parvathaneni wrote:
Hello,
This patch creates the required framework for MVE ACLE intrinsics.
The following changes are done in this patch to support MVE ACLE
intrinsics.
Header file arm_mve.h is added to source code, which contains the
definitions of MVE
On 12/18/19 5:00 PM, Mihail Ionescu wrote:
Hi Kyrill,
On 12/18/2019 02:13 PM, Kyrill Tkachov wrote:
> Hi Mihail,
>
> On 11/8/19 4:52 PM, Mihail Ionescu wrote:
>> Hi,
>>
>> This patch adds CLI and multilib support for Armv8.1-M MVE to the Arm
>> backend.
>&g
On 12/18/19 1:38 PM, Mihail Ionescu wrote:
Hi,
On 11/12/2019 10:23 AM, Kyrill Tkachov wrote:
On 10/23/19 10:26 AM, Mihail Ionescu wrote:
[PATCH, GCC/ARM, 9/10] Call nscall function with blxns
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline
Hi Mihail,
On 11/8/19 4:52 PM, Mihail Ionescu wrote:
Hi,
This patch adds CLI and multilib support for Armv8.1-M MVE to the Arm
backend.
Two new option added for v8.1-m.main: "+mve" for integer MVE
instructions only
and "+mve.fp" for both integer and single-precision/half-precision
Hi Wilco,
On 12/17/19 4:03 PM, Wilco Dijkstra wrote:
Hi Richard,
> This changelog entry is inadequate. It's also not in the correct style.
>
> It should say what has changed, not just that it has changed.
Sure, but there is often no useful space for that. We should auto generate
changelogs
On 12/17/19 2:33 PM, Christophe Lyon wrote:
On Tue, 17 Dec 2019 at 11:34, Kyrill Tkachov
wrote:
Hi Christophe,
On 11/18/19 9:00 AM, Christophe Lyon wrote:
On Wed, 13 Nov 2019 at 15:46, Christophe Lyon
wrote:
On Tue, 12 Nov 2019 at 12:13, Richard Earnshaw (lists)
wrote:
On 18/10/2019 14
Hi Christophe,
On 11/18/19 9:00 AM, Christophe Lyon wrote:
On Wed, 13 Nov 2019 at 15:46, Christophe Lyon
wrote:
>
> On Tue, 12 Nov 2019 at 12:13, Richard Earnshaw (lists)
> wrote:
> >
> > On 18/10/2019 14:18, Christophe Lyon wrote:
> > > + bool not_supported = arm_arch_notm || flag_pic
Hi Mihail,
On 12/16/19 6:29 PM, Mihail Ionescu wrote:
Hi Kyrill,
On 11/12/2019 09:55 AM, Kyrill Tkachov wrote:
Hi Mihail,
On 10/23/19 10:26 AM, Mihail Ionescu wrote:
[PATCH, GCC/ARM, 4/10] Clear GPR with CLRM
Hi,
=== Context ===
This patch is part of a patch series to add support
Hi Mihail,
On 12/16/19 6:29 PM, Mihail Ionescu wrote:
Hi Kyrill,
On 11/06/2019 04:12 PM, Kyrill Tkachov wrote:
Hi Mihail,
On 10/23/19 10:26 AM, Mihail Ionescu wrote:
[PATCH, GCC/ARM, 3/10] Save/restore FPCXTNS in nsentry functions
Hi,
=== Context ===
This patch is part of a patch series
Hi Mihail,
On 12/16/19 6:28 PM, Mihail Ionescu wrote:
Hi Kyrill
On 11/06/2019 03:59 PM, Kyrill Tkachov wrote:
Hi Mihail,
On 11/4/19 4:49 PM, Kyrill Tkachov wrote:
Hi Mihail,
On 10/23/19 10:26 AM, Mihail Ionescu wrote:
> [PATCH, GCC/ARM, 2/10] Add command line support
>
Hi Andrew,
On 3/15/19 1:18 AM, apin...@marvell.com wrote:
From: Andrew Pinski
Hi,
On OcteonTX2, ld1r and ld1 (with a single lane) are split
into two different micro-ops unlike most other targets.
This adds three extra costs to the cost table:
ld1_dup: used for "ld1r {v0.4s}, [x0]"
Hi Matthew,
Martin is the authority on this but I have a small comment inline...
On 12/12/19 3:19 PM, Matthew Malcomson wrote:
This is an analogous option to --bootstrap-asan to configure. It allows
bootstrapping GCC using HWASAN.
For the same reasons as for ASAN we have to avoid using the
Hi Srinath,
On 11/14/19 7:12 PM, Srinath Parvathaneni wrote:
Hello,
This patches series is to support Arm MVE ACLE intrinsics.
Please refer to Arm reference manual [1] and MVE intrinsics [2] for
more details.
Please refer to Chapter 13 MVE ACLE [3] for MVE intrinsics concepts.
This patch
Hi Mihail,
On 11/14/19 1:54 PM, Mihail Ionescu wrote:
Hi,
This is part of a series of patches where I am trying to add new
instructions for Armv8.1-M Mainline to the arm backend.
This patch is adding the following instructions:
ASRL (imm)
LSLL (imm)
LSRL (imm)
ChangeLog entry are as follow:
Hi Mihail,
On 11/14/19 1:54 PM, Mihail Ionescu wrote:
Hi,
This patch adds the new scalar shift instructions for Armv8.1-M
Mainline to the arm backend.
This patch is adding the following instructions:
ASRL (reg)
LSLL (reg)
Sorry for the delay, very busy time for GCC development :(
Hi all,
On 12/11/19 9:41 AM, Stam Markianos-Wright wrote:
On 12/11/19 3:48 AM, Jeff Law wrote:
> On Mon, 2019-12-09 at 13:40 +, Stam Markianos-Wright wrote:
>>
>> On 12/3/19 10:31 AM, Stam Markianos-Wright wrote:
>>>
>>> On 12/2/19 9:27 PM, Joseph Myers wrote:
On Mon, 2 Dec 2019,
Hi Stam,
On 11/15/19 5:26 PM, Stam Markianos-Wright wrote:
Pinging with more correct maintainers this time :)
Also would need to backport to gcc7,8,9, but need to get this approved
first!
Sorry for the delay.
Thank you,
Stam
Forwarded Message
Subject: Re:
Sorry, wrong list address from my side, please ignore.
Kyrill
On 12/5/19 10:59 AM, Kyrill Tkachov wrote:
Hi all,
This patch implements the .cfi_negate_ra_state to be consistent with
LLVM (https://reviews.llvm.org/D50136). The relevant DWARF code
DW_CFA_AARCH64_negate_ra_state
is multiplexed
Hi all,
This patch implements the .cfi_negate_ra_state to be consistent with
LLVM (https://reviews.llvm.org/D50136). The relevant DWARF code
DW_CFA_AARCH64_negate_ra_state
is multiplexed on top of DW_CFA_GNU_window_save, as per
https://gcc.gnu.org/ml/gcc-patches/2017-08/msg00753.html
I
On 12/3/19 1:45 PM, Wilco Dijkstra wrote:
Hi,
Part 2, split off from
https://gcc.gnu.org/ml/gcc-patches/2019-11/msg00399.html
To enable cores to use the correct max_cond_insns setting, use the
core-specific
tuning when a CPU/tune is selected unless -mrestrict-it is explicitly set.
On
On 12/2/19 12:14 PM, Wilco Dijkstra wrote:
Add support for Cortex-A76, Ares and Neoverse N1 cpu names in GCC8 branch.
2019-11-29 Wilco Dijkstra
* config/aarch64/aarch64-cores.def (ares): Define.
(cortex-a76): Likewise.
(neoverse-n1): Likewise.
*
Hi Wilco,
On 11/19/19 3:11 PM, Wilco Dijkstra wrote:
ping
Various CPUs have max_cond_insns set to 5 due to historical reasons.
Benchmarking shows that max_cond_insns=2 is fastest on modern Cortex-A
cores, so change it to 2 for all Cortex-A cores.
Hmm, I'm not too confident on that. I'd
Hi Srinath,
On 11/21/19 4:32 PM, Srinath Parvathaneni wrote:
Hello,
This patch fixes arm acle testcase crc_hf_1.c by modifying the
compiler options directive.
Regression tested on arm-none-eabi and found no regressions.
Ok for trunk? If ok, please commit on my behalf, I don't have the
On 11/19/19 1:41 PM, Dennis Zhang wrote:
Hi Kyrill,
On 19/11/2019 11:21, Kyrill Tkachov wrote:
Hi Dennis,
On 11/12/19 5:32 PM, Dennis Zhang wrote:
Hi Kyrill,
On 12/11/2019 15:57, Kyrill Tkachov wrote:
On 11/12/19 3:50 PM, Dennis Zhang wrote:
Hi Kyrill,
On 12/11/2019 09:40, Kyrill
Hi Dennis,
On 11/12/19 5:32 PM, Dennis Zhang wrote:
Hi Kyrill,
On 12/11/2019 15:57, Kyrill Tkachov wrote:
On 11/12/19 3:50 PM, Dennis Zhang wrote:
Hi Kyrill,
On 12/11/2019 09:40, Kyrill Tkachov wrote:
Hi Dennis,
On 11/7/19 1:48 PM, Dennis Zhang wrote:
Hi Kyrill,
I have rebased the patch
On 11/18/19 12:54 PM, Tamar Christina wrote:
OK to backport to GCC 9?
Yes.
Thanks,
Kyrill
Thanks,
Tamar
-Original Message-
From: gcc-patches-ow...@gcc.gnu.org
On Behalf Of Kyrill Tkachov
Sent: Tuesday, September 24, 2019 14:32
To: Stam Markianos-Wright ; gcc-
patc
Hi Prathamesh,
On 11/14/19 6:47 PM, Prathamesh Kulkarni wrote:
Hi,
As suggested in PR, the attached patch falls back to distributing
rshift over plus_expr instead of fallback widening -> arithmetic ->
narrowing sequence, if target support is not available.
Bootstrap+tested on
Hi Richard,
On 11/14/19 10:07 AM, Richard Henderson wrote:
I've put the implementation into config/arm/aarch-common.c, so
that it can be shared between the two targets. This required
a little bit of cleanup to the CC modes and constraints to get
the two targets to match up.
Changes for v2:
On 11/14/19 10:07 AM, Richard Henderson wrote:
The existing definition using register class CC_REG does not
work because CC_REGNUM does not support normal modes, and so
fails to match register_operand. Use a non-register constraint
and the cc_register predicate instead.
*
On 11/12/19 3:50 PM, Dennis Zhang wrote:
Hi Kyrill,
On 12/11/2019 09:40, Kyrill Tkachov wrote:
Hi Dennis,
On 11/7/19 1:48 PM, Dennis Zhang wrote:
Hi Kyrill,
I have rebased the patch on top of current truck.
For resolve_overloaded, I redefined my memtag overloading function to
fit
Hi Christophe,
On 11/12/19 10:29 AM, Christophe Lyon wrote:
On Thu, 7 Nov 2019 at 11:26, Kyrill Tkachov wrote:
Hi all,
This patch adds the plumbing for and an implementation of the saturation
intrinsics from ACLE [1], in particular the __ssat, __usat intrinsics.
These intrinsics set the Q
Hi Christophe,
On 10/18/19 2:18 PM, Christophe Lyon wrote:
Hi,
This patch extends support for -mpure-code to all thumb-1 processors,
by removing the need for MOVT.
Symbol addresses are built using upper8_15, upper0_7, lower8_15 and
lower0_7 relocations, and constants are built using sequences
On 10/23/19 10:26 AM, Mihail Ionescu wrote:
[PATCH, GCC/ARM, 10/10] Enable -mcmse
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline Security Extensions architecture. Its purpose is to enable the
-mcmse option now that support for Armv8.1-M
On 10/23/19 10:26 AM, Mihail Ionescu wrote:
[PATCH, GCC/ARM, 9/10] Call nscall function with blxns
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline Security Extensions architecture. Its purpose is to call
functions with the cmse_nonsecure_call
Hi Mihail,
On 10/23/19 3:24 PM, Mihail Ionescu wrote:
[PATCH, GCC/ARM, 8/10] Do lazy store & load inline when calling nscall
function
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline Security Extensions architecture. Its purpose is to generate
On 10/23/19 10:26 AM, Mihail Ionescu wrote:
[PATCH, GCC/ARM, 7/10] Clear all VFP regs inline in hardfloat nscall
functions
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline Security Extensions architecture. Its purpose is to generate
inline
Hi Mihail,
On 10/23/19 10:26 AM, Mihail Ionescu wrote:
[PATCH, GCC/ARM, 6/10] Clear GPRs inline when calling nscall function
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline Security Extensions architecture. Its purpose is to generate
inline
Hi Mihail,
On 10/23/19 10:26 AM, Mihail Ionescu wrote:
[PATCH, GCC/ARM, 5/10] Clear VFP registers with VSCCLRM
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline Security Extensions architecture. Its purpose is to improve
code density of functions
Hi Mihail,
On 10/23/19 10:26 AM, Mihail Ionescu wrote:
[PATCH, GCC/ARM, 4/10] Clear GPR with CLRM
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline Security Extensions architecture. Its purpose is to improve
code density of functions with the
11/2019 16:40, Kyrill Tkachov wrote:
Hi Dennis,
On 10/17/19 11:03 AM, Dennis Zhang wrote:
Hi,
Arm Memory Tagging Extension (MTE) is published with Armv8.5-A.
It can be used for spatial and temporal memory safety detection and
lightweight lock and key system.
This patch enables new intrinsics
Hi Richard,
On 11/9/19 12:44 PM, Richard Henderson wrote:
On 11/7/19 11:26 AM, Kyrill Tkachov wrote:
-;; The code sequence emitted by this insn pattern uses the Q flag, which GCC
-;; doesn't generally know about, so we don't bother expanding to individual
-;; instructions. It may be better
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