On 29 May 2012 17:31, Richard Guenther richard.guent...@gmail.com wrote:
On Tue, May 29, 2012 at 1:57 PM, Mohamed Shafi shafi...@gmail.com wrote:
Hi,
I am porting a private target in GCC 4.6.3 version. For my target
pointer size is 24bits and word size is 32bits. Moreover a byte is
32bit
Hi,
I am porting a private target in GCC 4.6.3 version. For my target
pointer size is 24bits and word size is 32bits. Moreover a byte is
32bit
For the testcase gcc.c-torture/compile/92-1.c i get the following ICE
92-1.c: In function 'f':
92-1.c:18:5: internal compiler error: in
ping !!!. Any help on http://gcc.gnu.org/ml/gcc/2011-09/msg00150.html
shafi
On 14 September 2011 15:07, Mohamed Shafi shafi...@gmail.com wrote:
Hi,
I am working on a 32bit private target which has the following restriction
1. store/load can happen only through a general purpose register
Hi,
For the target that i am porting needs a cpu command line option i.e
it doesn't have a default option. Currently it takes 3 variant, say
cpu1, cpu2, cpu3.
So when i enable multilib option
MULTILIB_OPTIONS = mcpu=1/mcpu=2/mcpu=3
I get the following libgcc variants:
cpu1/libgcc
cpu2/libgcc
Hi,
I am working on a 32bit private target which has the following restriction
1. store/load can happen only through a general purpose register (GP_REGS)
2. base register should be an address register (AD_REGS)
3. moves between GP_REGS and AD_REGS can happen only through PT_REGS
In a PRE_MODIFY
Hi,
I am doing a private port in GCC 4.5.1. For the my target i see some
strange behavior in delay slot scheduling. For my target the
instruction in the delay slots gets executed irrespective of whether
the branch is taken or not. I have generated the following code after
commenting out the call
On 6 September 2011 20:50, Jeff Law l...@redhat.com wrote:
On 09/06/11 08:46, Mohamed Shafi wrote:
Hi,
I am doing a private port in GCC 4.5.1. For the my target i see some
strange behavior in delay slot scheduling. For my target the
instruction in the delay slots gets executed irrespective
Hi all,
I am trying to add support for hardware loops for a 32bit target. In
the target QImode is 32bit. The loop counter used in hardware loop
construct is 17bit address registers. This is represented using
PQImode. Since mode for the doloop pattern is found out after loop
discovery it need not
Hello all,
I am porting GCC 4.5.1 for a private target. For one particular test
reloading pass is being asked to reload the following instruction:
(insn 45 175 46 11 pr20601-1.c:90 (set (reg/f:PQI 3 g3 [70])
(mem/f:PQI (pre_inc:PQI (reg/f:PQI 1 g1 [orig:55 prephitmp.16
] [55])) [2 S1
On 11 February 2011 15:28, Paulo J. Matos pocma...@gmail.com wrote:
On 11/02/11 09:46, Mohamed Shafi wrote:
How can i overcome this failure? Can some one suggest a solution?
Have you defined TARGET_LEGITIMATE_ADDRESS_P and also BASE_REG_CLASS
correctly for your target?
Yes, I have
On 10 February 2011 15:57, Richard Guenther richard.guent...@gmail.com wrote:
On Thu, Feb 10, 2011 at 6:23 AM, Mohamed Shafi shafi...@gmail.com wrote:
Hi all,
I am trying to port a private target in GCC 4.5.1. Following are the
properties of the target
#define BITS_PER_UNIT 32
On 10 February 2011 17:16, Richard Guenther richard.guent...@gmail.com wrote:
On Thu, Feb 10, 2011 at 12:42 PM, Mohamed Shafi shafi...@gmail.com wrote:
On 10 February 2011 15:57, Richard Guenther richard.guent...@gmail.com
wrote:
On Thu, Feb 10, 2011 at 6:23 AM, Mohamed Shafi shafi
Hi all,
I am trying to port a private target in GCC 4.5.1. Following are the
properties of the target
#define BITS_PER_UNIT 32
#define BITS_PER_WORD32
#define UNITS_PER_WORD 1
#define CHAR_TYPE_SIZE32
#define SHORT_TYPE_SIZE 32
#define INT_TYPE_SIZE
On 20 December 2010 10:56, Jeff Law l...@redhat.com wrote:
On 12/15/10 07:14, Mohamed Shafi wrote:
Hi,
I am doing a port in GCC 4.5.1.
The target supports storing immediate values into memory location
represented by a symbolic address. So in the move pattern i have given
constraints
On 20 December 2010 19:30, Jeff Law l...@redhat.com wrote:
On 12/20/10 01:47, Mohamed Shafi wrote:
I think this is a case where you're going to need a secondary reload to
force the immediate into a register if the destination is a non-symbolic
MEM
or a pseudo without a hard reg and its
Hi,
I am doing a port in GCC 4.5.1.
The target supports storing immediate values into memory location
represented by a symbolic address. So in the move pattern i have given
constraints to represent this.
(define_insn movqi_op
[(set (match_operand:QI 0 nonimmediate_operand
On 30 October 2010 05:45, Joern Rennecke joern.renne...@embecosm.com wrote:
Quoting Mohamed Shafi shafi...@gmail.com:
On 29 October 2010 00:06, Joern Rennecke joern.renne...@embecosm.com
wrote:
Quoting Mohamed Shafi shafi...@gmail.com:
Hi,
I am doing a port in GCC 4.5.1. For the port
1
Hi,
For a private target that i am porting in GCC 4.5 I have the following
pattern in my md file for call value:
(define_insn call_value_op
[(set (match_operand 0 register_operand =da)
(call (mem:QI (match_operand:QI 1 call_operand Wd))
(match_operand:QI 2 )))]
On 12 November 2010 18:39, Joern Rennecke amyl...@spamcop.net wrote:
Quoting Mohamed Shafi shafi...@gmail.com:
So i have the following questions:
1. Why is that constraints are not matched here?
Please read the node Register Classes in doc/tm.texi .
I am sorry , could you please highlight
Hi all,
I need a opinion on a design front. I am doing a port for a private
target in GCC 4.5.1. We are also in the process of designing the
hardware along with the development of the build tools. Currently we
don't have enough bits in the encoding to support conditional
instruction like arm
On 30 October 2010 05:45, Joern Rennecke joern.renne...@embecosm.com wrote:
Quoting Mohamed Shafi shafi...@gmail.com:
On 29 October 2010 00:06, Joern Rennecke joern.renne...@embecosm.com
wrote:
Quoting Mohamed Shafi shafi...@gmail.com:
Hi,
I am doing a port in GCC 4.5.1. For the port
1
Hi,
I am doing a port in GCC 4.5.1. For the port
1. there is only (reg + offset) addressing mode only when reg is SP.
Other base registers are not allowed
2. FP cannot be used as a base register. (FP based addressing is done
by copying it into a base register)
In order to take advantage of FP
On 29 October 2010 00:06, Joern Rennecke joern.renne...@embecosm.com wrote:
Quoting Mohamed Shafi shafi...@gmail.com:
Hi,
I am doing a port in GCC 4.5.1. For the port
1. there is only (reg + offset) addressing mode only when reg is SP.
Other base registers are not allowed
2. FP cannot
Hello all,
I am trying to do a port on GCC 4.5. The target has a memory
resolution of 32bits i.e. char is 32bits in the target (addr 0 selects
1st 32bit and addr 1 selects 2nd 32bit). It has only word (32bit)
access.
In terms of address resolution this target is similar to c4x which
became
Hello all,
I am trying to port GCC 4.5.1 for a processor that has the following
addressing capability:
The data memory address space of 64K bytes is represented by a total
of 15 bits, with each address selecting a 16-bit element. When using
the address register, the LSB of address reg (AD)
Hi,
I am doing a port for a 32bit target in GCC 4.4.0. I need a way to
identify that a register is part of a multiword register. I need to
emit an instruction that works on LSW of the double word register on
move instructions. Currently the target splits the DImode and DFmode
moves after
Hello all,
I am doing a port for a 32bit a target in GCC 4.4.0. The target
supports (base + offset) addressing mode for QImode store instructions
but not for QImode load instructions. GCC doesn't take the middle
path. It either supports an addressing mode completely and doesn't
support at all. I
2009/12/22 Richard Earnshaw rearn...@arm.com:
On Mon, 2009-12-21 at 18:44 +, Paul Brook wrote:
I am doing a port in GCC 4.4.0 for a 32 bit target. As a part of
scheduling framework i have to write the move patterns with more
clarity, so that i could control the scheduling with
Hi all,
I am doing a port in GCC 4.4.0 for a 32 bit target. As a part of
scheduling framework i have to write the move patterns with more
clarity, so that i could control the scheduling with the help of
attributes. Re-writting the pattern resulted in movsi pattern with 41
alternatives :( When i
2009/12/18 Hans-Peter Nilsson h...@bitrange.com:
On Fri, 20 Nov 2009, Mohamed Shafi wrote:
I tried implementing the suggestion given by Richard, but got into
issues. The GCC frame work is written assuming that there are no modes
with HOST_BITS_PER_WIDE_INT GET_MODE_BITSIZE (mode) 2
Hello all,
I am porting GCC 4.4.0 for a 32bit target. The target has 40bit data
registers and 32bit address register. Both can be used as general
purpose registers. All load and store operations are 32bit. If 40bit
data register is involved in load/sore the register gets sign
extended. Whenever
2009/11/10 Richard Henderson r...@redhat.com:
On 11/10/2009 05:48 AM, Mohamed Shafi wrote:
(define_insn mulsi3
[(set (match_operand:SI 0 register_operand =d)
(mult:SI (match_operand:SI 1 register_operand %d)
(match_operand:SI 2 register_operand d)))]
Note
Hello all,
I am doing a port for a 32bit target in GCC 4.4.0. In my target 32bit
multiply instruction is carried out in two instructions.
Dn = Da x Db is executed as
Dn = (Da.L * Db.H + Da.H * Db.L) 16
Dn = Dn + (Da.L * Db.L)
Currently the pattern that i have for this is as follows:
2009/11/6 Richard Henderson r...@redhat.com:
On 11/06/2009 05:29 AM, Mohamed Shafi wrote:
The target that i am working on has 1 2 bit shift-add patterns.
GCC is not generating shift-add patterns when the shift count is 1. It
is currently generating add operations. What should be done
2009/11/6 Ian Lance Taylor i...@google.com:
Mohamed Shafi shafi...@gmail.com writes:
It is generating with data registers. Here is the pattern that i have
written:
(define_insn *saddl
[(set (match_operand:SI 0 register_operand =r,d)
(plus:SI (mult:SI (match_operand:SI 1
2009/10/22 Richard Henderson r...@redhat.com:
On 10/21/2009 07:25 AM, Mohamed Shafi wrote:
For accessing a-b GCC generates the following code:
move.l (sp-16), d3
lsrr.l #16, d3
move.l (sp-12),d2
asll #16,d2
or d3,d2
cmpeq.w #2,d2
2009/10/22 Richard Henderson r...@redhat.com:
On 10/21/2009 07:25 AM, Mohamed Shafi wrote:
For accessing a-b GCC generates the following code:
move.l (sp-16), d3
lsrr.l #16, d3
move.l (sp-12),d2
asll #16,d2
or d3,d2
cmpeq.w #2,d2
2009/10/30 Jeff Law l...@redhat.com:
On 10/30/09 07:13, Mohamed Shafi wrote:
Hi,
I am doing a port for a 32bit target in GCC 4.4.0. The target does not
have support for symbolic address in QImode for load operations.
You'll need to make sure to reject such addresses for QImode
2009/10/30 Ian Lance Taylor i...@google.com:
Mohamed Shafi shafi...@gmail.com writes:
From ice4.c.168r.asmcons
(insn 5 2 6 2 ice4.c:4 (set (reg:SI 61 [ s ])
(mem/c/i:SI (symbol_ref:SI (s) [flags 0x2] var_decl
0xb7bfd000 s) [0 s+0 S4 A32])) 2 {*movsi_internal} (nil))
(insn 6 5 7 2
Hi,
I am doing a port for a 32bit target in GCC 4.4.0. The target does not
have support for symbolic address in QImode for load operations. In
order to do this what i have done is in define_expand for moveqi
reject symbolic address it they come in source operands and i have
also written a
Hi,
The internal doc says :
— Target Hook: bool TARGET_CAN_INLINE_P (tree caller, tree callee)
This target hook returns false if the caller function cannot
inline callee, based on target specific information. By default,
inlining is not allowed if the callee function has function specific
2009/9/14 Richard Henderson r...@redhat.com:
Another thing to look at, since you have hand-written routines and may be
able to specify that e.g. only a subset of the normal call clobbered
registers are actually modified, is to leave the call as a compare insn.
Something like
(define_insn
HI all,
I am porting GCC 4.4.0 for a 32bit target. The target has 40bit data
registers and 32bit address registers that can be used as general
purpose registers. When 40bit registers are used for arithmetic
operations or comparison operations GCC generates code assuming that
its a 32bit register.
2009/9/14 Richard Henderson r...@redhat.com:
On 09/14/2009 07:24 AM, Mohamed Shafi wrote:
Hello all,
I am doing a port for a 32bit target in GCC 4.4.0. I have to support a
40bit data (_Accum) in the port. The target has 40bit registers which
is a GPR and works as 32bit reg in other modes
2009/9/30 Richard Henderson r...@redhat.com:
On 09/29/2009 09:46 PM, Mohamed Shafi wrote:
bool strict = reload_completed ? true : false;
What happens if you set strict = false here?
That's what ARM does.
That particular case works, and yes arm does it that way but there
are other
2009/9/28 Richard Henderson r...@redhat.com:
On 09/28/2009 07:25 AM, Mohamed Shafi wrote:
Hope someone suggests me a solution.
The solution is almost certainly something involving the
TARGET_SECONDARY_RELOAD hook. You need to inform reload that it's going to
need some scratch registers
Hello all,
I am doing a port for a 32bit target in GCC 4.4.0.
I have defined memory_constraints in predicates.c like this
(define_memory_constraint Sr0
Memory refrence through base registers
(match_test target_mem_constraint (\r0\, op)))
In the function target_mem_constraint i have
int
Hello all,
I doing a port for a 32bit target for GCC 4.4.0. I am getting the
following error:
rd_er.c:19: error: insn does not satisfy its constraints:
(insn 5 35 34 2 rd_er.c:8 (set (reg:SI 16 r0)
(plus:SI (reg:SI 16 r0)
(reg:SI 2 d2))) 57 {addsi3} (expr_list:REG_EQUAL
I am doing a port for a 32bit target in GCC 4.4.0
I am getting segmentation fault in the function assign_temp in the
following line:
if (DECL_P (type_or_decl))
After analyzing the issue i find that this might be a bug. I just want
to confirm if that is the case or not.
In order to reproduce i
Hello all,
I am porting a 32bit target in GCC 4.4.0
The target has have distinct signed and unsigned compare instructions,
and only one set of conditional branch instructions. Moreover the
operands cannot be immediate values if the comparison is unsigned. I
have implemented this using
Hi all,
I am doing a GCC port for a 32bit target in GCC 4.4.0. The target uses
hand coded floating point compare routines. Generally the function
returns the values in the general purpose registers. But these fp cmp
routines return the result in the Status Register itself. So there is
no need to
Hello all,
I am doing a port for a 32bit target in GCC 4.4.0. I have to support a
40bit data (_Accum) in the port. The target has 40bit registers which
is a GPR and works as 32bit reg in other modes. The load and store for
_Accum happens in two step. The lower 32bit in one instruction and the
Hello all,
I am doing a port for a 32bit target in GCC 4.4.0. Of the addressing
modes that are allowed by my target the one with (base register +
offset) is restrictive in QImode. The restriction is that if the base
register is not Stack Pointer then this kind of address cannot come in
a load
Hello all,
I am trying to port a 32bit arch in GCC 4.4.0. My target has support
for 1bit, 2bit shift and add operations. I tried to write patterns for
this , but gcc is not generating those. The following are the patterns
that i have written in md file:
(define_insn shift_add_mode
[(set
2009/7/16 Richard Henderson r...@redhat.com:
On 07/13/2009 07:35 AM, Mohamed Shafi wrote:
So i made both TARGET_STRICT_ARGUMENT_NAMING and
PRETEND_OUTGOING_VARARGS_NAMED to return false. Is this correct?
Yes.
How to make the varargs argument to be promoted to 32bits when the
normal
HI,
I am trying to port a 32bit target in GCC 4.4.0. My target supports
big and little endian. This is selected using a target switch. So i
have defined the macro
#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
Currently i have written pattens only for SImode moves. So GCC will
synthesize DImode
2009/7/3 Ian Lance Taylor i...@google.com:
Mohamed Shafi shafi...@gmail.com writes:
I just want to know about the feasibility of implementing an
instruction for a port in gcc 4.4
The target has 40 bit register where the normal load/store/move
instructions will be able to access the 32 bits
Hello all,
I am trying to port a 32bit target in GCC 4.4.0
Of the addressing modes that are allowed by my target the one with
(base register + offset) is restrictive in QImode.
The restriction is that if the base register is not Stack Pointer then
this kind of address cannot come in a load
2009/8/5 Jim Wilson wil...@codesourcery.com:
On Tue, 2009-08-04 at 11:09 +0530, Mohamed Shafi wrote:
i am not able to implement the alignment for short.
The following is are the macros that i used for this
#define PARM_BOUNDARY 8
#define STACK_BOUNDARY 64
The target is 32bit . The first
2009/8/3 Jim Wilson wil...@codesourcery.com:
On 08/03/2009 02:14 AM, Mohamed Shafi wrote:
short - 2 bytes
i am not able to implement the alignment for short.
The following is are the macros that i used for this
#define PARM_BOUNDARY 8
#define STACK_BOUNDARY 64
You haven't explained what
2009/8/1 Dave Korn dave.korn.cyg...@googlemail.com:
Mohamed Shafi wrote:
I am looking for adding something to the end of each section in the
generated .s file. Using TARGET_ASM_NAMED_SECTION i will be able to
keep track of the sections that are being emitted. But from
TARGET_ASM_FILE_END hook
2009/8/1 Dave Korn dave.korn.cyg...@googlemail.com:
Mohamed Shafi wrote:
2009/8/1 Dave Korn dave.korn.cyg...@googlemail.com:
Mohamed Shafi wrote:
I am looking for adding something to the end of each section in the
generated .s file. Using TARGET_ASM_NAMED_SECTION i will be able to
keep track
2009/7/18 Dave Korn dave.korn.cyg...@googlemail.com:
Mohamed Shafi wrote:
Hello all,
Is it possible to emit a assembler directive at the end of each sections?
Say like section_end
Is there any support for doing something like this in the back-end files?
Or should i need to the make changes
2009/7/18 Ian Lance Taylor i...@google.com:
Mohamed Shafi shafi...@gmail.com writes:
The change logs says that current_function_outgoing_args_size is no
more available. But it doesnt say with what it is replaced. Looking at
the other targets i find that its replaced with some field
Hello all,
Is it possible to emit a assembler directive at the end of each sections?
Say like section_end
Is there any support for doing something like this in the back-end files?
Or should i need to the make changes in the gcc sources?
Is so do does anyone know in which function it should
Hello all,
The change logs says that current_function_outgoing_args_size is no
more available. But it doesnt say with what it is replaced. Looking at
the other targets i find that its replaced with some field in a
structure crtl. Where is this defined/declared.
I am working in GCC 4.4.0. I
Hello all,
I am doing a port for a private target in GCC 4.4.0. It generates code
for both little big endian.
The ABI for the target is as follows:
1. All arguments passed in stack are passed using their alignment constrains.
Solution: For this to happen no argument promotion should be done.
Hello all,
The GCC 4.4.0 internal says :
[Macro] CALL_REALLY_USED_REGISTERS
Like CALL_USED_REGISTERS except this macro doesn’t require that the
entire set of
FIXED_REGISTERS be included. (CALL_USED_REGISTERS must be a superset of FIXED_
REGISTERS). This macro is optional. If not specifed, it
Hello all,
I just want to know about the feasibility of implementing an
instruction for a port in gcc 4.4
The target has 40 bit register where the normal load/store/move
instructions will be able to access the 32 bits of the register. In
order to move data into the rest of the register [b32 to
Hi all,
Does GCC support architectures that has Variable Length Execution Set (VLES)?
Are there any developments happening in this direction?
Regards,
Shafi
2009/5/27 Ian Lance Taylor i...@google.com:
Mohamed Shafi shafi...@gmail.com writes:
Does GCC support architectures that has Variable Length Execution Set (VLES)?
Are there any developments happening in this direction?
gcc supports many instruction sets whose instructions are not all
- Original Message
From: Omar Torres [EMAIL PROTECTED]
To: [EMAIL PROTECTED]
Cc: gcc@gcc.gnu.org
Sent: Saturday, August 30, 2008 12:11:36 AM
Subject: Re: insn does not satisfy its constraints
shafi wrote:
Operand 0 is a register
Operand 1 is a memory
Operand 2
Hello all,
I am involved in the porting of GCC 4.1.2 for a 16 bit target. The
target doenst have any SImode comparisons. Most of the time SImode
comparisons are synthesized using HImode comparisons. But some in some
instances SImode patterns are generated like that, where the code is
expanded in
Hello all,
For the target that i am porting if support for partial argument
passing is enabled i get the following error:
error: Attempt to delete prologue/epilogue insn:
internal compiler error: in propagate_one_insn, at flow.c:1699
This is 16bit target with 4 argument registers.
Hello all,
I am involved in porting gcc 4.1.2.
For some processing i need to know whether a register is being defined
and used in a particular instruction. Till now i have been using
'refers_to_regno_p()' to know whether a register is being used in a
instruction and 'modified_in_p()' to know
Hello all,
I am involved in the porting of gcc 4.1.2 for 16 bit target. For this
target size of long long is 32bits. For the following code
#define VALUE 0x1B4E81B4E81B4DLL
#define AFTER 0x55
//void test (int n, long long q, int y);
void test (int n, ...);
int
main ()
{
test (1, VALUE,
2008/7/16 Ian Lance Taylor [EMAIL PROTECTED]:
Mohamed Shafi [EMAIL PROTECTED] writes:
I am involved in the porting of gcc 4.1.2 for 16 bit target. For this
target size of long long is 32bits. For the following code
#define VALUE 0x1B4E81B4E81B4DLL
That is not a 32-bit value.
#define
Hello all,
I am not sure if this the right mailing list.
I am involved in the porting of gcc 4.1.2 for a 16 bit target.
In some cases i noticed that callee save registers were getting
allocated in the body even though there isn't any function call. I
believe that callee save registers will be
and callee saved registers. So out of the 16
available registers ony 5+1+4 registers were used, even though there
was 6 caller save registers were available
HTH.
cheers
Ramana
On Tue, Jul 15, 2008 at 7:50 AM, Mohamed Shafi [EMAIL PROTECTED] wrote:
Hello all,
I am not sure if this the right
save registers.
cheers
Ramana
HTH.
cheers
Ramana
On Tue, Jul 15, 2008 at 7:50 AM, Mohamed Shafi [EMAIL PROTECTED] wrote:
Hello all,
I am not sure if this the right mailing list.
I am involved in the porting of gcc 4.1.2 for a 16 bit target.
In some cases i noticed that callee
Hello all,
Is there a way to know whether an operand is signed or unsigned from its rtx?
Regards,
Shafi
Hello all,
I am involved in porting a 16bit target in gcc 4.1.2
The target that i am porting to has a minor flaw. Comparison of signed
variables will go wrong. So i have to use a different approach to do
comparison of signed operands. This obviously takes more cycles and
instructions. But the
Hello all,
For the 16-bit target that i porting now to gcc 4.1.2 doesn't have any
branch instructions. It only has jump instructions. For comparison
operation it has this instruction:
if cond Rx Ry
execute this insn
So compare and branch is implemented as
if cond Rx Ry
jmp Label
If the
Hello everyone,
I am involved in gcc port in which i found the following problem.
Before register renaming pass, callee registers was being used in the
body of the code. Hence function prologue saved the register and
epilogue restored the register. But register renaming pass removed
this
2008/6/19 Ian Lance Taylor [EMAIL PROTECTED]:
Mohamed Shafi [EMAIL PROTECTED] writes:
Before register renaming pass, callee registers was being used in the
body of the code. Hence function prologue saved the register and
epilogue restored the register. But register renaming pass removed
2008/6/19 Ian Lance Taylor [EMAIL PROTECTED]:
Mohamed Shafi [EMAIL PROTECTED] writes:
Which version of gcc? I was under the impression that this
longstanding buglet was cleaned up by the dataflow work.
I am doing a port in gcc 4.1.2. The register is actually replaced
by register copy
2008/6/20 Andrew Pinski [EMAIL PROTECTED]:
On Thu, Jun 19, 2008 at 11:56 PM, Mohamed Shafi [EMAIL PROTECTED] wrote:
Can you tell me what was done in gcc 4.3 so that i can back port
the changes to gcc 4.1.2
It was a rewrite of life information of flow.c really. It is very
hard to backport
Hello all,
The 16bit target that i am porting to gcc4.1.2 doesn't have any
instructions for 32bit operations. But for addition and subtraction
there is
addc
subc
instructions that consider carry bit also. Presently i have patterns
for SImode addition and subtraction such that the template will
Hello all,
For the big endian 16bit target that i am porting to gcc 4.1.2 a nop
is needed after a load instruction if the destination register of the
load instruction is used as the source in the next instruction. So
load R0, R3[2]
add R2, R0
needs a nop inserted in between the instructions. I
Hello all,
The target that i am working on is 16bit, big endian and with 16 registers.
It has this particular addressing mode
load Rd, Ra[offset]
store Rs, Ra[offset]
where the offset should be positive, base register Ra should be an
even register and for the source or the destination register
Hello everyone,
I need to specify constraints for registers used in the memory
operands in a load pattern. For these the following are the things
that i have done.
#define CONSTRAINT_LEN(CHAR,STR) \
((CHAR) == 'R' ? 3 \
: DEFAULT_CONSTRAINT_LEN(CHAR,STR))
#define
On Sat, May 24, 2008 at 12:26 AM, Omar Torres [EMAIL PROTECTED] wrote:
Mohamed Shafi wrote:
Hello Omar,
I saw your mail to gcc mailing list regarding splitting of HImode
patterns into QImode patterns. I am also involved in porting. My
problem is similar to yours. But i have to split SImode
On Tue, May 20, 2008 at 1:54 PM, [EMAIL PROTECTED] wrote:
Dear Shafi
Thanks you very much for the clear details. Definitely your inputs are
helpful.
1) I am sure that in gcc-4.0 I found there is file gmon.c in the path
gcc-4.0.0/gcc/gmon.c. Anyhow let me concentrate on gmon.c of glibc.
On Wed, May 21, 2008 at 1:42 AM, Jeff Law [EMAIL PROTECTED] wrote:
Ian Lance Taylor wrote:
Mohamed Shafi [EMAIL PROTECTED] writes:
For the 16 bit target that i am currently porting can have only
positive offsets less than 0x100. (unsigned 8 bit) for offset
addressing mode.
I would expect
Hello all,
For the 16 bit target that i am currently porting can have only
positive offsets less than 0x100. (unsigned 8 bit) for offset
addressing mode.
During reload i am getting ICE because the address created is not
legitimate. So i guess i have to define the macro
LEGITIMIZE_RELOAD_ADDRESS.
2008/5/19 [EMAIL PROTECTED]:
Hi,
I am Raja, I need a favor on understand how the gmon.out file is created.
Please help me.
1. gmon.c is available in both gcc and glibc. Which is the one used to
create gmon.out ?
I don't think gcc has gmon.c. Only glibc has it. You can also find
gmon in
Hello all,
Recently i noticed that register allocation for the operands in a
unspec pattern was going wrong.
This was because there was no conflict between the registers used in
the unspec pattern and the other registers which should have been
there.
During debugging i found out that the code is
On Tue, Apr 1, 2008 at 2:10 AM, Jim Wilson [EMAIL PROTECTED] wrote:
Mohamed Shafi wrote:
For the source or the destination register Rd/Ra, the restriction is
that it should be one more than the base register . So the following
instructions are valid:
GCC doesn't provide any easy way
On Fri, May 16, 2008 at 11:39 PM, Eric Botcazou [EMAIL PROTECTED] wrote:
(insn 211 210 215 1 (set (reg:HI 1 R1 [+2 ])
(subreg:HI (reg/v:SF 207 [ d.104 ]) 2)) 4 {movhi_regmove}
(insn_list:REG_DEP_TRUE 208 (nil))
(nil))
(call_insn/u 215 211 217 1 (set (reg:HI 0 R0)
Hello all,
In the gcc 4.1.2 port i am working on, i get an ICE in insert_save, at
caller-save.c:725
And following is the assert that assert failure.
/* A common failure mode if register status is not correct in the
RTL is for this routine to be called with a REGNO we didn't
expect to
1 - 100 of 176 matches
Mail list logo
