On Mon, 03 Jun 2024 11:50:54 PDT (-0700), jeffreya...@gmail.com wrote:
On 6/3/24 11:03 AM, Palmer Dabbelt wrote:
+;; Provide a minmax pattern for ifcvt to match.
+(define_insn "*_cmp_3"
+ [(set (match_operand:X 0 "register_operand" "
erand:X 2 "reg_or_0_operand" "rJ")))]
"TARGET_ZBB"
"\t%0,%1,%z2"
[(set_attr "type" "")])
but it looks like it ends up with the same types after all the iterators
(there's some "max vs smax" and "smax vs maxs&quo
On Fri, 24 May 2024 16:50:52 PDT (-0700), jeffreya...@gmail.com wrote:
On 5/24/24 5:43 PM, Palmer Dabbelt wrote:
I'm only reading Zicclsm as saying both scalar and vector misaligned
accesses are supported, but nothing about the performance.
I think it was in the vector docs. It didn't say
On Fri, 24 May 2024 16:41:39 PDT (-0700), jeffreya...@gmail.com wrote:
On 5/24/24 5:39 PM, Palmer Dabbelt wrote:
On Fri, 24 May 2024 16:31:48 PDT (-0700), jeffreya...@gmail.com wrote:
On 5/24/24 11:14 AM, Palmer Dabbelt wrote:
On Fri, 24 May 2024 09:19:09 PDT (-0700), Robin Dapp wrote
On Fri, 24 May 2024 16:31:48 PDT (-0700), jeffreya...@gmail.com wrote:
On 5/24/24 11:14 AM, Palmer Dabbelt wrote:
On Fri, 24 May 2024 09:19:09 PDT (-0700), Robin Dapp wrote:
We should have something in doc/invoke too, this one is going to be
tricky for users. We'll also have to define how
On Fri, 24 May 2024 09:19:09 PDT (-0700), Robin Dapp wrote:
We should have something in doc/invoke too, this one is going to be
tricky for users. We'll also have to define how this interacts with
the existing -mstrict-align.
Addressed the rest in the attached v2 which also fixes tests.
I'm
On Fri, 24 May 2024 07:30:20 PDT (-0700), Robin Dapp wrote:
Hi,
this patch changes the default from always enabling movmisalign to
disabling it. It adds an option to override the default and adds
generic-ooo to the uarchs that support misaligned vector access.
It also adds a
On Wed, 22 May 2024 12:02:26 PDT (-0700), jeffreya...@gmail.com wrote:
On 5/22/24 12:15 PM, Palmer Dabbelt wrote:
On Wed, 22 May 2024 11:01:16 PDT (-0700), jeffreya...@gmail.com wrote:
On 5/22/24 6:47 AM, Jivan Hakobyan wrote:
After 8367c996e55b2 commit several checks on round_32.c test
On Wed, 22 May 2024 11:01:16 PDT (-0700), jeffreya...@gmail.com wrote:
On 5/22/24 6:47 AM, Jivan Hakobyan wrote:
After 8367c996e55b2 commit several checks on round_32.c test started to
fail.
The reason is that we prevent rounding DF->SI->DF on RV32 and instead of
a conversation sequence we
On Fri, 17 May 2024 15:37:43 PDT (-0700), juzhe.zh...@rivai.ai wrote:
I think it should be backport to GCC-14 since it is a bug.
Seems reasonable to me -- I guess in theory those extended scalar
patterns aren't bug fixes and we should split them out, but I don't
think it's all that big of a
On Fri, 17 May 2024 14:30:49 PDT (-0700), ger...@pfeifer.com wrote:
On Thu, 28 Apr 2022, Kito Cheng wrote:
---
htdocs/gcc-12/changes.html | 13 -
:
+New ISA extension support for vector and scalar crypto was added, only
+ support architecture testing marco and -march=
From: Jeff Law
As some of you know, Raphael has been working on stack-clash support for the
RISC-V port. A little while ago Florian reached out to us with an issue where
glibc was failing its smoke test due to referencing an unallocated stack slot.
Without diving into the code in detail I
Some processors from T-Head don't implement the `fence.tso` instruction
natively and instead trap to firmware. This breaks some users who
haven't yet updated the firmware and one could imagine it breaking users
who are trying to build firmware if they're using the C memory model.
So just add an
On Mon, 13 May 2024 16:08:21 PDT (-0700), Vineet Gupta wrote:
On 5/13/24 15:47, Jeff Law wrote:
On 5/13/24 11:49, Vineet Gupta wrote:
500.perlbench_r-0 | 1,214,534,029,025 | 1,212,887,959,387 |
500.perlbench_r-1 |740,383,419,739 | 739,280,308,163 |
500.perlbench_r-2 |
From: Yanzhang Wang
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_save_reg_p): Save ra for leaf
when enabling -mno-omit-leaf-frame-pointer
(riscv_option_override): Override omit-frame-pointer.
(riscv_frame_pointer_required): Save s0 for non-leaf function
On Tue, 07 May 2024 14:18:36 PDT (-0700), Jeff Law wrote:
> This is almost exclusively work from the VRULL team.
>
> As we've discussed in the Tuesday meeting in the past, we'd like to have
> a knob in the tuning structure to indicate that overlapped stores during
> move_by_pieces expansion of
widdling.
Either way, I think having the signed-NaN-preserving conversion is
reasonable as it's what users are going to expect (even if it's only
recommended by IEEE). So
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
in case you want to pick i
On Tue, 23 Apr 2024 07:45:03 PDT (-0700), Patrick O'Neill wrote:
Hi Pan,
Sorry about that. It looks like there was difference between my local
machine and CI machine.
From the CI it looks like we're back to the failure list we had on friday.
I'll do some local testing to manually confirm
On Mon, 22 Apr 2024 15:07:59 PDT (-0700), juzhe.zh...@rivai.ai wrote:
Apologize that we didn't post our (me, kito and Li Pan) disscussions.
Some amount of off-list discussion is inevitable, but as far as I can
tell here we ended up with some code committed that wasn't even posted
to the
t CSR are only valid when the specific ISA is set. The
read-only CSR can not be written by the CSR instructions.
This came up on IRC.
Acked-by: Palmer Dabbelt
Reviewed-by: Palmer Dabbelt
In case you want to merge it with the rest of thus, but I think it
should be something more like
Looks like we had a bunch of commits over the weekend that didn't get
tested/reviewed. Some didn't even make it to the lists so it's hard to
tell exactly what happened, but the result was a trunk that doesn't even
build and a bunch of ICEs after some trivial fix ups landed on the
lists.
So let's
On Mon, 22 Apr 2024 06:47:34 PDT (-0700), pan2...@intel.com wrote:
From: Pan Li
After we reverted below 2 commits, the reference to attr need some
adjustment as the group_overlap is no longer available.
* RISC-V: Robostify the W43, W86, W87 constraint enabled attribute
* RISC-V: Rename
On Fri, 12 Apr 2024 12:25:42 PDT (-0700), tschwi...@baylibre.com wrote:
Hi!
After having received around a dozen more buildbot notifications...
On 2024-04-10T06:46:04-0700, Palmer Dabbelt wrote:
On Tue, 09 Apr 2024 07:57:24 PDT (-0700), ishitatsuy...@gmail.com wrote:
Fixes: 97069657c4e
SiFive's P600 series (sifive-p600-series).
+ XiangShan's Nanhu microarchitecture
(xiangshan-nanhu).
+
+
+
Thanks for doing this. This all pretty minor wording stuff, so
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
Maybe next year we'll remember to ask submitters for these ;)
On Wed, 10 Apr 2024 00:57:59 PDT (-0700), sch...@suse.de wrote:
On Apr 09 2024, Palmer Dabbelt wrote:
I didn't actually regenerate this as I can't figure out how,
make regenerate-opt-urls
Ya, that's what the CI says too. I think I might just have a broken
build tree, something is mixed
e, but
I didn't actually run the regenerate script. So
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
On Tue, 09 Apr 2024 09:57:11 PDT (-0700), buga...@gmail.com wrote:
On Tue, Apr 9, 2024 at 7:24 PM Palmer Dabbelt wrote:
> I assume the buildbot failure that I just got an email about is
> unrelated; it's failing on some RISC-V thing.
Sorry if I missed something here, do you have a p
I didn't actually regenerate this as I can't figure out how, I've just
pasted in the diff from the sourceware buildbot (which is complaining
about post-regeneration diff).
Fixes: 97069657c4e ("RISC-V: Implement TLS Descriptors.")
gcc/ChangeLog:
* config/riscv/riscv.opt.urls:
On Tue, 09 Apr 2024 01:04:34 PDT (-0700), buga...@gmail.com wrote:
On Tue, Apr 9, 2024 at 10:27 AM Thomas Schwinge wrote:
Thanks, pushed to trunk branch:
- commit 532c57f8c3a15b109a46d3e2b14d60a5c40979d5 "Move GNU/Hurd startfile spec
from config/i386/gnu.h to config/gnu.h"
- commit
On Thu, 04 Apr 2024 07:37:56 PDT (-0700), ja...@redhat.com wrote:
On Thu, Apr 04, 2024 at 07:28:40AM -0700, Palmer Dabbelt wrote:
I'm not sure if we need release maintainer approval,
For cherry-picking one's own non-risky bugfixes for regression or
documentation bugs from trunk to release
_cum), arg);
/* Found out how many registers we need to save. */
Acked-by: Palmer Dabbelt
I'm not sure if we need release maintainer approval, all I can find is
the 13.2.1 status report saying 13.3 is expected in the spring
<https://inbox.sourceware.org/gcc/ZMJeq%2FY5SN+7i8a+@tucnak/>
On Tue, 02 Apr 2024 20:19:16 PDT (-0700), ji...@linux.alibaba.com wrote:
gcc/testsuite/ChangeLog:
* gcc.target/riscv/bf16_arithmetic.c: New test.
* gcc.target/riscv/bf16_call.c: New test.
* gcc.target/riscv/bf16_comparison.c: New test.
*
On Sun, 31 Mar 2024 09:53:46 PDT (-0700), Jeff Law wrote:
The test for the recently added XiangShan Nanhu microarchitecture is
failing because the scheduler description does not have entries for
certain insn types.
I'm adding branch, jalr, ret and sfb_alu to the scheduler description,
that's
We aren't doing anything with vxsat right now, but I'd like to add it as
an accepted register to the clobber list. If we get this into GCC-14
then we'll avoid some preprocessor-based twiddling if we ever start
using vxsat in the future.
gcc/ChangeLog:
* config/riscv/riscv.h
On Mon, 25 Mar 2024 13:49:18 PDT (-0700), jeffreya...@gmail.com wrote:
On 3/25/24 2:31 PM, Palmer Dabbelt wrote:
On Mon, 25 Mar 2024 13:27:34 PDT (-0700), Jeff Law wrote:
I'd doubt it's worth the complexity. Picking some reasonable value gets
you the vast majority of the benefit
On Mon, 25 Mar 2024 13:27:34 PDT (-0700), Jeff Law wrote:
On 3/25/24 2:13 PM, Palmer Dabbelt wrote:
On Mon, 25 Mar 2024 12:59:14 PDT (-0700), Jeff Law wrote:
On 3/25/24 1:48 PM, Xi Ruoyao wrote:
On Mon, 2024-03-18 at 20:54 -0600, Jeff Law wrote:
+/* Costs to use when optimizing
On Mon, 25 Mar 2024 12:59:14 PDT (-0700), Jeff Law wrote:
On 3/25/24 1:48 PM, Xi Ruoyao wrote:
On Mon, 2024-03-18 at 20:54 -0600, Jeff Law wrote:
+/* Costs to use when optimizing for xiangshan nanhu. */
+static const struct riscv_tune_param xiangshan_nanhu_tune_info = {
+ {COSTS_N_INSNS
/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* Verify that subword atomic op mappings match the Ztso suggested mapping. */
+/* { dg-add-options riscv_a } */
/* { dg-add-options riscv_ztso } */
/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
Presumably these trip up on the non-A targets that Edwin's just adding to the
testers? They'd also trip up anyone running newlib/mulilib tests.
Either way they look right to me, so
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
Thanks!
On Wed, 20 Mar 2024 11:54:34 PDT (-0700), Jeff Law wrote:
On 3/19/24 10:23 AM, Palmer Dabbelt wrote:
On Mon, 18 Mar 2024 20:50:14 PDT (-0700), jeffreya...@gmail.com wrote:
On 3/18/24 3:09 AM, Jivan Hakobyan wrote:
As RV has round instructions it is reasonable to use them instead
On Tue, 19 Mar 2024 13:05:54 PDT (-0700), Vineet Gupta wrote:
On 3/19/24 06:10, Jeff Law wrote:
On 3/19/24 12:48 AM, Andrew Waterman wrote:
On Mon, Mar 18, 2024 at 5:28 PM Vineet Gupta wrote:
On 3/16/24 13:21, Jeff Law wrote:
| 59944:add s0,sp,2047 <
| 59948:mv
On Tue, 19 Mar 2024 12:58:41 PDT (-0700), Andrew Waterman wrote:
On Tue, Mar 19, 2024 at 9:23 AM Palmer Dabbelt wrote:
On Mon, 18 Mar 2024 20:50:14 PDT (-0700), jeffreya...@gmail.com wrote:
>
>
> On 3/18/24 3:09 AM, Jivan Hakobyan wrote:
>> As RV has round instructions it is re
On Mon, 18 Mar 2024 20:50:14 PDT (-0700), jeffreya...@gmail.com wrote:
On 3/18/24 3:09 AM, Jivan Hakobyan wrote:
As RV has round instructions it is reasonable to use them instead of
calling the library functions.
With my patch for the following C code:
double foo(double a) {
return
On Wed, 28 Feb 2024 02:24:40 PST (-0800), Robin Dapp wrote:
I suggest specify -fno-schedule-insns to force tests assembler never
change for any scheduling model.
We already do that and that's the point - as I mentioned before, no
scheduling is worse than default scheduling here (for some
On Wed, 28 Feb 2024 09:36:38 PST (-0800), Patrick O'Neill wrote:
On 2/28/24 07:02, Palmer Dabbelt wrote:
On Wed, 28 Feb 2024 06:57:53 PST (-0800), jeffreya...@gmail.com wrote:
On 2/28/24 05:23, Kito Cheng wrote:
atomic_compare_and_swapsi will use lr.w and sc.w to do the atomic
operation
On Wed, 28 Feb 2024 06:57:53 PST (-0800), jeffreya...@gmail.com wrote:
On 2/28/24 05:23, Kito Cheng wrote:
atomic_compare_and_swapsi will use lr.w and sc.w to do the atomic operation on
RV64, however lr.w is doing sign extend to DI and compare instruction only have
DI mode on RV64, so the
On Tue, 27 Feb 2024 15:53:19 PST (-0800), jeffreya...@gmail.com wrote:
On 2/27/24 15:56, 钟居哲 wrote:
>> I don't think it's that simple. On some uarchs vsetvls are nearly free
while on others they can be fairly expensive. It's not clear (to me)
yet if one approach or the other is going to
On Thu, 22 Feb 2024 20:29:37 PST (-0800), Kito Cheng wrote:
I guess Palmer is too busy, so committed to trunk :P
Thanks, I got distracted with some work stuff ;)
On Tue, Feb 13, 2024 at 11:55 PM Jeff Law wrote:
On 2/9/24 09:53, Palmer Dabbelt wrote:
> This builds for me, an
On Wed, 21 Feb 2024 16:02:50 PST (-0800), Kito Cheng wrote:
Palmer Dabbelt 於 2024年2月22日 週四 07:42 寫道：
On Wed, 21 Feb 2024 15:34:32 PST (-0800), Kito Cheng wrote:
> LGTM for the patch
>
> Li, Pan2 於 2024年2月21日 週三 12:31 寫道：
>
>> Hi kito and juzhe.
>>
>> There may
On Wed, 21 Feb 2024 15:34:32 PST (-0800), Kito Cheng wrote:
LGTM for the patch
Li, Pan2 於 2024年2月21日 週三 12:31 寫道：
Hi kito and juzhe.
There may be 2 items for double-confirm. Thanks a lot.
1. Not very sure if we need to upgrade the version for
__riscv_th_v_intrinsic.
Yes since 0.11 and
-by: Palmer Dabbelt
---
gcc/doc/invoke.texi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 6ec56493e59..4a4bba9f1cd 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -30670,6 +30670,8 @@ Permissible values for this option
This builds for me, and I frequently have python-is-python3 type
packages installed so I think I've been implicitly testing it for a
while. Looks like Kito's tested similar configurations, and the
bugzilla indicates we should be moving over.
gcc/ChangeLog:
PR 109668
*
e/pragma-3.c
@@ -1,4 +1,4 @@
/* { dg-do compile } */
-/* { dg-skip-if "test rvv intrinsic" { *-*-* } { "*" } { "-march=rv*v*" } } */
+/* { dg-skip-if "test rvv intrinsic" { ! riscv_v } */
#pragma riscv intrinsic "report-error" /* { dg-error {unknown '#pragma riscv
intrinsic' option 'report-error'} } */
Reviewed-by: Palmer Dabbelt
On Wed, 24 Jan 2024 16:19:06 PST (-0800), jeffreya...@gmail.com wrote:
On 1/24/24 17:07, Patrick O'Neill wrote:
On 12/16/23 10:58, Jeff Law wrote:
On 12/15/23 17:14, Andrew Waterman wrote:
On Fri, Dec 15, 2023 at 1:38 PM Jeff Law wrote:
On 12/12/23 20:54, Palmer Dabbelt wrote:
I
On Wed, 17 Jan 2024 19:19:58 PST (-0800), monk.chi...@sifive.com wrote:
Thanks for your advice!! I agree it should be fixed in the RISC-V backend
when expansion.
On Wed, Jan 17, 2024 at 10:37 PM Jeff Law wrote:
On 1/17/24 05:14, Richard Biener wrote:
> On Wed, 17 Jan 2024, Monk Chiang
On Thu, 04 Jan 2024 19:17:21 PST (-0800), juzhe.zh...@rivai.ai wrote:
Hi, Wang Feng.
Your patch has some ICEs:
FAIL: gcc.target/riscv/rvv/base/zvbc-intrinsic.c (internal compiler error: RTL
check: expected code 'const_int', have 'reg' in vlmax_avl_type_p, at
config/riscv/riscv-v.cc:4930)
On Thu, 04 Jan 2024 10:20:25 PST (-0800), tamar.christ...@arm.com wrote:
> Hi All,
>
> currently GCC does not treat IFN_COPYSIGN the same as the copysign tree expr.
> The latter has a libcall fallback and the IFN can only do optabs.
>
> Because of this the change I made to optimize copysign only
On Thu, 21 Dec 2023 11:18:22 PST (-0800), jeffreya...@gmail.com wrote:
On 12/20/23 11:41, Palmer Dabbelt wrote:
I couldn't find another way to set the default code model.
gcc/ChangeLog:
* config.gcc (RISC-V): Add --with-cmodel
* config/riscv/riscv.h (TARGET_DEFAULT_CMODEL
On Wed, 20 Dec 2023 10:25:00 PST (-0800), jeffreya...@gmail.com wrote:
On 12/20/23 11:21, Palmer Dabbelt wrote:
Yea, the implementation relies largely on just pushing stuff into the
constant pool, so we're largely independent ABI stuff with the likely
exception being relocations.
Ya, but I
I couldn't find another way to set the default code model.
gcc/ChangeLog:
* config.gcc (RISC-V): Add --with-cmodel
* config/riscv/riscv.h (TARGET_DEFAULT_CMODEL): Use
TARGET_RISCV_DEFAULT_CMODEL
---
I thought we had this already, but I figured I'd double-check my "ya,
On Wed, 20 Dec 2023 10:13:06 PST (-0800), jeffreya...@gmail.com wrote:
>
>
> On 12/20/23 11:08, Palmer Dabbelt wrote:
>> This slipped through the cracks. Probably also NEWS-worthy.
>>
>> gcc/ChangeLog:
>>
>> * doc/invoke.texi (RISC-V): Add -mcmodel=
On Wed, 20 Dec 2023 10:12:04 PST (-0800), jeffreya...@gmail.com wrote:
On 12/20/23 11:05, Palmer Dabbelt wrote:
On Wed, 20 Dec 2023 09:55:48 PST (-0800), jeffreya...@gmail.com wrote:
On 12/18/23 00:46, KuanLin Chen wrote:
Hi Jeff,
Sorry for this missing.
I've removed
This was just merged. Looks like we forgot to add any other NEWS items,
so I've added the header as well.
---
htdocs/gcc-14/changes.html | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index 24e6409a..2a7432a7
This slipped through the cracks. Probably also NEWS-worthy.
gcc/ChangeLog:
* doc/invoke.texi (RISC-V): Add -mcmodel=large.
---
gcc/doc/invoke.texi | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index
On Wed, 20 Dec 2023 09:55:48 PST (-0800), jeffreya...@gmail.com wrote:
On 12/18/23 00:46, KuanLin Chen wrote:
Hi Jeff,
Sorry for this missing.
I've removed riscv_asm_output_pool_epilogue because the pool
beginning is always aligned from FUNCTION_BOUNDARY.
Please find attached. Thank you.
On Tue, 05 Dec 2023 04:57:27 PST (-0800), juzhe.zh...@rivai.ai wrote:
This patch fixes ICE mentioned on PR112851 and PR112852.
Actually these ICEs happens many times in full coverage testing.
The ICE happens on:
bug.c:84:1: internal compiler error: in partial_subreg_p, at rtl.h:3187
84 | }
On Tue, 12 Dec 2023 04:08:09 PST (-0800), jia...@iscas.ac.cn wrote:
Supports RISC-V profiles[1] in -march option.
Default input set the profile is before other formal extensions.
V2: Fixes some format errors and adds code comments for parse function
Thanks for Jeff Law's review and comments.
+
+#if !defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_f)
+#error "__riscv_f"
+#endif
+
+#if !defined(__riscv_d)
+#error "__riscv_d"
+#endif
+
+#if !defined(__riscv_v)
+#error "__riscv_v"
+#endif
+
+#if !defined(__riscv_zvfbfmin)
+#error "__riscv_zvfbfmin"
+#endif
+
+#if defined(__riscv_c)
+#error "__riscv_c"
+#endif
+
+#if defined(__riscv_a)
+#error "__riscv_a"
+#endif
+
+ return 0;
+}
Reviewed-by: Palmer Dabbelt
I can't actually find anything in the ISA manual that makes Ztso imply
A. In theory the memory ordering is just a different thing that the set
of availiable instructions (ie, Ztso without A would still imply TSO for
loads and stores). It also seems like a configuration that could be
sane to
On Wed, 06 Dec 2023 10:48:30 PST (-0800), Vineet Gupta wrote:
On 12/6/23 08:22, Palmer Dabbelt wrote:
Ran the test case at 122e7b4f9d0c2d54d865272463a1d812002d0a5c where the xfail
That's the original port submission, I'm actually kind of surprised it
still builds/works at all.
Full
laced \\\(int\\\) aa_.*with a_" "fre1" { xfail {
riscv*-*-* && lp64 } } } } */
+/* { dg-final { scan-tree-dump "Replaced \\\(int\\\) aa_.*with a_" "fre1" } }
*/
Reviewed-by: Palmer Dabbelt
Though Kito did all the test suite stuff back then, so not s
On Fri, 17 Nov 2023 16:01:27 PST (-0800), jeffreya...@gmail.com wrote:
On 11/17/23 16:16, 钟居哲 wrote:
>> I assume this hunk is meant for riscv_output_operand in riscv.cc. We
may also need to add '^' to the punct_valid_p hook. But yes, this is
the preferred way to go when all we need to do
On Wed, 22 Nov 2023 14:27:50 PST (-0800), jeffreya...@gmail.com wrote:
...
[Trimming everything else, as this is a big change. I'm also making it
a new subject/thread, so folks can see.]
More generally, I think I need to soften my prior statement about
deferring this to gcc-15. This code
The vectorizer picks up these loops and disables unrolling on targets
with variable vector factors. That result in better code here, but it
trips up the unrolling tests. So just disable vectorization for these.
gcc/testsuite/ChangeLog:
PR target/112531
* gcc.dg/unroll-8.c:
I was poking around with this test failure and noticed it was exercising
undefined behavior. The return type doesn't matter for what's being
tested, so just mark it as void.
gcc/testsuite/ChangeLog:
* gcc.dg/unroll-8.c: Remove UB.
---
I didn't tes this, but it seems trivial enough that
On Fri, 17 Nov 2023 03:39:48 PST (-0800), juzhe.zh...@rivai.ai wrote:
90% theadvector extension reusing current RVV 1.0 instructions patterns:
Just change ASM, For example:
@@ -2923,7 +2923,7 @@ (define_insn "*pred_mulh_scalar"
(match_operand:VFULLI_D 3 "register_operand" "vr,vr,
I'm going to be traveling for the next two weeks (Plumbers and then
Thanksgiving), so I won't be at the patchwork syncs.
#define uintX_t unsigned long
Presumably this still passes the tests? If so it LGTM so
Reviewed-by: Palmer Dabbelt
Thanks!
On Mon, 06 Nov 2023 18:47:24 PST (-0800), jeffreya...@gmail.com wrote:
On 11/6/23 18:19, Vineet Gupta wrote:
Do we have call tomorrow, given some folks are traveling for RV Summit ?
I'll be in the air, so "no" from me.
I'll be on the ground, but not sure that counts for much. IIRC Kito
On Tue, 31 Oct 2023 16:18:35 PDT (-0700), jeffreya...@gmail.com wrote:
On 10/31/23 12:35, Vineet Gupta wrote:
riscv_promote_function_mode doesn't promote a SI to DI for libcalls
case.
The fix is what generic promote_mode () in explow.cc does. I really
don't understand why the old code didn't
On Wed, 27 Sep 2023 10:28:55 PDT (-0700), jeffreya...@gmail.com wrote:
On 9/25/23 15:17, Maciej W. Rozycki wrote:
On Mon, 25 Sep 2023, Maciej W. Rozycki wrote:
NB the use of this specific header, still in place elsewhere,
seems gratuitous to me. We don't need or indeed want to print
On Mon, 18 Sep 2023 15:13:04 PDT (-0700), Vineet Gupta wrote:
On 9/18/23 09:11, Jeff Law wrote:
On 9/18/23 09:24, Kito Cheng wrote:
I may missed that one time too, not on plane yet, but need to go bed
earlier due to my flight is in next day early morning...
I'm unavailable as well, though I
for the test suite. Something's
still wrong somewhere with Patrick's builds, though...
On Thu, Sep 21, 2023 at 11:20 AM Palmer Dabbelt wrote:
On Wed, 20 Sep 2023 10:47:23 PDT (-0700), Patrick O'Neill wrote:
> Juzhe,
>
> On a more general note, are we expecting #include to cause a
> test
On Wed, 20 Sep 2023 10:47:23 PDT (-0700), Patrick O'Neill wrote:
Juzhe,
On a more general note, are we expecting #include to cause a
testcase to fail?
My motivation is to make the testsuite less noisy when checking for
regressions. For example, a patch like this one:
On Wed, 20 Sep 2023 07:58:49 PDT (-0700), juzhe.zh...@rivai.ai wrote:
According to PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110751
As Richard and Richi suggested, we recognize uninitialized SSA_NAME and convert
it
into SCRATCH rtx if the target predicate allows SCRATCH.
It can help to
My flight to the Cauldron lands in the middle of the meeting, so I'm
going to miss it. In theory it's all set up such that anyone can
join/run the meeting.
an equivalent patch (without the comment changes).
This patch resolves the build errors on glibc rv64gc with
--enable-checking=rtl.
Tested for regressions (without --enable-checking=rtl) using rv64gc &
rv32gc glibc.
This patch does not cause any regressions on those targets.
Reviewed-by: Palmer Dab
On Thu, 07 Sep 2023 13:16:36 PDT (-0700), dimi...@dinux.eu wrote:
Hi,
This patch appears to have caused PR 111259.
Thanks. Looks like wer'e not running our tests with RTL checking,
Patrick is going to try and see if we've got compute time left for some
builds -- even just having builds
On Wed, 06 Sep 2023 09:47:05 PDT (-0700), jeffreya...@gmail.com wrote:
On 9/6/23 10:22, Palmer Dabbelt wrote:
On Wed, 06 Sep 2023 09:07:33 PDT (-0700), christoph.muell...@vrull.eu
wrote:
From: Christoph Müllner
This patch implements the expansion of the strlen builtin for RV32/RV64
On Wed, 06 Sep 2023 09:07:33 PDT (-0700), christoph.muell...@vrull.eu wrote:
From: Christoph Müllner
This patch implements the expansion of the strlen builtin for RV32/RV64
for xlen-aligned aligned strings if Zbb or XTheadBb instructions are available.
The inserted sequences are:
rv32gc_zbb
On Tue, 05 Sep 2023 20:07:16 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
On 9/5/23 20:33, Tsukasa OI wrote:
Internally we have this as:
(TARGET_ZICOND || TARGET_XVENTANACONDOPS)
I don't really care, so I'm happy to go with yours.
Because XVentanaCondOps instructions are only available
On Thu, 31 Aug 2023 10:57:52 PDT (-0700), Vineet Gupta wrote:
On 8/31/23 06:51, Jeff Law wrote:
On 8/30/23 15:57, Vineet Gupta wrote:
This was tripping up gcc.c-torture/execute/pr60003.c at -O1 since the
pattern semantics can't be expressed by zicond instructions.
This involves test code
Vineet just got bit by the autovec params, and a bunch of us forgot
about the second one.
gcc/ChangeLog:
* doc/invoke.texi (RISC-V Options): Add some -march special
cases.
---
gcc/doc/invoke.texi | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff
On Tue, 29 Aug 2023 08:48:56 PDT (-0700), e...@rivosinc.com wrote:
On 8/28/2023 3:40 PM, Jeff Law wrote:
On 8/15/23 12:29, Edwin Lu wrote:
This patch is a modification of
https://gcc.gnu.org/pipermail/gcc-patches/2023-January/610115.html
following the discussion on
gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-9.c
similarity index 100%
rename from gcc/testsuite/gcc.target/riscv/vector-abi-9.c
rename to gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-9.c
Reviewed-by: Palmer Dabbelt
I think Joern is still looking into fixing up all these explicit
On Tue, 22 Aug 2023 10:59:35 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
On 8/22/23 11:40, Vineet Gupta wrote:
... otherwise user has no clue what -param to actually change
gcc/ChangeLog:
* config/riscv/riscv.opt: Add --param names
riscv-autovec-preference and
On Tue, 22 Aug 2023 10:39:38 PDT (-0700), Jeff Law wrote:
This adds multiarch support to the RISC-V port so that bootstraps work
with Debian out-of-the-box. Without this patch the stage1 compiler is
unable to find headers/libraries when building the stage1 runtime.
This is functionally (and
+)
+{
+a[i] = (val & 1) ? (-val) >> 17 : val;
+val += b;
+}
+}
Unless I'm missing something it looks like we're missing at least Wc1 as
well, and maybe a few others?
Either way
Reviewed-by: Palmer Dabbelt
Thanks!
On Thu, 17 Aug 2023 10:03:04 PDT (-0700), rdapp@gmail.com wrote:
Indeed all ANYLSF patterns have TARGET_HARD_FLOAT (==f extension) which
is incompatible with ZHINX or ZHINXMIN anyway. That should really be fixed
separately or at least clarified, maybe I'm missing something.
We've also got
On Thu, 17 Aug 2023 10:10:38 PDT (-0700), Patrick O'Neill wrote:
On 8/16/23 21:36, Jeff Law wrote:
On 8/16/23 19:17, Patrick O'Neill wrote:
This adds new regression tests to ensure half-register rotations are
correctly optimized into rori instructions.
gcc/testsuite/ChangeLog:
*
On Wed, 16 Aug 2023 15:59:13 PDT (-0700), jeffreya...@gmail.com wrote:
On 8/16/23 07:50, Robin Dapp wrote:
But if it's a float16 precision issue then I would have expected both
the computations for the lhs and rhs values to have suffered
similarly.
Yeah, right. I didn't look closely
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