On 10/07/15 12:35, Christophe Lyon wrote:
On 10 July 2015 at 09:14, Christian Bruel christian.br...@st.com wrote:
On 07/09/2015 05:39 PM, Christophe Lyon wrote:
Some multilibs do not support Thumb mode on ARM targets. This is the
case for instance when target is arm-linux-gnueabihf and with
yes, that '50' should be a parameter somewhere in loop_vec_info.
I see the broken code is still in aarch64.c - can someone please test
apply the above
patch?
I believe this is on Alan's todo list.
Ramana
Thanks,
Richard.
Richard.
Thanks,
James
---
[1]: Cortex-57 Software
I haven't seen the patch yet but here are my thoughts on where this should be
going.
On 07/07/15 18:17, Alan Lawrence wrote:
Kyrill Tkachov wrote:
On 07/07/15 17:34, Alan Lawrence wrote:
Kyrill Tkachov wrote:
On 07/07/15 14:09, Kyrill Tkachov wrote:
Hi Alan,
On 07/07/15 13:34, Alan
On 21/04/15 10:11, Kyrill Tkachov wrote:
Hi all,
This is the first of a series to clean up and simplify the arm rtx costs
function.
This patch initialises the cost to COSTS_N_INSNS (1) at the top and
increments it when appropriate
in the rest of the function. This makes it more similar
On 30/06/15 13:07, Christian Bruel wrote:
Hi,
A little bit of polishing around arm/thumb attribute_target emission and
testing: Since the arch mode is emitted for each function, the file setting
becomes useless or redundant.
for example with attr_thumb.c:
=.arm
=.syntax
On 06/07/15 17:38, Alan Lawrence wrote:
Trying to push these now (svn!), patch 2 is going first.
I realize my second iteration of patch 1/2, dropped the testcases from the
first version. Okay to include those as per
https://gcc.gnu.org/ml/gcc-patches/2015-07/msg00215.html ?
Yeah the
On 06/07/15 12:00, Alan Lawrence wrote:
Eric Botcazou wrote:
Technically this is incorrect since AGGREGATE_TYPE_P includes ARRAY_TYPE
and ARRAY_TYPE doesn't have TYPE_FIELDS. I doubt we could reach that
case though (unless there's a language that allows passing arrays by value).
Ada
On 18/06/15 20:02, Eric Botcazou wrote:
Please mark this pattern with (set_attr type multiple).
Done.
While I suspect that stack probing is done before any insns with invalid
constants in the function, it would be better to model the length of
this insn so that the minipool logic is not
On Thu, Jul 2, 2015 at 12:03 PM, Matthew Wahab
matthew.wa...@foss.arm.com wrote:
On 22/06/15 12:56, Richard Biener wrote:
I plan to release GCC 5.2.0 around July 10th which means a release
candidate being done around July 3rd.
Please check your open regression bugs for ones that eligible
On Thu, Jul 2, 2015 at 7:34 PM, Sebastian Pop seb...@gmail.com wrote:
On Thu, Jul 2, 2015 at 1:17 PM, Tobias Grosser tob...@grosser.es wrote:
On 07/02/2015 06:52 PM, Aditya Kumar wrote:
gcc/ChangeLog:
2015-07-02 Aditya Kumar aditya...@samsung.com
Sebastian Pop
On Wed, Jul 1, 2015 at 12:32 PM, Matthew Wahab
matthew.wa...@foss.arm.com wrote:
Hello,
Tests I recently added for the code generated by the ARM backend for the
__sync
builtins had
- 'do-require-effective-target', instead of the directive
'dg-require-effective-target' and
- 'stlex'
On Mon, Jun 22, 2015 at 10:52 AM, Matthew Wahab matthew.wa...@arm.com wrote:
This is the ARM version of the patches to strengthen memory barriers for the
__sync builtins on ARMv8 targets
(https://gcc.gnu.org/ml/gcc-patches/2015-05/msg01989.html).
This patch adds tests for the code generated
On Mon, Jun 22, 2015 at 10:50 AM, Matthew Wahab matthew.wa...@arm.com wrote:
This is the ARM version of the patches to strengthen memory barriers for the
__sync builtins on ARMv8 targets
(https://gcc.gnu.org/ml/gcc-patches/2015-05/msg01989.html).
This patch changes the code generated for
On Mon, Jun 22, 2015 at 10:48 AM, Matthew Wahab matthew.wa...@arm.com wrote:
This is the ARM version of the patches to strengthen memory barriers for the
__sync builtins on ARMv8 targets
(https://gcc.gnu.org/ml/gcc-patches/2015-05/msg01989.html).
The problem is that the barriers generated for
As part of the work on PR66192 I promised a doc update at some point -
here's that - hopefully better late than never.
I also wonder if this is worth putting into the documentation in
addition to our release notes though I couldn't convince myself that
standards.texi was the right place for
Radhakrishnan ramana.radhakrish...@arm.com
* config/arm/arm.c (arm_output_multireg_pop): Fix use of
TARGET_UNIFIED_ASM.
commit c085a69d4c1b9f9e43ef9655d1e88e7286ca3c2f
Author: Ramana Radhakrishnan ramana.radhakrish...@arm.com
Date: Thu Jun 25 09:43:11 2015 +0100
Use
On Mon, Jun 22, 2015 at 5:56 PM, Alex Velenko alex.vele...@arm.com wrote:
On 20/05/15 21:14, Joseph Myers wrote:
Again, the condition you propose to add doesn't make sense. arm_arch_X_ok
is only appropriate for tests using an explicit -march=X. Testing with
-march=armv7* should
This fixes PR target/29693 by returning DWARF_FRAME_REGISTERS instead of
calling gcc_unreachable.
Applied to trunk after bootstrap and regression testing on armhf.
Ramana
2015-06-25 Ramana Radhakrishnan ramana.radhakrish...@arm.com
PR target/29693
* config/arm/arm.c
Benedikt,
On 25/06/15 08:01, pins...@gmail.com wrote:
On Jun 18, 2015, at 5:04 AM, Benedikt Huber
benedikt.hu...@theobroma-systems.com wrote:
arch64 offers the instructions frsqrte and frsqrts, for rsqrt estimation and
a Newton-Raphson step, respectively.
There are ARMv8 implementations
to trunk.
Will apply to 5 after regression testing there and 4.9 after it unfreezes.
Ramana
2015-06-24 Ramana Radhakrishnan ramana.radhakrish...@arm.com
PR target/63408
* config/arm/arm.c (vfp3_const_double_for_fract_bits): Disable
for negative numbers.
2015-06-24
On 24/06/15 02:00, Sandra Loosemore wrote:
On 06/18/2015 11:32 AM, Eric Botcazou wrote:
The attached patch teaches regrename to validate insns affected by each
register renaming before making the change. I can see at least two
other ways to handle this -- earlier, by rejecting renamings that
-24 Ramana Radhakrishnan ramana.radhakrish...@arm.com
* gcc.target/arm/fixed_float_conversion.c: Skip for inappropriate
multilibs.
* gcc.target/arm/memset-inline-10.c: Likewise.
* gcc.target/arm/pr58784.c: Likewise.
* gcc.target/arm/pr59985.C: Likewise
On 12/06/15 21:50, Abe Skolnik wrote:
Hi everybody!
In the current implementation of if conversion, loads and stores are
if-converted in a thread-unsafe way:
* loads were always executed, even when they should have not been.
Some source code could be rendered invalid due to null
On 16/06/15 22:25, James Lemke wrote:
A divide by zero exception was not giving a proper traceback for LINUX
ARM_EABI. The attached patch fixes the problem on trunk (and several
local branches).
Tested on gcc-trunk for arm-none-linux-gnueabi.
OK to commit?
2015-06-16 James Lemke
On Fri, Jun 19, 2015 at 7:04 PM, Charles Baylis
charles.bay...@linaro.org wrote:
On 18 June 2014 at 11:06, Ramana Radhakrishnan
ramana@googlemail.com wrote:
On Tue, Jun 17, 2014 at 4:03 PM, Charles Baylis
charles.bay...@linaro.org wrote:
Your mention of larger vector modes prompted me
On Tue, Jun 23, 2015 at 5:18 PM, James Lemke jwle...@codesourcery.com wrote:
Tested on gcc-trunk for arm-none-linux-gnueabi.
OK to commit?
2015-06-16 James Lemke jwle...@codesourcery.com
libgcc/config/arm/
* lib1funcs.S (aeabi_idiv0, aeabi_ldiv0): Add CFI entries for
On Mon, Jun 22, 2015 at 7:11 PM, Alexander Monakov amona...@ispras.ru wrote:
On Mon, 22 Jun 2015, Jiong Wang wrote:
Have done a quick experiment, -fno-plt doesn't work on AArch64.
it's because although this patch force the function address into register,
but the combine pass runs later
I am not very familiar with this feature entirely so please bear with me
during review and will find some time to do some experiments with the
feature during this week, but a couple of things with respect to the
patch immediately spring to mind.
+(define_insn probe_stack_range
+ [(set
On Tue, Jun 16, 2015 at 1:35 PM, Christian Bruel christian.br...@st.com wrote:
Hi,
This fixes the torture/pr52429.c regression due to arm_set_current_function
that needs to handle DECL_FUNCTION_SPECIFIC_TARGET when set to
target_option_default_node.
Catch up with x86 and rs6000 backends.
On 16/06/15 09:54, Eric Botcazou wrote:
This is the C front-end + C family part.
* doc/extend.texi (type attributes): Document scalar_storage_order.
* doc/invoke.texi (Warnings): Document -Wno-scalar-storage-order.
c-family/
* c-common.c (c_common_attributes): Add
On Fri, Jun 12, 2015 at 10:06 AM, Jonathan Wakely jwak...@redhat.com wrote:
On 11/06/15 23:56 +0200, Torvald Riegel wrote:
On Fri, 2015-05-22 at 12:37 +0100, Ramana Radhakrishnan wrote:
I don't think we can remove _GLIBCXX_READ_MEM_BARRIER and
_GLIBCXX_WRITE_MEM_BARRIER from atomic_word.h
On 27/05/15 11:25, Kyrill Tkachov wrote:
Ping.
Here is the rebased (and retested) patch after Christian's series.
Thanks,
Kyrill
On 18/05/15 11:26, Kyrill Tkachov wrote:
Hi all,
When using the short Thumb2 IT blocks we want to also restrict ifcvt so that it
will not end up generating a
On 18/05/15 11:26, Kyrill Tkachov wrote:
Hi all,
When using the short Thumb2 IT blocks we want to also restrict ifcvt so that it
will not end up generating a number of back-to-back cond_execs
that will later end up being back to back single-instruction IT blocks.
Branching over them should
Sorry about missing this hunk in the original submission, was in my tree
but I hadn't spotted this as I was playing between the original AArch64
TARGET_RELAXED_ORDER and this patch.
Applied as obvious.
PR target/66200
PR target/66498
PR c++/66192
* g++.dg/testsuite/aarch64_guard1.C: Adjust
Bah, Now with patch attached.
Ramana
On 10/06/15 08:44, Ramana Radhakrishnan wrote:
Sorry about missing this hunk in the original submission, was in my tree
but I hadn't spotted this as I was playing between the original AArch64
TARGET_RELAXED_ORDER and this patch.
Applied as obvious.
PR
Hi,
A patch that's been sitting in my tree for sometime has been something
to fix up using dmb ish instead of dmb sy in the ARM backend. This
brings us in line with the AArch64 backend's behaviour as well for the
same. A future cleanup to write this in the form of memory_fences and
exploit
On 22/05/15 17:56, Torvald Riegel wrote:
On Fri, 2015-05-22 at 12:37 +0100, Ramana Radhakrishnan wrote:
Hi,
While writing atomic_word.h for the ARM backend to fix PR target/66200
I
thought it would make more sense to write it all up with atomic
primitives instead of providing various fragile
On Mon, Jun 8, 2015 at 9:07 AM, lin zuojian manjian2...@gmail.com wrote:
Hi,
in arm.c
static void
arm_conditional_register_usage (void)
...
if (TARGET_32BIT TARGET_HARD_FLOAT TARGET_VFP)
{
/* VFPv3 registers are disabled when earlier VFP
versions are
On 08/06/15 09:45, Christian Bruel wrote:
Hi Ramana,
Ok, I see.
The patch looks ok to me modulo the typo nits I pointed out, but I
think Ramana
should have the final say here as he's already started reviewing it
and it adds quite
a lot of functionality.
Thanks,
Kyrill
do you have other
On Sat, Jun 6, 2015 at 10:49 AM, Andreas Schwab sch...@linux-m68k.org wrote:
Bootstrap fails on aarch64:
Comparing stages 2 and 3
warning: gcc/cc1objplus-checksum.o differs
warning: gcc/cc1obj-checksum.o differs
warning: gcc/cc1plus-checksum.o differs
warning: gcc/cc1-checksum.o differs
On 29/05/15 20:40, Jason Merrill wrote:
On 05/29/2015 09:18 AM, Ramana Radhakrishnan wrote:
+static tree
+build_atomic_load_byte (tree src, HOST_WIDE_INT model)
This function needs a comment. The C++ changes are OK with that.
Jason
I'm assuming your review and rth's review constitute
Committed with said change r223982.
Is patch ok for fsf-5 backport?
Alex
OK if no regressions.
Ramana
On 03/06/15 05:12, Shiva Chen wrote:
snip
It seems that stl should generate as stlne.
Otherwise, slt will get null reference when r3 is 0.
To fix the issue, add %? when output stl assembly pattern in sync.md.
Please also mark these patterns as predicable.
i.e. (set_attr predicable
Hi Sriraman,
Thanks for the detailed explanation, that was useful.
I'm sorry I'm going to push back again for the same reason.
Let me describe the problem I am having in a little more detail:
For the PIC case, I think there is no confusion. Both of us agree on
what is being done. Attribute
On Tue, Jun 2, 2015 at 7:15 PM, Sriraman Tallam tmsri...@google.com wrote:
On Mon, Jun 1, 2015 at 1:33 PM, Ramana Radhakrishnan
ramana@googlemail.com wrote:
On Mon, Jun 1, 2015 at 7:55 PM, Sriraman Tallam tmsri...@google.com wrote:
On Mon, Jun 1, 2015 at 11:41 AM, Ramana Radhakrishnan
-patches/2015-05/msg01539.html
(5.2/6) https://gcc.gnu.org/ml/gcc-patches/2015-05/msg01558.html
(6 /6) https://gcc.gnu.org/ml/gcc-patches/2015-05/msg01542.html
Cheers
Christian
On 06/01/2015 11:53 AM, Ramana Radhakrishnan wrote:
2015-05-11 9:49 GMT+01:00 Christian Bruel christian.br
On 01/06/15 10:48, Alex Velenko wrote:
Hi,
This patch fix thumb-ltu.c to pass excess error test.
Without default -std=gnu90 flag, this testcase started failing
as some functions were called before being predefined.
Is patch ok?
gcc/testsuite
2015-06-01 Alex Velenko alex.vele...@arm.com
Why isn't it just an indirect call in the cases that would require a GOT
slot and a direct call otherwise ? I'm trying to work out what's so
different on each target that mandates this to be in the target backend.
Also it would be better to push the tests into gcc.dg if you can and check
for
2015-05-11 9:49 GMT+01:00 Christian Bruel christian.br...@st.com:
-BEGIN PGP MESSAGE-
Version: GnuPG v1.4.11 (GNU/Linux)
hQIOA7kay12Fw5I3EAf/dJLl6z88mNVga3f+gsF8SKunpHWh+OsNTdg0zovUsPH/
YX1l86qL92we5htdf86j8rKTOH9PdOQCITsAnwKecWgpas5cGV4s2LHcbX/wQyl4
On Mon, Jun 1, 2015 at 7:01 PM, Sriraman Tallam tmsri...@google.com wrote:
On Mon, Jun 1, 2015 at 1:24 AM, Ramana Radhakrishnan
ramana.radhakrish...@arm.com wrote:
Why isn't it just an indirect call in the cases that would require a GOT
slot and a direct call otherwise ? I'm trying to work
On Mon, Jun 1, 2015 at 7:55 PM, Sriraman Tallam tmsri...@google.com wrote:
On Mon, Jun 1, 2015 at 11:41 AM, Ramana Radhakrishnan
ramana@googlemail.com wrote:
On Mon, Jun 1, 2015 at 7:01 PM, Sriraman Tallam tmsri...@google.com wrote:
On Mon, Jun 1, 2015 at 1:24 AM, Ramana Radhakrishnan
On 22/05/15 18:36, Jason Merrill wrote:
On 05/22/2015 11:23 AM, Ramana Radhakrishnan wrote:
On 22/05/15 15:28, Jason Merrill wrote:
I do notice that get_guard_bits after build_atomic_load just won't work
on non-ARM targets, as it ends up trying to take the address of a value.
So on powerpc
On 13/05/15 11:16, Christian Bruel wrote:
- [2.2/6]: Redefine TARGET_MACROS for #pragma GCC target without
thumbness the glue.
Here it is, no regression for
arm-sim/
arm-sim//-march=armv7-a
arm-sim//-mthumb
arm-sim//-mthumb/-march=armv7-a
Obviously, [4/6],[5/6] and
On 26/05/15 09:58, Richard Biener wrote:
On Fri, May 22, 2015 at 5:44 PM, Jan Hubicka hubi...@ucw.cz wrote:
Hi,
PR 66181 is about ICE in verify_type that complains that type and its variant
differs
by TYPE_NO_FORCE_BLK. This flag is kind-of internal to stor-layout.c, so the
divergence
may
On Wed, May 13, 2015 at 9:49 AM, Christian Bruel christian.br...@st.com wrote:
2 parts for maintainers
- c-family: machine descriptions export macro definitions into c
implementation : need to export 'builtin_define_with_int_value' and '
builtin_define_type_sizeof'
Could a global
On Tue, May 26, 2015 at 2:42 PM, Christian Bruel christian.br...@st.com wrote:
On 05/26/2015 12:11 PM, Ramana Radhakrishnan wrote:
On 13/05/15 11:16, Christian Bruel wrote:
- [2.2/6]: Redefine TARGET_MACROS for #pragma GCC target without
thumbness the glue.
Here
+ add x19, x20, :lo12:.LANCHOR0
+ ldarx0, [x19]
+ tbz x0, 0, .L11
+.L9:
+ ldr x0, [x19, 8]
regards
Ramana
2015-05-22 Ramana Radhakrishnan ramana.radhakrish...@arm.com
PR c++/66192
* config/alpha/alpha.c (TARGET_RELAXED_ORDERING): Likewise.
* config
Bah ! now with patch attached.
Ramana
diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
index 1ba99d0..857c9ac 100644
--- a/gcc/config/alpha/alpha.c
+++ b/gcc/config/alpha/alpha.c
@@ -9987,12 +9987,6 @@ alpha_atomic_assign_expand_fenv (tree *hold, tree
*clear, tree *update)
Ok for trunk?
I can't approve but do you mind taking care of -march=armv8-a in the
arm backend too as that would have the same issues.
Ramana
Matthew
gcc/
2015-05-21 Matthew Wahab matthew.wa...@arm.com
* config/aarch64/aarch64.c (aarch64_emit_post_barrier): New.
/atomic_word.h: Rewrite using atomics.
commit a360fdf84683777db764ba313354da92691aeb17
Author: Ramana Radhakrishnan ramana.radhakrish...@arm.com
Date: Fri May 22 08:00:10 2015 +
rewrite as atomics.
diff --git a/libstdc++-v3/config/cpu/generic/atomic_word.h
b/libstdc++-v3/config/cpu/generic
On 22/05/15 14:40, Jason Merrill wrote:
On 05/22/2015 07:23 AM, Ramana Radhakrishnan wrote:
+ /* Load the guard value only through an atomic acquire load. */
+ guard = build_atomic_load (guard, MEMMODEL_ACQUIRE);
+
/* Check to see if the GUARD is zero. */
guard = get_guard_bits
On Mon, Apr 20, 2015 at 5:28 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
A pet project of mine is to get to the point where backend rtx costs
functions won't have
to handle rtxes that don't match down to any patterns/expanders we have. Or
at least limit such cases.
A case dealt
On 22/05/15 15:28, Jason Merrill wrote:
On 05/22/2015 09:55 AM, David Edelsohn wrote:
On Fri, May 22, 2015 at 9:40 AM, Jason Merrill ja...@redhat.com wrote:
On 05/22/2015 07:23 AM, Ramana Radhakrishnan wrote:
+ /* Load the guard value only through an atomic acquire load. */
+ guard
On 21/05/15 06:33, Sandra Loosemore wrote:
ARM testing shares the AArch64 advsimd-intrinsics execution tests. On
ARM, though, the NEON support being tested is optional -- some arches
are compatible with the NEON compilation options but hardware available
for testing might or might not be able
And here's an additional patch for the testsuite which was missed in the
original posting.
This is a testism that's testing code generation as per
TARGET_RELAXED_ORDERING being false and therefore needs to be adjusted
as attached.
Ramana
PR target/66200
* g++.dg/abi/aarch64_guard1.C:
On Wed, May 20, 2015 at 9:11 PM, Joseph Myers jos...@codesourcery.com wrote:
On Wed, 20 May 2015, Alex Velenko wrote:
Hi,
This patch prevents arm_thumb1_ok XPASS in sibcall-3.c and sibcall-4.c
testcases. Sibcalls are not ok for Thumb1 and testcases need to be fixed.
arm_thumb1_ok means
Testism introduced by last commit to fix PR26702 on arm-*-linux*
targets. The fix is to restore target selector to arm*-*-eabi* as the
target macro changes only affect arm*-*-eabi*
Applied to trunk as obvious
Ramana
* gcc.target/arm/pr26702.c: Adjust target selector.
Index:
On 20/05/15 14:37, David Howells wrote:
Paul E. McKenney paul...@linux.vnet.ibm.com wrote:
I was thinking of y as a simple variable, but if it is something more
complex, then the compiler could do this, right?
char *x;
y;
x = z;
Yeah. I presume it has to maintain
On 20/05/15 15:03, Paul E. McKenney wrote:
On Wed, May 20, 2015 at 02:44:30PM +0100, Ramana Radhakrishnan wrote:
On 20/05/15 14:37, David Howells wrote:
Paul E. McKenney paul...@linux.vnet.ibm.com wrote:
I was thinking of y as a simple variable, but if it is something more
complex
on the assumption that one
doesn't need the barriers elsewhere). I suspect other architectures like
MIPS may also be affected by this.
commit 414345c424fa020717c6c3083089cd987f3032db
Author: Ramana Radhakrishnan ramana.radhakrish...@arm.com
Date: Wed May 20 13:55:44 2015 +0100
Add relaxed memory
Hi,
Like the ARM port, the AArch64 ports needs to set glibc_integral_traps
to false as integer divide instructions do not trap.
Bootstrapped and regression tested on aarch64-none-linux-gnu
Ok to apply ?
regards
Ramana
2015-05-17 Ramana Radhakrishnan ramana.radhakrish...@arm.com
.
regards
Ramana
2015-05-17 Ramana Radhakrishnan ramana.radhakrish...@arm.com
* configure.host: Define cpu_defines_dir for ARM.
* config/cpu/arm/cpu_defines.h: New file.
Index: ChangeLog
===
--- ChangeLog (revision
On Tue, May 19, 2015 at 4:54 PM, pins...@gmail.com wrote:
On May 19, 2015, at 5:54 AM, Ramana Radhakrishnan
ramana.radhakrish...@foss.arm.com wrote:
Hi,
Like the ARM port, the AArch64 ports needs to set glibc_integral_traps to
false as integer divide instructions do not trap
On Thu, Apr 23, 2015 at 9:29 AM, Ludovic Courtès l...@gnu.org wrote:
As discussed at https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65711.
Patch is for both 4.8 and 4.9 (possibly 5.1 too, I haven’t checked.)
OK for trunk. This is also ok for all release branches if no
objections in 24 hours.
On 15/05/15 07:41, Kugan wrote:
Hi Richard,
r223090 seem to miss a parenthesis and seem to be causing:
from ../../widen/gcc/fold-const.c:46:
../../widen/gcc/fold-const.c: In function 'tree_node*
fold_range_test(location_t, tree_code, tree, tree, tree)':
On 13/05/15 19:11, Martin Galvan wrote:
Here's the new patch. I downloaded the gcc sources from the SVN
repository, removed the extra semicolon from my version of the files
and re-generated the patch using svn diff, making sure the context
info had all the tabs from the original. I then
On 07/05/15 23:12, Jim Wilson wrote:
I noticed that the list of -mtune options in the arm-cores.def file
didn't match the list in the doc/invoke.texi file. There are 3 cores
missing: generic-armv7-a, cortex-a17, and cortex-a17.cortex-a7. This
patch adds the missing cores to the docs.
Jim
On 12/05/15 14:01, Martin Galvan wrote:
On Tue, May 12, 2015 at 5:49 AM, Ramana Radhakrishnan
ramana.radhakrish...@arm.com wrote:
That's what I mean when I say email clients munged it : email clients and
/ or some popular email servers appear to end up munging white spaces and
patches don't
On 13/05/15 17:37, Ramana Radhakrishnan wrote:
On 12/05/15 14:01, Martin Galvan wrote:
On Tue, May 12, 2015 at 5:49 AM, Ramana Radhakrishnan
ramana.radhakrish...@arm.com wrote:
That's what I mean when I say email clients munged it : email
clients and
/ or some popular email servers appear
On Tue, May 12, 2015 at 7:43 PM, Jakub Jelinek ja...@redhat.com wrote:
Hi!
This patch improves expansion of __builtin_mul_overflow for HImode, both
signed and unsigned, on x86_64/i686.
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
2015-05-12 Jakub Jelinek
On 05/05/15 09:22, Kyrill Tkachov wrote:
Hi all,
As the PR says, the movcond_addsi pattern takes the REGNO of an operand that
may be a CONST_INT.
The fix for that is rather simple (perhaps even obvious?).
Unfortunately the testcase is in ada, and I'm not sure how to integrate this
into the
On 11/05/15 20:44, Martin Galvan wrote:
On Mon, May 11, 2015 at 4:45 AM, Ramana Radhakrishnan
ramana.radhakrish...@arm.com wrote:
sorry about the slow response, I was travelling for a bit and missed your
emails. Trying your patch out gives me failures possibly because my mail
client munged
, 2015 at 2:07 PM, Martin Galvan
martin.gal...@tallertechnologies.com wrote:
Thanks a lot. I don't have write access to the repository, could you
commit this for me?
On Tue, Apr 28, 2015 at 1:21 PM, Ramana Radhakrishnan
ramana@googlemail.com wrote:
On Tue, Apr 28, 2015 at 4:19 PM, Martin Galvan
On Mon, May 11, 2015 at 10:43 AM, Thomas Preud'homme
thomas.preudho...@arm.com wrote:
Hi,
Testcase made for PR64616 was only passing when using a litteral pool. Rather
than having an alternative for systems where this is not true, this patch
changes the test to check that a global copy
On Mon, May 11, 2015 at 10:13 AM, Christian Bruel
christian.br...@st.com wrote:
OK with those changes.
Ramana
thanks, done
following up the thumb_code cleanup, here is a missing chunk for the vxworks
config.
arm-vxworks build checked. ok for trunk ?
thanks,
Christian
OK thanks
I'm still playing with the code, so this is a partial review.
We should prevent inlining of ARM state functions into functions we know
will be T16 if !TARGET_SOFT_FLOAT on the grounds that the architecture
doesn't have floating point instruction encodings in the T16 ISA
(Thumb1). We'll just
On 06/05/15 15:27, Christian Bruel wrote:
Implements the hooks for #pragma GCC target
A test included to check that macros were correctly defined/undefined on
pragma regions.
Thanks
Christian
Missing the hooks - this only appears to have the test.
Ramana
2014-09-23 Christian Bruel christian.br...@st.com
* config/arm/arm.h (arm_option_override): Reoganized and split.
Reorganized and split into
(arm_option_params_internal); New function.
s/;/: New function.
(arm_option_check_internal): New function.
On 06/05/15 15:22, Christian Bruel wrote:
Re-implement ARM_DECLARE_FUNCTION_NAME as a function. That will make
changed related to unified/divided and mode directives easier to insert.
Patch could be smaller as below.
Thanks
Christian
2014-09-23 Christian Bruel christian.br...@st.com
On 06/05/15 15:20, Christian Bruel wrote:
In preparation of the pragma target
reorganize ÂTARGET_CPU_CPP_BUILTINSÂ to redefine mode dependent macros
based on current thumb_p.
I'm not entirely happy with this patch as it appears to be too tied to
just the thumbness of the attributes.
On Tue, May 5, 2015 at 6:53 PM, Sandra Loosemore
san...@codesourcery.com wrote:
This patch I posted last fall:
https://gcc.gnu.org/ml/gcc-patches/2014-11/msg00711.html
still has not been reviewed, in spite of me pinging it several times before
GCC 5 went into stage 4. Now that we're back in
On Thu, Apr 30, 2015 at 6:49 PM, Yvan Roux yvan.r...@linaro.org wrote:
Hi,
On 23 March 2015 at 18:47, Yvan Roux yvan.r...@linaro.org wrote:
Hi,
On 23 March 2015 at 17:08, Ramana Radhakrishnan
ramana@googlemail.com wrote:
On Wed, Mar 18, 2015 at 10:19 AM, Yvan Roux yvan.r...@linaro.org
On Mon, Apr 20, 2015 at 9:35 AM, Christian Bruel christian.br...@st.com wrote:
Hello Ramana
Can you respin this now that we are in stage1 again ?
Ramana
Attached the rebased, rechecked set of patches. Original with comments
posted in
Christian
A general note, please reply to each of the patches with a rebased
patch as a separate email. Further more all your patches appear to
have dos line endings so they don't seem to apply cleanly. Please
don't have spurious headers in your patch submission - it then makes
it hard to ,
On 29/04/2015 09:24, Christian Bruel wrote:
Hi Ramana, Richard
After playing with the attritute ((target ([thumb,arm])), during the
pending review, I added the default selector to neutralize
-mflip-thumb for the setjmp/longjmp based tests.
I was wondering it there would be an interest
On Tue, Apr 28, 2015 at 4:19 PM, Martin Galvan
martin.gal...@tallertechnologies.com wrote:
This patch adds CFI directives to the soft floating point support code for
ARM.
Previously, if we tried to do a backtrace from that code in a debug session
we'd
get something like this:
(gdb) bt
On Tue, Apr 28, 2015 at 4:15 PM, Alan Lawrence alan.lawre...@arm.com wrote:
No new code here ;). There is a slight change of execution path, i.e. some
VEC_PERM_EXPRs (e.g. those for reductions via shifts) will be expanded
using
arm_expand_vec_perm_const rather than the vec_shr pattern. This
On Wed, Feb 4, 2015 at 12:12 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This patch improves the vccond patterns in neon.md to use proper RTL
operations rather than UNSPECS.
It is done in a similar way to the analogous aarch64 operations i.e. vceq is
expressed as
(neg (eq (...)
On 23/04/15 17:36, Jakub Jelinek wrote:
Hi!
This patch undoes the PR65780 performance regressions on a few targets
I have tested to work fine.
This PR was about an access to uninitialized COMMON symbol defined in
executable (or PIE) where there is a normal symbol definition in a shared
On Mon, Mar 30, 2015 at 9:25 PM, Kwok Cheung Yeung k...@codesourcery.com
wrote:
This is a simple patch that ensures that a .size directive is emitted when
space is allocated for a static variable in the BSS on bare-metal ARM
targets. This allows other tools such as GDB to look up the size of
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