RE: [PATCH] aarch64: Add backend support for expanding __builtin_memset

Hi Richard > -Original Message- > From: Richard Sandiford > Sent: 11 November 2020 17:52 > To: Sudakshina Das > Cc: Wilco Dijkstra ; gcc-patches@gcc.gnu.org; > Kyrylo Tkachov ; Richard Earnshaw > > Subject: Re: [PATCH] aarch64: Add backend support for expa

RE: [PATCH] aarch64: Add backend support for expanding __builtin_memset

Hi Richard > -Original Message- > From: Richard Sandiford > Sent: 03 November 2020 11:34 > To: Sudakshina Das > Cc: Wilco Dijkstra ; gcc-patches@gcc.gnu.org; > Kyrylo Tkachov ; Richard Earnshaw > > Subject: Re: [PATCH] aarch64: Add backend support for expa

RE: [PATCH] aarch64: Add backend support for expanding __builtin_memset

Hi Richard > -Original Message- > From: Richard Sandiford > Sent: 30 October 2020 19:56 > To: Sudakshina Das > Cc: Wilco Dijkstra ; gcc-patches@gcc.gnu.org; > Kyrylo Tkachov ; Richard Earnshaw > > Subject: Re: [PATCH] aarch64: Add backend support for expa

RE: [PATCH] aarch64: Fix PR97638

Hi Richard > -Original Message- > From: Richard Sandiford > Sent: 02 November 2020 10:31 > To: Sudakshina Das > Cc: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ; > Richard Earnshaw > Subject: Re: [PATCH] aarch64: Fix PR97638 > > Sudakshina Das write

[PATCH] aarch64: Fix PR97638

for trunk and gcc 10 backport? Thanks Sudi gcc/ChangeLog: 2020-10-30 Sudakshina Das PR target/97638 * config/aarch64/aarch64-bti-insert.c (aarch64_pac_insn_p): Update return value on INSN_P check. gcc/testsuite/ChangeLog: 2020-10-30 Sudakshina Das PR

RE: [PATCH] aarch64: Add backend support for expanding __builtin_memset

Hi Richard Thank you for the review. Please find my comments inlined. > -Original Message- > From: Richard Sandiford > Sent: 30 October 2020 15:03 > To: Sudakshina Das > Cc: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ; > Richard Earnshaw > Subject: Re: [PATCH]

[PATCH] aarch64: Add backend support for expanding __builtin_memset

for trunk? gcc/ChangeLog: 2020-xx-xx Sudakshina Das * config/aarch64/aarch64-protos.h (aarch64_expand_setmem): New declaration. * config/aarch64/aarch64.c (aarch64_gen_store_pair): Add case for E_V16QImode. (aarch64_set_one_block_and_progress_pointer): New

RE: [PATCH V2] aarch64: Use Q-reg loads/stores in movmem expansion

Sent: 05 August 2020 14:52 > To: Andreas Schwab > Cc: Sudakshina Das ; gcc-patches@gcc.gnu.org > Subject: Re: [PATCH V2] aarch64: Use Q-reg loads/stores in movmem > expansion > > Andreas Schwab writes: > > This breaks bootstrap. > > I've pushed the below to fi

RE: [PATCH V2] aarch64: Use Q-reg loads/stores in movmem expansion

Hi Richard > -Original Message- > From: Richard Sandiford > Sent: 31 July 2020 16:14 > To: Sudakshina Das > Cc: gcc-patches@gcc.gnu.org; Kyrylo Tkachov > Subject: Re: [PATCH V2] aarch64: Use Q-reg loads/stores in movmem > expansion > > Sudakshina Das writes

[PATCH V2] aarch64: Use Q-reg loads/stores in movmem expansion

code size reduction on most SPEC2017 Int benchmarks on Neoverse N1 due to more LDP/STP Q pair registers. Bootstrapped and regression tested on aarch64-none-linux-gnu. Is this ok for trunk? Thanks Sudi gcc/ChangeLog: 2020-07-23 Sudakshina Das Kyrylo Tkachov * config/aarch

RE: [PATCH] Fix handling of OPT_mgeneral_regs_only in attribute.

Hi Martin > -Original Message- > From: Martin Liška > Sent: 21 May 2020 16:01 > To: gcc-patches@gcc.gnu.org > Cc: Sudakshina Das > Subject: [PATCH] Fix handling of OPT_mgeneral_regs_only in attribute. > > Hi. > > Similarly to: > > case

[Committed, testsuite] Fix PR92870

limiting the test to the target that I know pass. Committed as obvious r279310. gcc/testsuite/ChangeLog 2019-12-12 Sudakshina Das PR testsuite/92870 * gcc.dg/vect/vect-shift-5.c: Add target to scan-tree-dump. diff --git a/gcc/testsuite/gcc.dg/vect/vect-shift-5.c b/gcc/testsuite

Re: Fwd: [PATCH, GCC, Vect] Fix costing for vector shifts

Hi Christophe On 10/12/2019 09:01, Christophe Lyon wrote: > Hi, > > On Mon, 9 Dec 2019 at 11:23, Sudakshina Das wrote: >> >> Hi Jeff >> >> On 07/12/2019 17:44, Jeff Law wrote: >>> On Fri, 2019-12-06 at 14:05 +, Sudakshina Das wrote: >>&g

Re: Fwd: [PATCH, GCC, Vect] Fix costing for vector shifts

Hi Jeff On 07/12/2019 17:44, Jeff Law wrote: > On Fri, 2019-12-06 at 14:05 +0000, Sudakshina Das wrote: >> Hi >> >> While looking at the vectorization for following example, we >> realized >> that even though vectorizable_shift function was distinguishing &g

Fwd: [PATCH, GCC, Vect] Fix costing for vector shifts

. This gives a 3.42% boost to 525.x264_r in Spec2017 for AArch64. gcc/ChangeLog: 2019-xx-xx Sudakshina Das Richard Sandiford * tree-vect-stmt.c (vectorizable_shift): Condition ndts for vect_model_simple_cost call on scalar_shift_arg. gcc/testsuite/ChangeLog: 2019-xx

Re: [Patch, GCC] Fix a condition post r278611

Hi Richard On 05/12/2019 17:04, Richard Sandiford wrote: > Sudakshina Das writes: >> Hi >> >> While looking at vect_model_reduction_cost function, it seems Richard's >> change in a recent commit r278611 missed an update to the following if >> condition. Since the

[Patch, GCC] Fix a condition post r278611

2019-xx-xx Sudakshina Das * tree-vect-loop.c (vect_model_reduction_cost): Remove reduction_type check from if condition. Is this ok for trunk? Thanks Sudi diff --git a/gcc/tree-vect-loop.c b/gcc/tree-vect-loop.c index ca8c818..7469204 100644 --- a/gcc/tree-vect-loop.c +++ b/gcc

[Committed][Arm][testsuite] Fix failure for arm-fp16-ops-*.C

Committed as obvious r278905 gcc/testsuite/ChangeLog: 2019-xx-xx Sudakshina Das * g++.dg/ext/arm-fp16/arm-fp16-ops.h: Remove volatile keyword. Thanks Sudi diff --git a/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops.h b/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops.h index 320494e..a92e

Re: [PATCH, GCC, AArch64] Fix PR88398 for AArch64

arget hook and only for a specific case​ (multiple exits).​ ​ Thanks​ Sudi From: Richard Biener Sent: Friday, November 15, 2019 9:32 AM To: Sudakshina Das Cc: gcc-patches@gcc.gnu.org ; Kyrill Tkachov ; James Greenhalgh ; Richard Earnshaw ; bin.ch...@linux.alibaba.com ; o...@ucw.cz S

[PATCH, GCC, AArch64] Fix PR88398 for AArch64

Sudakshina Das PR88398 * cfgloop.h: Include target.h. (lpt_dec): Move to... * target.h (lpt_dec): ... Here. * target.def: Define TARGET_LOOP_DECISION_ADJUST. * loop-unroll.c (decide_unroll_runtime_iterations): Use new target hook

Re: [PATCH, GCC] Fix unrolling check.

On 11/11/2019 14:50, Eric Botcazou wrote: >> Thanks for the explanation. However, I do not understand why are we >> returning with the default value. > > The regression you reported should be clear enough though: if we don't do > that, we will unroll in cases where we would not have before. Try

Re: [PATCH, GCC] Fix unrolling check.

Hi Eric On 08/11/2019 19:16, Eric Botcazou wrote: >> I was fiddling around with the loop unrolling pass and noticed a check >> in decide_unroll_* functions (in the patch). The comment on top of this >> check says >> "/* If we were not asked to unroll this loop, just return back silently. >>

[PATCH, GCC] Fix unrolling check.

not desirable? Thanks Sudi gcc/ChangeLog: 2019-11-07 Sudakshina Das * loop-unroll.c (decide_unroll_constant_iterations): Update condition to check loop->unroll. (decide_unroll_runtime_iterations): Likewise. (decide_unroll_stupid): Likewise. diff --git a/gcc

[PATCH, GCC, AArch64] Enable Transactional Memory Extension

ension-tme-intrinsics Builds and regression tested on aarch64-none-linux-gnu and added new tests for the new instructions. Is this okay for trunk? Thanks Sudi *** gcc/ChangeLog *** 2019-xx-xx Sudakshina Das * config/aarch64/aarch64-builtins.c (enum aarch64_buil

Re: [PATCH][AArch64] Make use of FADDP in simple reductions

Hi Elen Thank you for doing this. You will need a maintainer's approval but I would like to add a couple of comments. Please find them inline. On 08/05/2019 14:36, Elen Kalda wrote: > Hi, > > This patch adds a pattern to support the FADDP (scalar) instruction. > > Before the patch, the C code

RE: [PATCH, GCC, AARCH64] Add GNU note section with BTI and PAC.

Hi James -Original Message- From: James Greenhalgh Sent: 18 April 2019 09:56 To: Sudakshina Das Cc: Richard Henderson ; H.J. Lu ; Richard Henderson ; gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw ; Marcus Shawcroft ; ni...@redhat.com Subject: Re: [PATCH, GCC, AARCH64] Add GNU note

Re: [PATCH, GCC, AARCH64] Add GNU note section with BTI and PAC.

Ping. On 04/04/2019 17:01, Sudakshina Das wrote: > Hi Richard > > On 03/04/2019 11:28, Richard Henderson wrote: >> On 4/3/19 5:19 PM, Sudakshina Das wrote: >>> +  /* PT_NOTE header: namesz, descsz, type. >>> + namesz = 4 ("GNU\0") >>> +

Re: [PATCH, GCC, AARCH64] Add GNU note section with BTI and PAC.

Hi Richard On 03/04/2019 11:28, Richard Henderson wrote: > On 4/3/19 5:19 PM, Sudakshina Das wrote: >> + /* PT_NOTE header: namesz, descsz, type. >> + namesz = 4 ("GNU\0") >> + descsz = 16 (Size of the program property array) >> +

Re: [PATCH, GCC, AARCH64] Add GNU note section with BTI and PAC.

Hi Richard On 02/04/2019 10:25, Sudakshina Das wrote: > Hi > > On 02/04/2019 03:27, H.J. Lu wrote: >> On Tue, Apr 2, 2019 at 10:05 AM Richard Henderson >> wrote: >>> >>> On 4/1/19 8:53 PM, Sudakshina Das wrote: >>>>> This could stand to use

Re: [PATCH, GCC, DOCS, AArch64] Add missing documenation for mbranch-protection

Hi Sandra On 02/04/2019 16:32, Sandra Loosemore wrote: > On 4/2/19 6:45 AM, Sudakshina Das wrote: >> Hi >> >> This patch add the missing documentation bits for -mbranch-protection in >> both extend.texi and invoke.texi. >> >> Is this ok for trunk? >>

[PATCH, GCC, DOCS, AArch64] Add missing documenation for mbranch-protection

Hi This patch add the missing documentation bits for -mbranch-protection in both extend.texi and invoke.texi. Is this ok for trunk? Sudi *** gcc/ChangeLog *** 2019-xx-xx Sudakshina Das * doc/extend.texi: Add deprecated comment on sign-return-address function attribute

Re: [PATCH, GCC, AARCH64] Add GNU note section with BTI and PAC.

Hi On 02/04/2019 03:27, H.J. Lu wrote: > On Tue, Apr 2, 2019 at 10:05 AM Richard Henderson wrote: >> >> On 4/1/19 8:53 PM, Sudakshina Das wrote: >>>> This could stand to use a comment, a moment's thinking about the sizes, >>>> and to >

Re: [PATCH, wwwdocs] Mention -march=armv8.5-a and other new command line options for AArch64 and Arm for GCC 9

Hi James On 29/03/2019 13:41, Sudakshina Das wrote: > Hi James > > On 22/03/2019 16:25, James Greenhalgh wrote: >> On Wed, Mar 20, 2019 at 10:17:41AM +0000, Sudakshina Das wrote: >>> Hi Kyrill >>> >>> On 12/03/2019 12:03, Kyrill Tkachov wrote: &

Re: [PATCH, GCC, AARCH64] Add GNU note section with BTI and PAC.

Hi Richard Thanks for the comments and pointing out the much cleaner existing asm output functions! On 29/03/2019 17:51, Richard Henderson wrote: >> +#define ASM_LONG "\t.long\t" > > Do not replicate targetm.asm_out.aligned_op.si, or integer_asm_op, really. > >>

[PATCH, GCC, AARCH64] Add GNU note section with BTI and PAC.

for these in binutils are already approved and committed. https://sourceware.org/ml/binutils/2019-03/msg00072.html Bootstrapped and regression tested with aarch64-none-linux-gnu. Is this ok for trunk? Thanks Sudi *** gcc/ChangeLog *** 2018-xx-xx Sudakshina Das * config/aarch64/aarch64

Re: [PATCH, wwwdocs] Mention -march=armv8.5-a and other new command line options for AArch64 and Arm for GCC 9

Hi James On 22/03/2019 16:25, James Greenhalgh wrote: > On Wed, Mar 20, 2019 at 10:17:41AM +0000, Sudakshina Das wrote: >> Hi Kyrill >> >> On 12/03/2019 12:03, Kyrill Tkachov wrote: >>> Hi Sudi, >>> >>> On 2/22/19 10:45 AM, Sudakshina Das wrote: >

Re: [PATCH, wwwdocs] Mention -march=armv8.5-a and other new command line options for AArch64 and Arm for GCC 9

Hi Kyrill On 12/03/2019 12:03, Kyrill Tkachov wrote: > Hi Sudi, > > On 2/22/19 10:45 AM, Sudakshina Das wrote: >> Hi >> >> This patch documents the addition of the new Armv8.5-A and corresponding >> extensions in the gcc-9/changes.html. >> As per https:/

Re: [PATCH, wwwdocs] Mention -march=armv8.5-a and other new command line options for AArch64 and Arm for GCC 9

Pinging and adding Gerald to the CC list. On 22/02/2019 10:45, Sudakshina Das wrote: > Hi > > This patch documents the addition of the new Armv8.5-A and corresponding > extensions in the gcc-9/changes.html. > As per https://gcc.gnu.org/about.html, I have used W3 Validator. >

Re: [PATCH, GCC, AArch64] Fix a couple of bugs in BTI

On 21/02/2019 22:52, James Greenhalgh wrote: > On Thu, Feb 21, 2019 at 06:19:10AM -0600, Sudakshina Das wrote: >> Hi >> >> While doing more testing I found a couple of issues with my BTI patches. >> This patch fixes them: >> 1) Remove a reference to retur

[PATCH, wwwdocs] Mention -march=armv8.5-a and other new command line options for AArch64 and Arm for GCC 9

Hi This patch documents the addition of the new Armv8.5-A and corresponding extensions in the gcc-9/changes.html. As per https://gcc.gnu.org/about.html, I have used W3 Validator. Is this ok for cvs? Thanks Sudi Index: htdocs/gcc-9/changes.html

[PATCH, GCC, AArch64] Fix a couple of bugs in BTI

/ChangeLog: 2019-xx-xx Sudakshina Das * config/aarch64/aarch64.c (aarch64_output_mi_thunk): Add bti instruction if enabled. (aarch64_override_options): Remove reference to return address key. Is this ok for trunk? Sudi diff --git a/gcc/config/aarch64/aarch64.c

Re: [PATCH 2/2][GCC][ARM] Implement hint intrinsics for ARM

Hi Srinath On 10/01/19 19:20, Srinath Parvathaneni wrote: > Hi All, > > This patch implements the ACLE hint intrinsics (nop,yield,wfe,wfi,sev > and sevl), for all ARM targets. > > The intrinsics specification will be published on the Arm website [1]. > > [1] >

Re: [PATCH 1/2][GCC][AArch64] Implement hint intrinsics for AArch64

Hi Srinath On 10/01/19 19:20, Srinath Parvathaneni wrote: > Hi All, > > This patch implements the ACLE hint intrinsics (nop, yield, wfe, wfi, > sev and sevl), for AArch64. > > The instructions are documented in the ArmARM[1] and the intrinsics > specification will be > published on the Arm

[Committed, GCC, AArch64] Disable tests for ilp32.

in the tests. *** gcc/testsuite/ChangeLog *** 2019-01-10 Sudakshina Das * gcc.target/aarch64/bti-1.c: Exempt for ilp32. * gcc.target/aarch64/bti-2.c: Likewise. * gcc.target/aarch64/bti-3.c: Likewise. Only test directive change, hence only tested the above tests

Re: [PATCH, GCC, AARCH64, 5/6] Enable BTI : Add new pass for BTI.

Hi On 20/12/18 16:40, Sudakshina Das wrote: > Hi James > > On 19/12/18 3:40 PM, James Greenhalgh wrote: >> On Fri, Dec 14, 2018 at 10:09:03AM -0600, Sudakshina Das wrote: >> >> >> >>> I have updated the patch according to our discussions offline. >&

Re: [PATCH][GCC][Aarch64] Change expected bfxil count in gcc.target/aarch64/combine_bfxil.c to 18 (PR/87763)

Hi Sam On 04/01/19 10:26, Sam Tebbs wrote: > > On 12/19/18 4:47 PM, Sam Tebbs wrote: > >> Hi all, >> >> Since r265398 (combine: Do not combine moves from hard registers), the bfxil >> scan in gcc.target/aarch64/combine_bfxil.c has been failing. >> >> FAIL: gcc.target/aarch64/combine_bfxil.c

Re: Fix devirtualiation in expanded thunks

Hi Jan On 21/12/18 7:20 PM, Jan Hubicka wrote: > Hi, > this patch fixes polymorphic call analysis in thunks. Unlike normal > methods, thunks take THIS pointer offsetted by a known constant. This > needs t be compensated for when calculating address of outer type. > > Bootstrapped/regtested

Re: GCC 8 backports

Hi Martin On 27/12/18 12:32 PM, Martin Liška wrote: > On 11/20/18 11:58 AM, Martin Liška wrote: >> On 10/3/18 11:23 AM, Martin Liška wrote: >>> On 9/25/18 8:48 AM, Martin Liška wrote: Hi. One more tested patch. Martin >>> One more tested patch. >>> >>> Martin >>> >>

Re: [PATCH] PR fortran/81509 and fortran/45513

Hi Steve On 27/12/18 8:58 PM, Steve Kargl wrote: > On Thu, Dec 27, 2018 at 11:24:07AM +0000, Sudakshina Das wrote: >> With the failure as: >> >> Excess errors: >> /build/src/gcc/libgomp/testsuite/libgomp.fortran/aligned1.f03:55:14: >> Error: Arguments of 'iand' ha

Re: [PATCH] PR fortran/81509 and fortran/45513

Hi Steve On 23/12/18 6:49 PM, Steve Kargl wrote: > This is a re-submission of a patch I submitted 15 months ago. > See https://gcc.gnu.org/ml/fortran/2017-09/msg00124.html > > At that time one reviewer OK'd the patch for committing, > and one reviewer raised objections to the patch as I > chose

Re: [Committed] XFAIL gfortran.dg/ieee/ieee_9.f90

Hi On 25/12/18 5:13 PM, Steve Kargl wrote: > On Tue, Dec 25, 2018 at 09:51:03AM +0200, Janne Blomqvist wrote: >> On Mon, Dec 24, 2018 at 9:42 PM Steve Kargl < >> s...@troutmask.apl.washington.edu> wrote: >> >>> On Mon, Dec 24, 2018 at 09:29:50PM +0200, Janne Blomqvist wrote: On Mon, Dec 24,

Re: Fix devirtualization with LTO

Hi Jan On 22/12/18 8:08 PM, Jan Hubicka wrote: > Hi, > while fixing Firefox issues I also noticed that type simplification > completely disabled type based devirtualization on LTO path. Problem > is that method pointers now point to simplified type and > obj_type_ref_class is not ready for that.

Re: [PATCH] fortran/69121 -- Make IEEE_SCALB generic

Hi Steve On 21/12/18 8:01 PM, Steve Kargl wrote: > On Fri, Dec 21, 2018 at 07:39:45PM +, Joseph Myers wrote: >> On Fri, 21 Dec 2018, Steve Kargl wrote: >> >>> scalbln(double x, long n) >>> { >>> >>> return (scalbn(x, (n > NMAX) ? NMAX : (n < NMIN) ? NMIN : (int)n)); >>> } >>> >>> A

Re: [PATCH, GCC, AARCH64, 5/6] Enable BTI : Add new pass for BTI.

Hi James On 19/12/18 3:40 PM, James Greenhalgh wrote: > On Fri, Dec 14, 2018 at 10:09:03AM -0600, Sudakshina Das wrote: > > > >> I have updated the patch according to our discussions offline. >> The md pattern is now split into 4 patterns and i have added a new >

Re: [PATCH, GCC, AARCH64, 5/6] Enable BTI : Add new pass for BTI.

Hi James On 29/11/18 16:47, Sudakshina Das wrote: > Hi > > On 13/11/18 14:47, Sudakshina Das wrote: >> Hi >> >> On 02/11/18 18:38, Sudakshina Das wrote: >>> Hi >>> >>> This patch is part of a series that enables ARMv8.5-A in GCC and >&

Re: [PATCH, GCC, AARCH64, 3/6] Restrict indirect tail calls to x16 and x17

Hi On 02/11/18 18:37, Sudakshina Das wrote: > Hi > > This patch is part of a series that enables ARMv8.5-A in GCC and > adds Branch Target Identification Mechanism. > (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) > &g

Re: [PATCH, GCC, AARCH64, 5/6] Enable BTI : Add new pass for BTI.

Hi On 13/11/18 14:47, Sudakshina Das wrote: > Hi > > On 02/11/18 18:38, Sudakshina Das wrote: >> Hi >> >> This patch is part of a series that enables ARMv8.5-A in GCC and >> adds Branch Target Identification Mechanism. >> (https://developer.arm.com

Re: [PATCH, GCC, AARCH64, 6/6] Enable BTI: Add configure option for BTI and PAC-RET

Hi James On 07/11/18 15:36, James Greenhalgh wrote: > On Fri, Nov 02, 2018 at 01:38:46PM -0500, Sudakshina Das wrote: >> Hi >> >> This patch is part of a series that enables ARMv8.5-A in GCC and >> adds Branch Target Identification Mechanism. >> (https://develo

Re: [PATCH, GCC, AARCH64, 5/6] Enable BTI : Add new pass for BTI.

Hi On 02/11/18 18:38, Sudakshina Das wrote: > Hi > > This patch is part of a series that enables ARMv8.5-A in GCC and > adds Branch Target Identification Mechanism. > (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) > > This

Re: [PATCH, GCC, AARCH64, 1/6] Enable ARMv8.5-A in gcc

Hi James On 07/11/18 15:16, James Greenhalgh wrote: > On Fri, Nov 02, 2018 at 01:37:33PM -0500, Sudakshina Das wrote: >> Hi >> >> This patch is part of a series that enables ARMv8.5-A in GCC and >> adds Branch Target Identification Mechanism. >> (https://develo

Re: [PATCH 2/3][GCC][AARCH64] Add new -mbranch-protection option to combine pointer signing and BTI

Hi Sam On 02/11/18 17:31, Sam Tebbs wrote: > Hi all, > > The -mbranch-protection option combines the functionality of > -msign-return-address and the BTI features new in Armv8.5 to better reflect > their relationship. This new option therefore supersedes and deprecates the > existing

Re: [PATCH, GCC, ARM] Enable armv8.5-a and add +sb and +predres for previous ARMv8-a in ARM

Hi Kyrill On 09/11/18 18:21, Kyrill Tkachov wrote: > Hi Sudi, > > On 09/11/18 15:33, Sudakshina Das wrote: >> Hi >> >> This patch adds -march=armv8.5-a to the Arm backend. >> (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration

[PATCH, GCC, AArch64] Branch Dilution Pass

Hi I am posting this patch on behalf of Carey (cc'ed). I also have some review comments that I will make as a reply to this later. This implements a new AArch64 specific back-end pass that helps optimize branch-dense code, which can be a bottleneck for performance on some Arm cores. This is

[PATCH, GCC, ARM] Enable armv8.5-a and add +sb and +predres for previous ARMv8-a in ARM

tested with arm-none-linux-gnueabihf. Is this ok for trunk? Sudi *** gcc/ChangeLog *** 2018-xx-xx Sudakshina Das * config/arm/arm-cpus.in (armv8_5, sb, predres): New features. (ARMv8_5a): New fgroup. (armv8.5-a): New arch. (armv8-a, armv8.1-a, armv8.2-a, armv8.

Re: [PATCH, arm] Backport -- Fix ICE during thunk generation with -mlong-calls

Hi Mihail On 08/11/18 10:02, Ramana Radhakrishnan wrote: > On 07/11/2018 17:49, Mihail Ionescu wrote: >> Hi All, >> >> This is a backport from trunk for GCC 8 and 7. >> >> SVN revision: r264595. >> >> Regression tested on arm-none-eabi. >> >> >> gcc/ChangeLog >> >> 2018-11-02 Mihail Ionescu >>

Re: [PATCH, GCC, AARCH64, 1/6] Enable ARMv8.5-A in gcc

Hi On 02/11/18 18:37, Sudakshina Das wrote: > Hi > > This patch is part of a series that enables ARMv8.5-A in GCC and > adds Branch Target Identification Mechanism. > (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) > >

[PATCH, GCC, AARCH64, 6/6] Enable BTI: Add configure option for BTI and PAC-RET

with and without configure option with a BTI enabled aem. Only 2 regressions and these were because newlib requires patches to protect hand coded libraries with BTI. Is this ok for trunk? Thanks Sudi *** gcc/ChangeLog *** 2018-xx-xx Sudakshina Das * config/aarch64/aarch64.c

[PATCH, GCC, AARCH64, 4/6] Enable BTI: Add new to -mbranch-protection.

ti to 2 since I am also adding a configure option in a later patch and a value different from 0 and 1 would help identify if its already been updated. Bootstrapped and regression tested with aarch64-none-linux-gnu. Is this ok for trunk? Thanks Sudi *** gcc/ChangeLog *** 2018-xx-xx Sudakshina D

[PATCH, GCC, AARCH64, 5/6] Enable BTI : Add new pass for BTI.

e we have already changed the use of indirect tail calls to only x16 and x17, we do not have to use "BTI JC". (check patch 3/6). Bootstrapped and regression tested with aarch64-none-linux-gnu. Added new tests. Is this ok for trunk? Thanks Sudi *** gcc/ChangeLog *** 2

[PATCH, GCC, AARCH64, 3/6] Restrict indirect tail calls to x16 and x17

*** gcc/ChangeLog*** 2018-xx-xx Sudakshina Das * config/aarch64/aarch64.c (aarch64_expand_prologue): Use new epilogue/prologue scratch registers EP0_REGNUM and EP1_REGNUM. (aarch64_expand_epilogue): Likewise. (aarch64_output_mi_thunk): Likewise

[PATCH, GCC, AARCH64, 2/6] Add new arch command line feaures from ARMv8.5-A

instructions. All of the above only effect the assembler and have already (or almost for a couple of cases) gone in the trunk of binutils. Bootstrapped and regression tested with aarch64-none-linux-gnu. Is this ok for trunk? Thanks Sudi *** gcc/ChangeLog *** 2018-xx-xx Sudakshina Das

[PATCH, GCC, AARCH64, 1/6] Enable ARMv8.5-A in gcc

with aarch64-none-linux-gnu. Is this ok for trunk? Thanks Sudi *** gcc/ChangeLog *** 2018-xx-xx Sudakshina Das * config/aarch64/aarch64-arches.def: Define AARCH64_ARCH for ARMv8.5-A. * gcc/config/aarch64/aarch64.h (AARCH64_FL_V8_5): New. (AARCH64_FL_FOR_ARCH8_5

Re: [PATCH][GCC][AArch64] Limit movmem copies to TImode copies.

Hi Tamar On 13/08/18 17:27, Tamar Christina wrote: Hi Thomas, Thanks for the review. I’ll correct the typo before committing if I have no other changes required by a maintainer. Regards, Tamar. I am not a maintainer but I would like to point out something in your patch. I think you test

Re: [PATCH][GCC][AARCH64] Use STLUR for atomic_store

Hi Matthew On 02/08/18 17:26, matthew.malcom...@arm.com wrote: Use the STLUR instruction introduced in Armv8.4-a. This insruction has the store-release semantic like STLR but can take a 9-bit unscaled signed immediate offset. Example test case: ``` void foo () { int32_t *atomic_vals =

Re: [PATCH][GCC] Correct name of file in ChangeLog

Hi Matthew On 01/08/18 10:25, matthew.malcom...@arm.com wrote: My first patch included an incorrect ChangeLog entry -- the filename was misspelt. This corrects it. I think this counts as an obvious change. I have committed this on your behalf. Thanks Sudi

Re: [PATCH][AARCH64] PR target/84521 Fix frame pointer corruption with -fomit-frame-pointer with __builtin_setjmp

Hi On 31/07/18 22:48, Andrew Pinski wrote: On Tue, Jul 31, 2018 at 2:43 PM James Greenhalgh wrote: On Thu, Jul 12, 2018 at 12:01:09PM -0500, Sudakshina Das wrote: Hi Eric On 27/06/18 12:22, Wilco Dijkstra wrote: Eric Botcazou wrote: This test can easily be changed not to use optimize

Re: [GCC][PATCH][Aarch64] Stop redundant zero-extension after UMOV when in DI mode

Hi Sam On 01/08/18 10:12, Sam Tebbs wrote: On 07/31/2018 11:16 PM, James Greenhalgh wrote: On Thu, Jul 26, 2018 at 11:52:15AM -0500, Sam Tebbs wrote: Thanks for making the changes and adding more test cases. I do however see that you are only covering 2 out of 4 new

Re: [GCC][PATCH][Aarch64] Stop redundant zero-extension after UMOV when in DI mode

Hi Sam On 25/07/18 14:08, Sam Tebbs wrote: On 07/23/2018 05:01 PM, Sudakshina Das wrote: Hi Sam On Monday 23 July 2018 11:39 AM, Sam Tebbs wrote: Hi all, This patch extends the aarch64_get_lane_zero_extendsi instruction definition to also cover DI mode. This prevents a redundant

Re: [GCC][PATCH][Aarch64] Stop redundant zero-extension after UMOV when in DI mode

Hi Sam On 25/07/18 14:08, Sam Tebbs wrote: On 07/23/2018 05:01 PM, Sudakshina Das wrote: Hi Sam On Monday 23 July 2018 11:39 AM, Sam Tebbs wrote: Hi all, This patch extends the aarch64_get_lane_zero_extendsi instruction definition to also cover DI mode. This prevents a redundant

Re: [PATCH][AArch64] Implement new intrinsics vabsd_s64 and vnegd_s64

Hi Vlad On Friday 20 July 2018 10:37 AM, Vlad Lazar wrote: Hi, The patch adds implementations for the NEON intrinsics vabsd_s64 and vnegd_s64.

Re: [GCC][PATCH][Aarch64] Stop redundant zero-extension after UMOV when in DI mode

Hi Sam On Monday 23 July 2018 11:39 AM, Sam Tebbs wrote: Hi all, This patch extends the aarch64_get_lane_zero_extendsi instruction definition to also cover DI mode. This prevents a redundant AND instruction from being generated due to the pattern failing to be matched. Example: typedef

Re: [GCC][PATCH][Aarch64] Exploiting BFXIL when OR-ing two AND-operations with appropriate bitmasks

Hi Sam On 13/07/18 17:09, Sam Tebbs wrote: Hi all, This patch adds an optimisation that exploits the AArch64 BFXIL instruction when or-ing the result of two bitwise and operations with non-overlapping bitmasks (e.g. (a & 0x) | (b & 0x)). Example: unsigned long long

Re: [PATCH][AARCH64] PR target/84521 Fix frame pointer corruption with -fomit-frame-pointer with __builtin_setjmp

Hi Eric On 27/06/18 12:22, Wilco Dijkstra wrote: Eric Botcazou wrote: This test can easily be changed not to use optimize since it doesn't look like it needs it. We really need to tests these builtins properly, otherwise they will continue to fail on most targets. As far as I can see PR

Re: [PATCH][GCC][AARCH64] Canonicalize aarch64 widening simd plus insns

Hi Matthew On 12/07/18 11:18, Richard Sandiford wrote: Looks good to me FWIW (not a maintainer), just a minor formatting thing: Matthew Malcomson writes: diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index

Re: [AArch64] Generate load-pairs when the last load clobbers the address register [2/2]

Hi Jackson On 11/07/18 17:48, Jackson Woodruff wrote: Hi Sudi, On 07/10/2018 02:29 PM, Sudakshina Das wrote: Hi Jackson On Tuesday 10 July 2018 09:37 AM, Jackson Woodruff wrote: Hi all, This patch resolves PR86014.  It does so by noticing that the last load may clobber the address

Re: [AArch64] Use arrays and loops rather than numbered variables in aarch64_operands_adjust_ok_for_ldpstp [1/2]

Hi Jackson On 11/07/18 17:48, Jackson Woodruff wrote: Hi Sudi, Thanks for the review. On 07/10/2018 10:56 AM, Sudakshina wrote: Hi Jackson -  if (!MEM_P (mem_1) || aarch64_mem_pair_operand (mem_1, mode)) +  if (!MEM_P (mem[1]) || aarch64_mem_pair_operand (mem[1], mode)) mem_1 == mem[1]?

Re: [AArch64] Generate load-pairs when the last load clobbers the address register [2/2]

Hi Jackson On Tuesday 10 July 2018 09:37 AM, Jackson Woodruff wrote: Hi all, This patch resolves PR86014.  It does so by noticing that the last load may clobber the address register without issue (regardless of where it exists in the final ldp/stp sequence).  That check has been changed so

Re: [PATCH][AARCH64] PR target/84521 Fix frame pointer corruption with -fomit-frame-pointer with __builtin_setjmp

PING! On 14/06/18 12:10, Sudakshina Das wrote: Hi Eric On 07/06/18 16:33, Eric Botcazou wrote: Sorry this fell off my radar. I have reg-tested it on x86 and tried it on the sparc machine from the gcc farm but I think I couldn't finished the run and now its showing to he unreachable

Re: [PATCH][AARCH64] PR target/84521 Fix frame pointer corruption with -fomit-frame-pointer with __builtin_setjmp

/pr84521.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects execution test Testing: Bootstrapped and regtested on aarch64-none-linux-gnu. Is this ok for trunk? Sudi *** gcc/ChangeLog *** 2018-06-14 Sudakshina Das PR target/84521 * config/aarch64/aarch64.h

Re: [PATCH][AARCH64] PR target/84521 Fix frame pointer corruption with -fomit-frame-pointer with __builtin_setjmp

On 02/05/18 18:28, Jeff Law wrote: On 03/14/2018 11:40 AM, Sudakshina Das wrote: Hi This patch is another partial fix for PR 84521. This is adding a definition to one of the target hooks used in the SJLJ implemetation so that AArch64 defines the hard_frame_pointer_rtx

Re: C++ PATCHes to xvalue handling

On 23/05/18 18:21, Jason Merrill wrote: The first patch implements the adjustments from core issues 616 and 1213 to the value category of subobjects of class prvalues: they were considered prvalues themselves, but that was kind of nonsensical. Now they are considered xvalues. Along with this,

Re: [PATCH][RFC] Radically simplify emission of balanced tree for switch statements.

Hi Martin On 25/05/18 10:45, Martin Liška wrote: On 05/21/2018 04:42 PM, Sudakshina Das wrote: On 21/05/18 15:00, Rainer Orth wrote: Hi Martin, Thanks for opened eyes, following patch will fix that. It's quite obvious, I'll install it right after tests will finish. unfortunately

Re: [PATCH][AARCH64][PR target/84882] Add mno-strict-align

Hi Richard On 18/05/18 15:48, Richard Earnshaw (lists) wrote: On 27/03/18 13:58, Sudakshina Das wrote: Hi This patch adds the no variant to -mstrict-align and the corresponding function attribute. To enable the function attribute, I have modified aarch64_can_inline_p () to allow checks even

Re: [PATCH][RFC] Radically simplify emission of balanced tree for switch statements.

On 21/05/18 15:00, Rainer Orth wrote: Hi Martin, Thanks for opened eyes, following patch will fix that. It's quite obvious, I'll install it right after tests will finish. unfortunately, it didn't fix either issue: * The switchlower -> switchlower1 renames in the dg-final* lines

Re: [PATCH][AARCH64][PR target/84882] Add mno-strict-align

Ping! On 27/03/18 13:58, Sudakshina Das wrote: Hi This patch adds the no variant to -mstrict-align and the corresponding function attribute. To enable the function attribute, I have modified aarch64_can_inline_p () to allow checks even when the callee function has no attribute. The need

Re: [AARCH64] Neon vld1_*_x3, vst1_*_x2 and vst1_*_x3 intrinsics

Hi Sameera On 11/04/18 13:05, Sameera Deshpande wrote: On 11 April 2018 at 15:53, Sudakshina Das <sudi@arm.com> wrote: Hi Sameera On 11/04/18 09:04, Sameera Deshpande wrote: On 10 April 2018 at 20:07, Sudakshina Das <sudi@arm.com> wrote: Hi Sameera On 10/04/18 11

Re: [AARCH64] Neon vld1_*_x3, vst1_*_x2 and vst1_*_x3 intrinsics

Hi Sameera On 11/04/18 09:04, Sameera Deshpande wrote: On 10 April 2018 at 20:07, Sudakshina Das <sudi@arm.com> wrote: Hi Sameera On 10/04/18 11:20, Sameera Deshpande wrote: On 7 April 2018 at 01:25, Christophe Lyon <christophe.l...@linaro.org> wrote: Hi, 2018-04-06 12:

Re: [AARCH64] Neon vld1_*_x3, vst1_*_x2 and vst1_*_x3 intrinsics

Hi Sameera On 10/04/18 11:20, Sameera Deshpande wrote: On 7 April 2018 at 01:25, Christophe Lyon wrote: Hi, 2018-04-06 12:15 GMT+02:00 Sameera Deshpande : Hi Christophe, Please find attached the updated patch with testcases. Ok for

Re: [Aarch64] Fix conditional branches with target far away.

testcase. Ok for trunk? Thank you so much for fixing the length as well along with you patch. You mention a failing testcase? Maybe it would be helpful to add that to the patch for the gcc testsuite. Sudi On 22 March 2018 at 19:06, Sudakshina Das <sudi@arm.com> wrote: Hi Sameera On 22

Re: [PATCH, GCC-7, GCC-6][ARM][PR target/84826] Backport Fix ICE in extract_insn, at recog.c:2304 on arm-linux-gnueabihf

Hi Kyrill On 29/03/18 09:41, Kyrill Tkachov wrote: Hi Sudi, On 28/03/18 15:04, Sudakshina Das wrote: Hi This patch is a request to backport r258777 and r258805 to gcc-7-branch and gcc-6-branch. The same ICE occurs in both the branches with -fstack-check. Thus the test case directive has been

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