Re: [PATCH, rs6000] 3/3 Add x86 SSE intrinsics to GCC PPC64LE taget

On Wed, Aug 16, 2017 at 03:50:55PM -0500, Steven Munroe wrote: > This it part 3/3 for contributing PPC64LE support for X86 SSE > instrisics. This patch includes testsuite/gcc.target tests for the > intrinsics included by xmmintrin.h. > +#define CHECK_EXP(UINON_TYPE, VALUE_TYPE, FMT)

Re: [PATCH, rs6000] 2/3 Add x86 SSE intrinsics to GCC PPC64LE taget

Hi! On Wed, Aug 16, 2017 at 03:35:40PM -0500, Steven Munroe wrote: > +extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, > __artificial__)) > +_mm_add_ss (__m128 __A, __m128 __B) > +{ > +#ifdef _ARCH_PWR7 > + __m128 a, b, c; > + static const __vector unsigned int mask =

Ping on target independent stack clash protection patches

#01 of #08: https://gcc.gnu.org/ml/gcc-patches/2017-07/msg01971.html #02 of #08: https://gcc.gnu.org/ml/gcc-patches/2017-07/msg01972.html #03 of #08: https://gcc.gnu.org/ml/gcc-patches/2017-07/msg01974.html Need to reach some kind of closure on these, then I can start pinging the target

Re: GCC 7.2 Released

> The GNU Compiler Collection version 7.2 has been released. Shouldn't the release have a tag on git? It doesn't seem to be there: https://gcc.gnu.org/git/?p=gcc.git;a=tags git tag gcc-7_2_0-release 1bd23ca8c30f4827c4bea23deedf7ca33a86ffb5 BR, Klaus > > GCC 7.2 is a bug-fix release from

[Bug target/81709] __attribute__((interrupt)) should handle SSE registers

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81709 --- Comment #3 from H.J. Lu --- (In reply to Anatol from comment #2) > Theoretically it is possible to do things like this manually. Track > functions x86 extensions usage and save registers accordingly. But I would > love to see a more

[Bug c++/81873] spurious -Wreturn-type calling a locally declared noreturn function

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81873 --- Comment #2 from Andrew Pinski --- This is not so much an -Wreturn-type issue but a symptom of the C++ front-end not merging decls for globals. You filed a few other cases which are accepts invalid which are the same here.

[PATCH 5/3] C++ bits to improve detection of attribute conflicts (PR 81544)

To make review easier I broke out the C++ changes for the attributes work into a patch of their own. I also found the API I had asked about, to look up a declaration based on one that's about to be added/merged. This patch depends on the foundation bits posted here:

[Bug target/81709] __attribute__((interrupt)) should handle SSE registers

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81709 --- Comment #2 from Anatol --- Theoretically it is possible to do things like this manually. Track functions x86 extensions usage and save registers accordingly. But I would love to see a more automated and less error-prone way to do it. Similar

[Bug c++/81855] [mingw-w64] dllexport-ed explicit template instantiation has no symbol in DLL in certain condition

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81855 --- Comment #2 from Xingcan Lan --- Checked diassembly code and found that __declspec(dllexport) never applied to explicitly instantiated `Template`. If I change the code from `extern template struct __declspec(dllexport) Template;` to `extern

Re: [RS6000] PR 80938, Don't emit eh_frame for regs that don't need saving

On Thu, Aug 17, 2017 at 11:25:27AM +0930, Alan Modra wrote: > On Wed, Aug 16, 2017 at 06:23:13PM -0500, Segher Boessenkool wrote: > > Maybe whatever is creating those instructions should set RTX_FRAME_RELATED_P > > by itself? Not sure if that is nicer. > > > > Both this CR2 and R0 handling are

Release Signing Keys are Susceptible to Attack

After downloading and verifying the releases on ftp://ftp.gnu.org/gnu/, I found that the maintainers used 1024 bit DSA keys with SHA1 content digests. 1024 bit keys are considered to be susceptible to realistic attacks, and SHA1 has been considered broken for some time.

[Bug target/80938] [7/8 Regression] ICE in maybe_record_trace_start, at dwarf2cfi.c:2330

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80938 --- Comment #6 from Alan Modra --- Author: amodra Date: Thu Aug 17 02:03:03 2017 New Revision: 251140 URL: https://gcc.gnu.org/viewcvs?rev=251140=gcc=rev Log: [RS6000] PR 80938, Don't emit frame info for regs that don't need saving It is

Re: [RS6000] PR 80938, Don't emit eh_frame for regs that don't need saving

On Wed, Aug 16, 2017 at 06:23:13PM -0500, Segher Boessenkool wrote: > Hi! > > On Wed, Aug 16, 2017 at 08:05:04AM +0930, Alan Modra wrote: > > Repost with requested changes. I've extracted the logic that omits > > frame saves from rs6000_frame_related to a new function, because it's > > easier to

Re: How to migrate ggc_alloc_XXX for GCC v8.x (git-20170816)?

for tree2WeakVH https://github.com/xiangzhai/dragonegg/blob/master/include/dragonegg/gt-cache-4.6.inc#L24 but gengtype will not auto-generate ggc_alloc_XXX for GCC v6.x or v8.x (git-20170816), for example: struct GTY((for_user)) tree2WeakVH https://github.com/xiangzhai/dragonegg/blob/master/include/dragonegg

[Bug target/81317] builtin_vec_ld fails for powerpc with altivec

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81317 --- Comment #24 from Randy MacLeod --- This ICE still happens with gcc-7.2. Here's the stacktrace: (gdb) bt #0 store_expr_with_bounds (exp=exp@entry=0x76275900, target=target@entry=0x7625d660, call_param_p=call_param_p@entry=0,

Re: [PATCH, rs6000] Fix PR target/72804: Poor code gen with -mvsx-timode

On Wed, Aug 16, 2017 at 05:56:09PM -0500, Peter Bergner wrote: > On 8/16/17 5:30 PM, Segher Boessenkool wrote: > > On Mon, Aug 14, 2017 at 04:28:25PM -0500, Peter Bergner wrote: > >> + mr %0,%L1; mr %L0,%1 > > > >mr %0,%L1\;mr %L0,%1 > > So you want the ';' escaped and the space removed?

Re: [PATCH, rs6000] 1/3 Add x86 SSE <xmmintrin,h> intrinsics to GCC PPC64LE taget

Hi! On Wed, Aug 16, 2017 at 02:11:31PM -0500, Steven Munroe wrote: > These is the third major contribution of X86 intrinsic equivalent > headers for PPC64LE. > This patch just adds the mm_malloc.h header with is will be needed by > xmmintrin.h and cleans up some noisy warnings from the previous

Re: Overwhelmed by GCC frustration

On Wed, Aug 16, 2017 at 11:23:27PM +0900, Oleg Endo wrote: > > First of all, LRA cannot cope with cc0 (Yes, I know deprecating > > cc0 is just to deprecate all non-LRA BEs).  LRA asserts that > > accessing the frame doesn't change condition code. LRA doesn't > > provide replacement for

[Bug c++/81873] spurious -Wreturn-type calling a locally declared noreturn function

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81873 Martin Sebor changed: What|Removed |Added Keywords||diagnostic See Also|

[Bug c++/81873] New: spurious -Wreturn-type calling a locally declared noreturn function

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81873 Bug ID: 81873 Summary: spurious -Wreturn-type calling a locally declared noreturn function Product: gcc Version: 8.0 Status: UNCONFIRMED Severity: normal

Re: Redundant loads for bitfield accesses

When implementing the RISC-V port, I took the name of this macro at face value. It does seem that we should follow Andrew's advice and set it to 1. (For your examples, doing so does improve code generation.) We'll submit a patch if the change doesn't regress. On Wed, Aug 16, 2017 at 4:00 PM,

[Bug tree-optimization/81488] [8 Regression] gcc goes off the limits allocating memory in gimple-ssa-strength-reduction.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81488 --- Comment #5 from Bill Schmidt --- Just for the record, the problem disappears with r250523, in which a change to reassociation of multiplication in match.pd causes the SLSR opportunities to disappear. So the SLSR problem has just gone

Re: [RS6000] PR 80938, Don't emit eh_frame for regs that don't need saving

Hi! On Wed, Aug 16, 2017 at 08:05:04AM +0930, Alan Modra wrote: > Repost with requested changes. I've extracted the logic that omits > frame saves from rs6000_frame_related to a new function, because it's > easier to document that way. The logic has been simplified a little > too: fixed_reg_p

[PATCH], Enable -mfloat128 by default on PowerPC VSX systems

This patch enables -mfloat128 to be the default on PowerPC Linux VSX systems. This patch depends on the libquadmatch/81848 patch being approved and installed: https://gcc.gnu.org/ml/gcc-patches/2017-08/msg00977.html In this patch, I removed the old undocumented -mfloat128-type switch, and made

Re: [PATCH, rs6000] Fix endianness issue with vmrgew and vmrgow permute constant recognition

Hi! On Tue, Aug 15, 2017 at 04:14:21PM -0500, Bill Schmidt wrote: > One of Carl Love's proposed built-in function patches exposed a bug in the > Power > code that recognizes specific permute control vector patterns for a permute, > and > changes the permute to a more specific and more efficient

Re: [PATCH, rs6000] Fix PR target/72804: Poor code gen with -mvsx-timode

On 8/16/17 5:30 PM, Segher Boessenkool wrote: > On Mon, Aug 14, 2017 at 04:28:25PM -0500, Peter Bergner wrote: >> + mr %0,%L1; mr %L0,%1 > >mr %0,%L1\;mr %L0,%1 So you want the ';' escaped and the space removed? Ok. >> + [(set (match_operand:VSX_TI 0 "int_reg_operand" "") > > You

Re: Redundant loads for bitfield accesses

> On 17 Aug 2017, at 10:41 AM, Andrew Pinski wrote: > > On Wed, Aug 16, 2017 at 3:29 PM, Michael Clark wrote: >> Hi, >> >> Is there any reason for 3 loads being issued for these bitfield accesses, >> given two of the loads are bytes, and one is a

gcc-6-20170816 is now available

Snapshot gcc-6-20170816 is now available on ftp://gcc.gnu.org/pub/gcc/snapshots/6-20170816/ and on various mirrors, see http://gcc.gnu.org/mirrors.html for details. This snapshot has been generated from the GCC 6 SVN branch with the following options: svn://gcc.gnu.org/svn/gcc/branches/gcc-6

Re: [PATCH, rs6000] Remove TARGET_VSX_TIMODE and -mno-vsx-timode usage

On Mon, Aug 14, 2017 at 06:02:51PM -0500, Peter Bergner wrote: > The undocumented option -mvsx-timode was added because there were reload > bugs we couldn't fix when we tried allowing TImode values in VSX registers. > We used the option to allow TImode values in VSX registers when LRA was > being

[Bug target/81863] [7 regression] -mword-relocations is unreliable

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81863 Arnd Bergmann changed: What|Removed |Added Known to work|6.3.1 | --- Comment #1 from Arnd Bergmann ---

Re: Redundant loads for bitfield accesses

On Wed, Aug 16, 2017 at 3:29 PM, Michael Clark wrote: > Hi, > > Is there any reason for 3 loads being issued for these bitfield accesses, > given two of the loads are bytes, and one is a half; the compiler appears to > know the structure is aligned at a half word

Re: Redundant loads for bitfield accesses

Here’s a more extreme example: - https://cx.rv8.io/g/2HWQje The bitfield type is unsigned int, so one or two 32-bit loads should suffice (depending on register pressure). GCC is issuing a lw at some point in the asm. struct foo { unsigned int a : 3; unsigned int b : 3; unsigned int c :

[PATCH 4/3] improve detection of attribute conflicts (PR 81544)

Jon, Attached is the libstdc++ only patch to remove the pointless const attribute from __pool::_M_destroy_thread_key(void*). https://gcc.gnu.org/ml/gcc/2017-08/msg00027.html I only belatedly now broke it out of the larger patch under review here:

Re: [PATCH, rs6000] Fix PR target/72804: Poor code gen with -mvsx-timode

On Mon, Aug 14, 2017 at 04:28:25PM -0500, Peter Bergner wrote: > The following patch fixes a performance issue when loading/storing/moving > TImode values when using -mvsx-timode -mcpu=power7 with LRA. The problem is > that the vsx_le_permute_ and vsx_le_perm_{load,store}_ patterns > do no

Redundant loads for bitfield accesses

Hi, Is there any reason for 3 loads being issued for these bitfield accesses, given two of the loads are bytes, and one is a half; the compiler appears to know the structure is aligned at a half word boundary. Secondly, the riscv code is using a mixture of 32-bit and 64-bit adds and shifts.

Re: [PATCH], Enable _Float128 in VSX PowerPC system and enable #pragma GCC target "float128"

Hi Mike, On Mon, Aug 14, 2017 at 03:21:42PM -0400, Michael Meissner wrote: > This patch enables the _Float128 keyword for the C langauge all of the time > for > PowerPC VSX systems. The __float128 keyword continues to be only enabled if > you use the -mfloat128 option. Looks good, please

[Bug bootstrap/81869] [8 Regression] --enable-checking=yes,rtl failed to bootstrap on 32-bit hosts

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81869 --- Comment #4 from H.J. Lu --- It doesn't happen with the preprocessed source.

[Bug target/81872] Enable __float128 by default on PowerPC Linux systems

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81872 Michael Meissner changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Last reconfirmed|

[Bug target/81872] New: Enable __float128 by default on PowerPC Linux systems

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81872 Bug ID: 81872 Summary: Enable __float128 by default on PowerPC Linux systems Product: gcc Version: 8.0 Status: UNCONFIRMED Severity: enhancement Priority: P3

Re: Overwhelmed by GCC frustration

On Wed, Aug 16, 2017 at 03:53:24PM +0200, Georg-Johann Lay wrote: > This means it's actually waste of time to work on these backends. The > code will finally end up in the dustbin as cc0 backends are considered > undesired ballast that has to be "jettisoned". > > "Deprecate all cc0" is just a

[Bug bootstrap/81869] [8 Regression] --enable-checking=yes,rtl failed to bootstrap on 32-bit hosts

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81869 --- Comment #3 from H.J. Lu --- (In reply to H.J. Lu from comment #2) > On 64-bit hosts, I got > > (gdb) p cfun->cfg->x_last_basic_block > $1 = 432 > (gdb) call debug_tree (cfun->decl) Please ignore this. I didn't use --enable-checking=yes,rtl

[Bug bootstrap/81869] [8 Regression] --enable-checking=yes,rtl failed to bootstrap on 32-bit hosts

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81869 H.J. Lu changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug sanitizer/81870] -fsanitize=undefined doesn't pay attention to __builtin_assume_aligned()

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81870 --- Comment #2 from Petr --- I see, so if I understand it correctly then: 1. `__builtin_assume_aligned()` should be used to promote the type to a higher than natural alignment, for example 16 bytes for easier auto-vectorization. 2.

[Bug tree-optimization/81488] [8 Regression] gcc goes off the limits allocating memory in gimple-ssa-strength-reduction.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81488 --- Comment #4 from Bill Schmidt --- With a cross it doesn't reproduce for current trunk (r251128) either, but does reproduce with r250217 as originally reported. So I can look at that. Going to check what made the problem go away also...

libgo patch committed: improvements for AIX netpoll

This patch by Tony Reix improves the AIX netpoll code used by libgo. Bootstrapped on x86_64-pc-linux-gnu. Committed to mainline. Ian Index: gcc/go/gofrontend/MERGE === --- gcc/go/gofrontend/MERGE (revision 251127) +++

Re: How to Verify GNU Releases

On Wed, Aug 16, 2017 at 3:53 PM, R0b0t1 wrote: > Hello, > > I have no problem working GnuPG. However, files on ftp://ftp.gnu.org > are signed by individuals, at least for the projects I am interested > in (binutils, gcc, gdb). Where might I find a GNU's endorsement of the >

Re: [PATCH] use strnlen in pretty printer for "%.*s" (PR 81859)

On Wed, 2017-08-16 at 10:12 -0600, Martin Sebor wrote: > PR c/81859 - [8 Regression] valgrind error from > warn_about_normalization > > gcc/ChangeLog: > > PR c/81859 > * pretty-print.c (pp_format): Use strnlen in %.*s to avoid > reading > past the end of an array. >

How to Verify GNU Releases

Hello, I have no problem working GnuPG. However, files on ftp://ftp.gnu.org are signed by individuals, at least for the projects I am interested in (binutils, gcc, gdb). Where might I find a GNU's endorsement of the signers? I started another thread about a related issue, my apologies if I

[PATCH, rs6000] 3/3 Add x86 SSE intrinsics to GCC PPC64LE taget

This it part 3/3 for contributing PPC64LE support for X86 SSE instrisics. This patch includes testsuite/gcc.target tests for the intrinsics included by xmmintrin.h. For these tests I added -Wno-psabi to dg-options to suppress warnings associated with the vector ABI change in GCC5. These warning

[Bug target/81861] [8.0 Regression] ASan pr64820.c testcase segfaults with LTO and -fstack-protector-strong

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81861 Uroš Bizjak changed: What|Removed |Added Component|lto |target --- Comment #7 from Uroš Bizjak

[PATCH, rs6000] 2/3 Add x86 SSE intrinsics to GCC PPC64LE taget

This it part 2/3 for contributing PPC64LE support for X86 SSE instrisics. This patch includes the new (for PPC) xmmintrin.h and associated config.gcc changes. This submission implements all the SSE Technology intrinsic functions except those associated with directly accessing and updating the MX

[Bug sanitizer/81870] -fsanitize=undefined doesn't pay attention to __builtin_assume_aligned()

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81870 Andrew Pinski changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[PATCH] Move TYPE_BINFO

My excision of TYPE_METHODS frees up the TYPE_MAX_VALUES_RAW slot in RECORD_TYPEs. This patch moves TYPE_BINFO to there. That move frees up type_non_common::binfo, which I rename to type_non_common::lang_1 and adjust TYPE_LANG_SLOT_1 to allow any type slot to use it. TYPE_LANG_SLOT_1 is

[Bug c/78666] conflicting attribute alloc_size accepted

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78666 Martin Sebor changed: What|Removed |Added See Also||https://gcc.gnu.org/bugzill

[Bug c/81871] New: bogus attribute alloc_align accepted

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81871 Bug ID: 81871 Summary: bogus attribute alloc_align accepted Product: gcc Version: 8.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: c

[Bug bootstrap/81869] [8 Regression] --enable-checking=yes,rtl failed to bootstrap on 32-bit hosts

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81869 --- Comment #1 from H.J. Lu --- On 64-bit host, I got Number of expanded macros: 25177 Average number of tokens per macro expansion: 34 Line Table allocations during the compilation process Number of ordinary maps used:

[Bug sanitizer/81870] New: -fsanitize=undefined doesn't pay attention to __builtin_assume_aligned()

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81870 Bug ID: 81870 Summary: -fsanitize=undefined doesn't pay attention to __builtin_assume_aligned() Product: gcc Version: 7.1.0 Status: UNCONFIRMED Severity:

[Bug c/78666] conflicting attribute alloc_size accepted

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78666 --- Comment #7 from Martin Sebor --- The following nonsensical declaration is also not diagnosed: void __attribute__ ((alloc_align (1))) f (void*); The attribute handler should check that the referenced argument has integer type and that the

Re: Should --enable-checking=yes,rtl work on 32-bit hosts?

On Tue, Aug 15, 2017 at 5:43 PM, Daniel Santos wrote: > On 08/15/2017 06:18 AM, Richard Biener wrote: >> On Mon, Aug 14, 2017 at 5:23 PM, H.J. Lu wrote: >>> For GCC 8, when --enable-checking=yes,rtl is used with x32 GCC, >>> I got >>> >>> cc1plus:

[Bug bootstrap/81869] New: [8 Regression] --enable-checking=yes,rtl failed to bootstrap on 32-bit hosts

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81869 Bug ID: 81869 Summary: [8 Regression] --enable-checking=yes,rtl failed to bootstrap on 32-bit hosts Product: gcc Version: 8.0 Status: UNCONFIRMED Severity:

[PATCH, rs6000] 1/3 Add x86 SSE <xmmintrin,h> intrinsics to GCC PPC64LE taget

These is the third major contribution of X86 intrinsic equivalent headers for PPC64LE. X86 SSE technology was the second SIMD extension which added wider 128-bit vector (XMM) registers and single precision float capability. They also addressed missing MMX capabilies and provided transfers (move,

[committed] diagnostic-show-locus.c: remove unused field from class colorizer

Successfully bootstrapped on x86_64-pc-linux-gnu. Committed to trunk as r251128. gcc/ChangeLog: * diagnostic-show-locus.c (colorizer::m_caret): Remove unused field. --- gcc/diagnostic-show-locus.c | 1 - 1 file changed, 1 deletion(-) diff --git a/gcc/diagnostic-show-locus.c

libgo patch committed: Signal/register improvements

This patch by Tony Reix fixes dumpregs on i386 to use the right type, implements dumpregs for PPC Linux/AIX, and retrieves the PC value on AIX. Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed to mainline. Ian Index: gcc/go/gofrontend/MERGE

[Bug fortran/81651] Enhancement request: have f951 print out fully qualified module file name

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81651 Thomas Koenig changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[PATCH, testsuite]: Adapt c-c++-common/patchable_function_entry-*.c for alpha

2017-08-16 Uros Bizjak * c-c++-common/patchable_function_entry-decl.c (dg-final): Adapt scan-assembler-times for alpha*-*-*. * c-c++-common/patchable_function_entry-default.c (dg-final): Ditto. * c-c++-common/patchable_function_entry-definition.c (dg-final):

[Bug fortran/81116] Last character of allocatable-length string reset to blank in an assigment

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81116 Thomas Koenig changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

Re: [PATCH] Further driver signal cleanup

On Wed, Aug 16, 2017 at 02:24:10PM -0400, Nathan Sidwell wrote: > This, almost obvious, patch merges the older SIGPIPE conditional into the > new switch I added. I found the FALLTHROUGH marker needed to be outside the > #if, which was a little annoying. True, it needs to precede the casea token.

[PATCH] Further driver signal cleanup

This, almost obvious, patch merges the older SIGPIPE conditional into the new switch I added. I found the FALLTHROUGH marker needed to be outside the #if, which was a little annoying. I changed the backtrace error message to also explicitly say it was a signal wot did it. ok? nathan --

[Bug lto/81861] [8.0 Regression] ASan pr64820.c testcase segfaults with LTO and -fstack-protector-strong

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81861 --- Comment #6 from Maxim Ostapenko --- Created attachment 41990 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=41990=edit Untested fix The problem is that LTO doesn't propagate changed ix86_stack_protector_guard_reg value: 6654 /*

Re: PR81635: Use chrecs to help find related data refs

"Bin.Cheng" writes: > On Wed, Aug 16, 2017 at 5:00 PM, Richard Sandiford > wrote: >> "Bin.Cheng" writes: >>> On Wed, Aug 16, 2017 at 2:38 PM, Richard Sandiford >>> wrote: The first

Re: [Bug web/?????] New: Fwd: failure notice: Bugzilla down.

On Wed, 16 Aug 2017, NightStrike wrote: > On Mon, Aug 14, 2017 at 11:10 PM, Martin Sebor wrote: > > On 08/14/2017 04:22 PM, Eric Gallager wrote: > >> > >> I'm emailing this manually to the list because Bugzilla is down and I > >> can't file a bug on Bugzilla about Bugzilla

Re: [Bug web/?????] New: Fwd: failure notice: Bugzilla down.

On Wed, 16 Aug 2017, NightStrike wrote: > On Mon, Aug 14, 2017 at 11:10 PM, Martin Sebor wrote: > > On 08/14/2017 04:22 PM, Eric Gallager wrote: > >> > >> I'm emailing this manually to the list because Bugzilla is down and I > >> can't file a bug on Bugzilla about Bugzilla

Re: [Bug web/?????] New: Fwd: failure notice: Bugzilla down.

On Wed, 16 Aug 2017, Eric Gallager wrote: > I see Richi redid all his 7.2 release changes; does that imply that > the server restore is now complete? No, there's still a search process ongoing to identify corrupted or missing files by comparison with the last backup. My expectation is that all

Re: [Bug web/?????] New: Fwd: failure notice: Bugzilla down.

On Wed, 16 Aug 2017, Eric Gallager wrote: > I see Richi redid all his 7.2 release changes; does that imply that > the server restore is now complete? No, there's still a search process ongoing to identify corrupted or missing files by comparison with the last backup. My expectation is that all

Re: [42/77] Use scalar_int_mode in simplify_shift_const_1

On 07/13/2017 02:53 AM, Richard Sandiford wrote: > This patch makes simplify_shift_const_1 use scalar_int_modes > for all code that is specific to scalars rather than vectors. > This includes situations in which the new shift mode is different > from the original one, since the function never

[Bug fortran/81116] Last character of allocatable-length string reset to blank in an assigment

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81116 --- Comment #3 from Thomas Koenig --- Author: tkoenig Date: Wed Aug 16 17:21:22 2017 New Revision: 251125 URL: https://gcc.gnu.org/viewcvs?rev=251125=gcc=rev Log: 2017-08-16 Thomas Koenig PR fortran/81116

Re: [41/77] Split scalar integer handling out of force_to_mode

On 07/13/2017 02:53 AM, Richard Sandiford wrote: > force_to_mode exits partway through for modes that aren't scalar > integers. This patch splits the remainder of the function out > into a subroutine, force_int_to_mode, so that the modes from that > point on can have type scalar_int_mode. > >

Re: [40/77] Use scalar_int_mode for extraction_insn fields

On 07/13/2017 02:52 AM, Richard Sandiford wrote: > insv, extv and eztzv modify or read a field in a register or > memory. The field always has a scalar integer mode, while the > register or memory either has a scalar integer mode or BLKmode. > The mode of the bit position is also a scalar

[Bug libstdc++/81797] gcc 7.1.0 fails to build on macOS 10.13 (High Sierra):

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81797 Misty De Meo changed: What|Removed |Added CC||misty at brew dot sh --- Comment #3 from

Re: [39/77] Two changes to the get_best_mode interface

On 07/13/2017 02:52 AM, Richard Sandiford wrote: > get_best_mode always returns a scalar_int_mode on success, > so this patch makes that explicit in the type system. Also, > the "largest_mode" argument is used simply to provide a maximum > size, and in practice that size is always a compile-time

Re: [36/77] Use scalar_int_mode in the RTL iv routines

On 07/13/2017 02:51 AM, Richard Sandiford wrote: > This patch changes the iv modes in rtx_iv from machine_mode > to scalar_int_mode. It also passes the mode of the iv down > to subroutines; this avoids the previous situation in which > the mode information was sometimes lost and had to be added >

Re: [Bug web/?????] New: Fwd: failure notice: Bugzilla down.

On Mon, Aug 14, 2017 at 11:10 PM, Martin Sebor wrote: > On 08/14/2017 04:22 PM, Eric Gallager wrote: >> >> I'm emailing this manually to the list because Bugzilla is down and I >> can't file a bug on Bugzilla about Bugzilla being down. The error >> message looks like this: > >

Re: [Bug web/?????] New: Fwd: failure notice: Bugzilla down.

On Mon, Aug 14, 2017 at 11:10 PM, Martin Sebor wrote: > On 08/14/2017 04:22 PM, Eric Gallager wrote: >> >> I'm emailing this manually to the list because Bugzilla is down and I >> can't file a bug on Bugzilla about Bugzilla being down. The error >> message looks like this: > >

[Bug c++/81868] Internal completer error: Segmentation Fault

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81868 --- Comment #1 from Al Thomason --- I was unable to attach the source files, too large. Please download directly from: https://github.com/AlternatorRegulator/alt-Source/archive/1.1.0.zip -or-

[Bug c++/81868] New: Internal completer error: Segmentation Fault

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81868 Bug ID: 81868 Summary: Internal completer error: Segmentation Fault Product: gcc Version: 4.9.2 Status: UNCONFIRMED Severity: normal Priority: P3 Component:

Re: [sparc64] kernel OOPS with gcc 7.1 / 7.2

From: Anatoly Pugachev Date: Wed, 16 Aug 2017 11:42:43 +0300 > On Wed, Aug 16, 2017 at 7:30 AM, David Miller wrote: >> From: Anatoly Pugachev >> Date: Tue, 15 Aug 2017 21:50:45 +0300 >> >>> Together with Dmitry (ldv) , we've

[Bug tree-optimization/81303] [8 Regression] 410.bwaves regression caused by r249919

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81303 amker at gcc dot gnu.org changed: What|Removed |Added CC||amker at gcc dot gnu.org ---

[Bug c/81859] [8 Regression] valgrind error from warn_about_normalization

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81859 --- Comment #3 from Martin Sebor --- Patch: https://gcc.gnu.org/ml/gcc-patches/2017-08/msg01004.html

[PATCH] use strnlen in pretty printer for "%.*s" (PR 81859)

Bug 81859 points out that my fix for bug 81586 wasn't quite right (or complete): the argument of a %.*s directive need not be a nul-terminated string when the precision is less than the initialized size of the array the argument points to. The attached tweak uses strnlen to avoid reading past

Re: PR81635: Use chrecs to help find related data refs

On Wed, Aug 16, 2017 at 5:00 PM, Richard Sandiford wrote: > "Bin.Cheng" writes: >> On Wed, Aug 16, 2017 at 2:38 PM, Richard Sandiford >> wrote: >>> The first loop in the testcase regressed after my recent changes

Re: PR81635: Use chrecs to help find related data refs

"Bin.Cheng" writes: > On Wed, Aug 16, 2017 at 2:38 PM, Richard Sandiford > wrote: >> The first loop in the testcase regressed after my recent changes to >> dr_analyze_innermost. Previously we would treat "i" as an iv even >> for bb analysis

[Bug c++/81867] New: Internal completer error: Segmentation Fault

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81867 Bug ID: 81867 Summary: Internal completer error: Segmentation Fault Product: gcc Version: 4.9.2 Status: UNCONFIRMED Severity: normal Priority: P3 Component:

[Bug middle-end/81814] [5/6/7/8 Regression] Incorrect behaviour at -O0 (conditional operator)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81814 Marek Polacek changed: What|Removed |Added Component|tree-optimization |middle-end Target Milestone|---

Re: tests for GCC internal functions

On 08/16/2017 09:20 AM, David Malcolm wrote: On Wed, 2017-08-16 at 16:51 +0200, Marek Polacek wrote: On Wed, Aug 16, 2017 at 08:46:20AM -0600, Martin Sebor wrote: Is there a setup for writing and running as part of the test suite unit tests that exercise internal GCC functions like error and

[Bug c++/81866] New: ICE with a default template parameter which is a template class nested in a template class

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81866 Bug ID: 81866 Summary: ICE with a default template parameter which is a template class nested in a template class Product: gcc Version: 7.1.1 Status: UNCONFIRMED

Re: Optimizing away deletion of null pointers with g++

On 08/16/2017 08:44 AM, Jonathan Wakely wrote: > On 16 August 2017 at 15:40, Jonathan Wakely wrote: >> On 16 August 2017 at 15:27, Oleg Endo wrote: >>> On Wed, 2017-08-16 at 13:30 +0200, Paolo Carlini wrote: I didn't understand why we don't already handle the easy case:

[PATCH, i386]: Allow memory operands for btr/bts and btc (PR target/46091)

Hello! Attached patch allows memory operands for btr/bts and btc instructions. The previous comment was wrong, these instructions do not enforce atomic operations with memory operand without "lock" prefix. Instructions in its RMW form with immediate operand are not slower than corresponding

[Bug target/46091] missed optimization: x86 bt/btc/bts instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=46091 --- Comment #3 from uros at gcc dot gnu.org --- Author: uros Date: Wed Aug 16 15:25:34 2017 New Revision: 251124 URL: https://gcc.gnu.org/viewcvs?rev=251124=gcc=rev Log: PR target/46091 * config/i386/i386.md (*anddi_1_btr):

Re: c-family PATCH to improve -Wtautological-compare (PR c/81783)

On Wed, Aug 16, 2017 at 11:07:36AM -0400, David Malcolm wrote: > On Wed, 2017-08-16 at 16:29 +0200, Marek Polacek wrote: > > This patch improves -Wtautological-compare so that it also detects > > bitwise comparisons involving & and | that are always true or false, > > e.g. > > > > if ((a & 16)

Re: c-family PATCH to improve -Wtautological-compare (PR c/81783)

On 8/16/17, David Malcolm wrote: > On Wed, 2017-08-16 at 16:29 +0200, Marek Polacek wrote: >> This patch improves -Wtautological-compare so that it also detects >> bitwise comparisons involving & and | that are always true or false, >> e.g. >> >> if ((a & 16) == 10) >>

  1   2   3   4   >