Hi,
Mentor Graphics is submitting on behalf of Altera, a GCC port for the
Nios II architecture. Attached are the series of patches, including a
few small additions to machine-independent parts.
We are proposing Sandra Loosemoore and myself (Chung-Lin Tang), both of
Mentor Graphics, as port
These are patches for libgcc.
2013-04-18 Sandra Loosemore san...@codesourcery.com
Chung-Lin Tang clt...@codesourcery.com
Based on patches from Altera Corporation
* config.host (nios2-*-*,nios2-*-linux*): Add nios2 host cases.
* config/nios2/lib2-nios2.h
Testsuite changes, including gcc.target tests, plus some selected
filtering of some other tests.
2013-04-18 Sandra Loosemore san...@codesourcery.com
Chung-Lin Tang clt...@codesourcery.com
Based on patches from Altera Corporation
* gcc.dg/stack-usage-1.c (SIZE
This patch was a fix by Julian which corrected a HOST_BITS_PER_WIDE_INT
host dependency in dwarf generation. Nios II does not have
need_64bit_hwint switched on during configuring, and ran into GDB test
FAILs originating from this problem.
2013-04-18 Julian Brown jul...@codesourcery.com
the code on the command line, we are
proposing the attached patch to allow, for example '-mcustom-fadds=255'
to be written as '-mcustom-fadds=0xff'
2013-04-18 Chung-Lin Tang clt...@codesourcery.com
* opts-common.c (integral_argument): Add support for hexadecimal
command option
On 2013/4/18 09:49 PM, Chung-Lin Tang wrote:
Testsuite changes, including gcc.target tests, plus some selected
filtering of some other tests.
2013-04-18 Sandra Loosemore san...@codesourcery.com
Chung-Lin Tang clt...@codesourcery.com
Based on patches from Altera
Hi Sterling,
the last thread pointer builtin changes left an unused 'arg' variable in
xtensa_expand_builtin(), which triggered a new warning. Thanks to
Jan-Benedict for testing this. Attached patch was committed as obvious.
Thanks,
Chung-Lin
* config/xtensa/xtensa.c
On 12/9/27 6:25 AM, Janis Johnson wrote:
On 09/26/2012 01:58 AM, Chung-Lin Tang wrote:
+/* { dg-do compile } */
+/* { dg-options -mthumb -O1 -march=armv5te -fno-omit-frame-pointer
-fno-forward-propagate } */
+/* { dg-require-effective-target arm_thumb1_ok } */
This test will fail
On 2012/10/12 06:55 AM, Oleg Endo wrote:
This broke the recently added thread pointer built-ins on SH, but I was
prepared for that, so no problem here. The attached patch is a straight
forward fix.
However, with the patch applied I get an ICE on one of the SH thread
pointer tests:
This patch set has been committed, thanks to all maintainers who
reviewed the respective parts.
Thanks,
Chung-Lin
Full ChangeLog:
2012-10-11 Chung-Lin Tang clt...@codesourcery.com
* builtins.c (expand_builtin_thread_pointer): New.
(expand_builtin_set_thread_pointer): New
it)
Resubmitting the patch adapted, basically a single-liner adding
CORE_REGS to the preferred reload class under Thumb-1. Cross-tested
with no regressions under -march=armv5te -mthumb. Okay for trunk?
Thanks,
Chung-Lin
2012-09-26 Chung-Lin Tang clt...@codesourcery.com
PR target/44557
On 2012/9/16 05:15 PM, Richard Sandiford wrote:
Second ping for the ARM part of Chung-Lin's __builtin_thread_pointer patch:
http://gcc.gnu.org/ml/gcc-patches/2012-08/msg01914.html
I think this is the only part that hasn't been approved.
Thanks,
Richard
Ping again.
(and thanks to
On 2012/8/28 下午 04:15, Chung-Lin Tang wrote:
On 12/7/12 下午2:52, Chung-Lin Tang wrote:
Xtensa parts updated to use MD pattern.
Thanks,
Chung-Lin
* config/xtensa/xtensa.md (get_thread_pointersi): Renamed from
load_tp.
(set_thread_pointersi): Renamed from set_tp
On 2012/8/28 下午 04:14, Chung-Lin Tang wrote:
On 12/7/12 5:47 PM, Ramana Radhakrishnan wrote:
On 12 July 2012 07:52, Chung-Lin Tang clt...@codesourcery.com wrote:
ARM parts, no further notes.
ARM parts are ok, modulo approval for generic parts and no
regressions with testing on arm-linux
On 2012/7/6 02:23 PM, Richard Sandiford wrote:
Richard Sandiford rdsandif...@googlemail.com writes:
(3) Also related to libraries, I edited CRT_CALL_STATIC_FUNCTION to emit
a 32-bit code sequence under both MIPS/MIPS16 mode (under O32).
As you can see in the original Feb. patch, I had changes
On 2012/8/30 02:44 AM, Richard Sandiford wrote:
Chung-Lin Tang clt...@codesourcery.com writes:
On 2012/7/6 02:23 PM, Richard Sandiford wrote:
Richard Sandiford rdsandif...@googlemail.com writes:
(3) Also related to libraries, I edited CRT_CALL_STATIC_FUNCTION to emit
a 32-bit code sequence
On 12/7/12 2:52 PM, Chung-Lin Tang wrote:
Core parts adding the new hooks. BUILT_IN_THREAD_POINTER and
BUILT_IN_SET_THREAD_POINTER are different hooks, as some targets only
implement one of them (thread pointer read).
Following Richard H.'s advice, I have revised the patch to use a
standard
On 12/7/12 2:52 PM, Chung-Lin Tang wrote:
Alpha parts. Note that now the machine-independent
__builtin_thread_pointer() is now marked as const/readonly, slightly
different from the original alpha backend code.
Alpha patch updated to use MD pattern.
* config/alpha/alpha.md
On 12/7/12 5:47 PM, Ramana Radhakrishnan wrote:
On 12 July 2012 07:52, Chung-Lin Tang clt...@codesourcery.com wrote:
ARM parts, no further notes.
ARM parts are ok, modulo approval for generic parts and no
regressions with testing on arm-linux-gnueabi.
ARM parts updated to use MD patterns
On 12/7/18 8:05 PM, Andreas Krebbel wrote:
On 07/12/2012 08:52 AM, Chung-Lin Tang wrote:
* config/s390/s390.c (s390_builtin,code_for_builtin_64,
code_for_builtin_31,s390_init_builtins,s390_expand_builtin):
Remove.
(s390_expand_builtin_thread_pointer): Add hook
On 12/7/12 下午2:52, Chung-Lin Tang wrote:
xtensa parts. No other notes.
Thanks,
Chung-Lin
* config/xtensa/xtensa.c
(xtensa_expand_builtin_thread_pointer): Add hook function for
TARGET_EXPAND_BUILTIN_THREAD_POINTER.
(xtensa_expand_builtin_set_thread_pointer
On 12/7/12 2:53 PM, Chung-Lin Tang wrote:
Finally, what I personally need, the MIPS parts.
Thanks,
Chung-Lin
* config/mips/mips.c (mips_get_tp): Add 'target' parameter for
generating to specific reg.
(mips_legitimize_tls_address): Update calls to mips_get_tp
On 2012/8/23 05:08, Richard Guenther wrote:
First of all the warning should be probably issued from stor-layout.c
itself - see
other cases where we warn about packed structs. Yes, that means you'll
get the warning even when there is no access but you'll only get it a
single time.
As of
the associated updated xlp.md, essentially the same
description posted earlier, but with the m(f|t)(hi|lo) attributes
updated to use the new style. Also included is the new XLP case in
mips_issue_rate().
Thanks,
Chung-Lin
2012-07-20 Chung-Lin Tang clt...@codesourcery.com
Maxim Kuvyrkov
On 2012/7/16 12:28 AM, Richard Sandiford wrote:
Chung-Lin Tang clt...@codesourcery.com writes:
This patch adds scheduling support for the NetLogic XLP, including a new
pipeline description, and associated changes.
Asides from the new xlp.md description file, there are also some sync
On 12/7/14 9:58 AM, Mike Stump wrote:
On Jul 12, 2012, at 11:47 PM, Chung-Lin Tang clt...@codesourcery.com wrote:
and then for the return value, maybe a const0_rtx for Pmode.
A little unsure what you mean. Are you referring to return const0_rtx
for default_expand_builtin_thread_pointer
On 2012/7/13 09:28 AM, Mike Stump wrote:
On Jul 11, 2012, at 11:52 PM, Chung-Lin Tang wrote:
Core parts adding the new hooks. BUILT_IN_THREAD_POINTER and
BUILT_IN_SET_THREAD_POINTER are different hooks, as some targets only
implement one of them (thread pointer read).
sorry seems a little
On 2012/7/13 02:37 AM, Richard Sandiford wrote:
+void
+default_expand_builtin_set_thread_pointer (rtx val ATTRIBUTE_UNUSED)
+{
+ sorry (__builtin_set_thread_pointer() not available for this target);
+}
Function names should be quoted by % %. But maybe we can save the
translators some
On 2012/7/13 02:45 AM, Richard Sandiford wrote:
/* Implement TARGET_EXPAND_BUILTIN_THREAD_POINTER. */
static rtx
mips_expand_builtin_thread_pointer (rtx tp)
{
rtx fn;
if (TARGET_MIPS16)
...
}
(i.e. always using the passed-in tp, which is safe with your 1/6 patch),
then
...@codesourcery.com
Date: Mon, 18 Jun 2012 18:10:19 -0700
Subject: [PATCH] XLP scheduling.
2012-07-13 Chung-Lin Tang clt...@codesourcery.com
Maxim Kuvyrkov ma...@codesourcery.com
NetLogic Microsystems Inc.
* config/mips/mips.md (define_attr type): New values atomic
, s390, and xtensa
ports, so please bear with me if you see anything wrong (the patches are
simply straightforward changes associated with the builtin).
Thanks,
Chung-Lin
Full ChangeLog:
2012-07-12 Chung-Lin Tang clt...@codesourcery.com
* targhooks.c
Core parts adding the new hooks. BUILT_IN_THREAD_POINTER and
BUILT_IN_SET_THREAD_POINTER are different hooks, as some targets only
implement one of them (thread pointer read).
Thanks,
Chung-Lin
* targhooks.c (default_expand_builtin_thread_pointer): New.
Alpha parts. Note that now the machine-independent
__builtin_thread_pointer() is now marked as const/readonly, slightly
different from the original alpha backend code.
Thanks,
Chung-Lin
* config/alpha/alpha.c (alpha_builtin): Remove
ALPHA_BUILTIN_THREAD_POINTER,
ARM parts, no further notes.
Thanks,
Chung-Lin
* config/arm/arm.c (arm_builtins): Remove
ARM_BUILTIN_THREAD_POINTER.
(arm_init_tls_builtins): Remove function.
(arm_init_builtins): Remove call to arm_init_tls_builtins().
(arm_expand_builtin): Remove
S390 parts. In this patch, because the thread-pointer builtins were the
only machine-dependent builtins in the s390 backend, I have removed
basically all the init/expand builtin hook code. If the s390 maintainers
want to keep the code for possible future backend builtins, this patch
might need to
xtensa parts. No other notes.
Thanks,
Chung-Lin
* config/xtensa/xtensa.c
(xtensa_expand_builtin_thread_pointer): Add hook function for
TARGET_EXPAND_BUILTIN_THREAD_POINTER.
(xtensa_expand_builtin_set_thread_pointer): Add hook function
for
Finally, what I personally need, the MIPS parts.
Thanks,
Chung-Lin
* config/mips/mips.c (mips_get_tp): Add 'target' parameter for
generating to specific reg.
(mips_legitimize_tls_address): Update calls to mips_get_tp().
(mips_expand_builtin_thread_pointer): Add
On 2012/7/6 02:23 PM, Richard Sandiford wrote:
Richard Sandiford rdsandif...@googlemail.com writes:
(3) Also related to libraries, I edited CRT_CALL_STATIC_FUNCTION to emit
a 32-bit code sequence under both MIPS/MIPS16 mode (under O32).
As you can see in the original Feb. patch, I had changes
Hi Richard,
picking up a yet uncommitted part of the MIPS16 changes, see below:
On 2012/2/3 11:28 PM, Richard Sandiford wrote:
Chung-Lin Tang clt...@codesourcery.com writes:
(2) is interesting if there is also a way to build those MIPS16 libraries
out of the box. I'd like such a mechanism
On 2012/6/26 09:37 AM, Yi-Hsiu Hsu wrote:
Updated changelog.
* config/arm/marvell-pj4.md: New marvell-pj4 pipeline description.
* config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
* config/arm/arm.md (tune_marvell): Add marvell_pj4.
* config/arm/arm-cores.def: Add core marvell-pj4.
*
On 2012/6/14 02:18 AM, Ramana Radhakrishnan wrote:
On 29 May 2012 10:07, Yi-Hsiu Hsu a...@marvell.com wrote:
Hi,
This patch maintains Marvell PJ4 cores pipeline description.
Run arm testsuite on arm-linux-gnueabi and no extra regressions are found.
* config/arm/marvell-pj4.md: New
Ping?
On 2012/6/1 06:24 PM, Chung-Lin Tang wrote:
On 12/5/23 1:46 AM, Richard Henderson wrote:
On 05/18/12 03:48, Chung-Lin Tang wrote:
@@ -2401,6 +2401,7 @@ scan_trace (dw_trace_info *trace)
{
/* Propagate across fallthru edges. */
dwarf2out_flush_queued_reg_saves
On 12/5/23 1:46 AM, Richard Henderson wrote:
On 05/18/12 03:48, Chung-Lin Tang wrote:
@@ -2401,6 +2401,7 @@ scan_trace (dw_trace_info *trace)
{
/* Propagate across fallthru edges. */
dwarf2out_flush_queued_reg_saves ();
+ def_cfa_1 (this_cfa
On 2012/5/18 03:26 PM, Gabriel Dos Reis wrote:
On Fri, May 18, 2012 at 12:48 AM, Chung-Lin Tang
clt...@codesourcery.com wrote:
The point here is that, a group of changes that broke C bootstrap went
in undetected for several days, because of the partially C++ default. To
prevent
on SH and MIPS, and bootstrapped/tested on x86_64.
Thanks,
Chung-Lin
2012-05-18 Chung-Lin Tang clt...@codesourcery.com
* dwarf2cfi.c (scan_trace): Update CFA before exiting scan.
Handle annulled-taken branch (!INSN_FROM_TARGET_P) case.
Index: dwarf2cfi.c
. The
generated unwind info should still be correct, though will need other
changes to be optimal.
Thanks,
Chung-Lin
2012-05-18 Chung-Lin Tang clt...@codesourcery.com
* config/sh/sh.c (output_stack_adjust): Remove !epilogue_p
condition for generating REG_FRAME_RELATED_EXPR note
together once approved.
Thanks,
Chung-Lin
2012-05-18 Chung-Lin Tang clt...@codesourcery.com
* configure.ac: Check for -Wmissing-declarations for C++.
* configure: Regenerate.
* Makefile.in (CXX_LOOSE_WARN): Set to @cxx_loose_warn@.
(GCC_WARN_CXXFLAGS): Add $(CXX_LOOSE_WARN).
Index: configure.ac
On 2012/5/18 03:20 AM, Joseph S. Myers wrote:
On Fri, 18 May 2012, Chung-Lin Tang wrote:
Joseph, how does this look? It makes the default post-stage1 C++
bootstrap fail similarly without the other options.c Makefile change, so
I guess it works as intended.
For build system patches you
, and
-Werror -Wmissing-prototypes are in effect (oddly, such strict checking
is not enforced in the default post-stage1 C++ bootstrap)
Here's a simple one-liner Makefile.in change that seems to make things
work. Okay to commit?
Thanks,
Chung-Lin
2012-05-17 Chung-Lin Tang clt...@codesourcery.com
...
The attached patch adds an additional equality check, plus some comment
updates. Cross-tested without regressions, is this okay for trunk?
Thanks,
Chung-Lin
2012-03-27 Chung-Lin Tang clt...@codesourcery.com
PR target/52667
* config/sh/sh.c (find_barrier): Add equality check
(the mem-ref2 merge, may be related to effects on bitfields).
So if suitable, please also approve this patch for 4.6/4.7 branches.
Thanks,
Chung-Lin
2012-03-10 Chung-Lin Tang clt...@codesourcery.com
PR rtl-optimization/52528
* combine.c (can_combine_p): Add setting of subst_low_luid
Hi Richard,
Sorry for the delay to respond, and thanks for revising and committing
the changes to trunk. The revised changes look much cleaner :)
About the other concerns:
(2) is interesting if there is also a way to build those MIPS16 libraries
out of the box. I'd like such a mechanism to
On 2012/1/22 06:33 PM, Richard Sandiford wrote:
The MIPS16 port has never handled long branches properly; see PR 51931
for the details. It isn't easy to xfail MIPS16-specific problems at
the dejagnu level because of -mflip-mips16, so the patch below forces
a nomips16 attribute instead.
Hi, I noticed that cfgloop.c:cancel_loop() is missing a free of the bbs
array obtained from get_loop_body(). Committed attached patch as obvious.
Thanks,
Chung-Lin
2012-01-08 Chung-Lin Tang clt...@codesourcery.com
* cfgloop.c (cancel_loop): Add free() of bbs array.
Index: cfgloop.c
to build glibc
as MIPS16 code with this TLS implementation, so I believe things should
be fairly stable.
Anyways, I believe this will be going in only after 4.8-stage1 opens, so
you should have plenty time to review it :)
Thanks, and Happy New Year
Chung-Lin
2012-01-06 Chung-Lin Tang clt
On 2011/12/19 上午 03:18, Richard Henderson wrote:
On 12/17/2011 10:36 PM, Chung-Lin Tang wrote:
I don't think it's that kind of problem; the powerpc backend uses
unlikely_text_section_p(), which compares the passed in argument section
and the value of function_section_1(current_function_decl
On 2011/12/17 06:21 AM, Richard Henderson wrote:
On 12/16/2011 03:16 AM, Chung-Lin Tang wrote:
Hi, under powerpc targets, using -mrelocatable under some cases triggers
an error during final assembly generation: rs6000_assemble_integer()
calls varasm.c:unlikely_text_section_p(), and the call
to compile.
Tested on a powerpc target, is this okay for trunk? (and maybe 4.6 too?)
Thanks,
Chung-Lin
2011-12-16 Chung-Lin Tang clt...@codesourcery.com
gcc/
* varasm.c (default_section_type_flags): Set SECTION_CODE in
flags when decl is NULL_TREE, and section name
On 2011/12/5 12:39 AM, Mike Stump wrote:
On Dec 4, 2011, at 3:29 AM, Richard Sandiford rdsandif...@googlemail.com
wrote:
The problem is that MIPS has
native TLS support, but the ABI has not yet been extended to MIPS16.
MIPS16 is supposed to be link-compatible with non-MIPS16, so we can't
applied, attaching committed patch.
Thanks,
Chung-Lin
Index: ChangeLog
===
--- ChangeLog (revision 181662)
+++ ChangeLog (working copy)
@@ -1,3 +1,9 @@
+2011-11-23 Chung-Lin Tang clt...@codesourcery.com
+
+ PR rtl
On 2011/10/25 02:04 AM, Bernd Schmidt wrote:
On 10/24/11 20:02, Chung-Lin Tang wrote:
On 2011/10/18 04:03 PM, Eric Botcazou wrote:
thread_prologue_and_epilogue_insns should detect all cases where a
return insn can be created. So any CFG cleanup that runs before it does
not need
On 2011/10/27 04:33 PM, Revital Eres wrote:
Hello,
I'm working on estimating register pressure in SMS and using
ira_available_class_regs for getting the number of available
registers.
However I encounter a case where ira_available_class_regs showed 64
available regs for a certain class
, so the patch here just tries to plug the recursion hole
for the exact condition.
Bootstrapped and tested on i686 and x86_64 without regressions. Is this
okay for trunk?
Thanks,
Chung-Lin
2011-10-27 Chung-Lin Tang clt...@codesourcery.com
PR rtl-optimization/49720
* simplify-rtx.c
On 2011/10/18 04:03 PM, Eric Botcazou wrote:
thread_prologue_and_epilogue_insns should detect all cases where a
return insn can be created. So any CFG cleanup that runs before it does
not need this functionality.
So we're left with CFG cleanups that run after it and could forward edges to
Hi Richard, this looks very similar to this patch, originally for LP:689887:
http://gcc.gnu.org/ml/gcc-patches/2011-01/msg00794.html
Apart from your additional handling in the dominance modes cases.
I remember that last patch was held down because Thumb-2 native
bootstrap failed. Did you try that
On 2011/6/15 09:12 PM, Richard Earnshaw wrote:
On 22/04/11 16:21, Chung-Lin Tang wrote:
Hi Richard, this part's for you.
The ARM backend changes needed are very little after the prior patches,
basically just a case in arm_canonicalize_comparison() to detect
(zero_extend:SI (subreg:QI (reg:SI
On 2011/7/18 04:46 PM, Richard Earnshaw wrote:
The patch to arm.c is ok, but the change to the test is not as it will cause
problems with multilib testing. A better fix is to skip the test if the
target is thumb1.
The other test needs a similar check as it seems to expect a movs
Ping.
On 2011/5/9 11:02 PM, Chung-Lin Tang wrote:
Ping.
On 04/22/2011 11:21 PM, Chung-Lin Tang wrote:
Hi Richard, this part's for you.
The ARM backend changes needed are very little after the prior patches,
basically just a case in arm_canonicalize_comparison() to detect
(zero_extend:SI
Ping.
On 2011/5/26 01:29 AM, Chung-Lin Tang wrote:
On 2011/5/20 07:46 PM, Chung-Lin Tang wrote:
On 2011/5/20 下午 07:41, Ramana Radhakrishnan wrote:
On 17/05/11 14:10, Chung-Lin Tang wrote:
On 2011/5/13 04:26 PM, Richard Sandiford wrote:
Richard Sandifordrichard.sandif...@linaro.org writes
On 2011/5/20 07:46 PM, Chung-Lin Tang wrote:
On 2011/5/20 下午 07:41, Ramana Radhakrishnan wrote:
On 17/05/11 14:10, Chung-Lin Tang wrote:
On 2011/5/13 04:26 PM, Richard Sandiford wrote:
Richard Sandifordrichard.sandif...@linaro.org writes:
Chung-Lin Tangclt...@codesourcery.com writes:
My
On 2011/5/20 11:45 AM, Dmitry Plotnikov wrote:
This patch adds support for 12-bit immediate values for Thumb-2 in ADD and
SUB instructions. We added two new alternatives for *arm_addsi3 which
make use of two new constraints for 12-bit values. Also we modified
costs of PLUS rtx expression.
On 2011/5/20 下午 12:10, Richard Earnshaw wrote:
On Fri, 2011-05-20 at 18:06 +0200, Chung-Lin Tang wrote:
On 2011/5/20 11:45 AM, Dmitry Plotnikov wrote:
This patch adds support for 12-bit immediate values for Thumb-2 in ADD and
SUB instructions. We added two new alternatives for *arm_addsi3
On 2011/5/21 12:06 AM, Chung-Lin Tang wrote:
I'll also note here that ADD/SUB are not the only instructions with
12-bit immediate under Thumb-2; so does AND, ORR, etc.
FTR, I was wrong on the above statement. Only add/sub seems to have the
wide constant operands.
CL
On 2011/5/20 下午 07:41, Ramana Radhakrishnan wrote:
On 17/05/11 14:10, Chung-Lin Tang wrote:
On 2011/5/13 04:26 PM, Richard Sandiford wrote:
Richard Sandifordrichard.sandif...@linaro.org writes:
Chung-Lin Tangclt...@codesourcery.com writes:
My fix here simply adds 'reload_completed
On 2011/5/13 04:26 PM, Richard Sandiford wrote:
Richard Sandiford richard.sandif...@linaro.org writes:
Chung-Lin Tang clt...@codesourcery.com writes:
My fix here simply adds 'reload_completed' as an additional condition
for EPILOGUE_USES to return true for LR_REGNUM. I think this should
Ping.
On 04/22/2011 11:21 PM, Chung-Lin Tang wrote:
Hi Richard, this part's for you.
The ARM backend changes needed are very little after the prior patches,
basically just a case in arm_canonicalize_comparison() to detect
(zero_extend:SI (subreg:QI (reg:SI ...) 0)), and swap it into (and:SI
On 2011/5/6 05:57 PM, Paolo Bonzini wrote:
On 04/22/2011 05:21 PM, Chung-Lin Tang wrote:
Also, instead of testing for XEXP(SET_SRC(PATTERN(i3)),1) == const0_rtx
at the top, it now allows CONST_INT_P(XEXP(SET_SRC(PATTERN(i3)),1)),
tries to adjust it by simplify_compare_const() from the last
; it should be safe for IRA to treat it as a normal call-used register.
I did a cross-test on QEMU with clean results, plus a successful native
bootstrap on a Pandaboard. Is this okay for trunk?
Thanks,
Chung-Lin
2011-04-28 Chung-Lin Tang clt...@codesourcery.com
PR target/42017
On 2011/4/26 02:08 AM, Jeff Law wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 04/22/11 09:21, Chung-Lin Tang wrote:
This patch is the main bulk of this submission. It modifies the compare
combining part of try_combine(), adding a call of
CANONICALIZE_COMPARISON into the entire
regressions. ARM cross-testing also completed without
regressions, and currently doing a native bootstrap test.
Thanks,
Chung-Lin
2011-04-22 Chung-Lin Tang clt...@codesourcery.com
* combine.c (simplify_comparison): Abstract out parts into...
(simplify_compare_const): ... new function
This patch abstracts out a small part of simplify_comparison(), into a
new function simplify_compare_const(). The parts are basically where the
comparison RTX code and a constant operand (op1) can be simplified
towards compare with zero. Note this part leaves op0 untouched, thus
not passed into
This patch is the main bulk of this submission. It modifies the compare
combining part of try_combine(), adding a call of
CANONICALIZE_COMPARISON into the entire logic.
Also, instead of testing for XEXP(SET_SRC(PATTERN(i3)),1) == const0_rtx
at the top, it now allows
Hi Richard, this part's for you.
The ARM backend changes needed are very little after the prior patches,
basically just a case in arm_canonicalize_comparison() to detect
(zero_extend:SI (subreg:QI (reg:SI ...) 0)), and swap it into (and:SI
(reg:SI) #255).
Had we not tried the combine
On 2011/4/20 11:12 PM, Richard Earnshaw wrote:
On Wed, 2011-04-20 at 23:06 +0800, Chung-Lin Tang wrote:
On 2011/4/20 09:24 PM, Richard Sandiford wrote:
Hi Chung-Lin,
I'm seeing an ICE with this patch, specifically;
Chung-Lin Tang clt...@codesourcery.com writes:
+ if (coproc_p
Ping.
On 2011/3/31 10:57 PM, Chung-Lin Tang wrote:
This PR doesn't exactly trigger currently on trunk; a REG_DEAD note that
occurs in trunk, but not in the 4.5-based compilers which this bug was
reported for, currently blocks auto-inc-dec from doing its job, and just
happens to avoid this ICE
updates to work, so I'm leaving that for a later patch.
I've listed your name together as significant parts are from you. Is it
ready for trunk?
Thanks,
Chung-Lin
2011-04-08 Chung-Lin Tang clt...@codesourcery.com
Richard Earnshaw rearn...@arm.com
PR target/48250
On 2011/3/31 06:14 PM, Richard Earnshaw wrote:
On Thu, 2011-03-31 at 11:33 +0800, Chung-Lin Tang wrote:
On 2011/3/30 05:28 PM, Richard Earnshaw wrote:
On Wed, 2011-03-30 at 15:35 +0800, Chung-Lin Tang wrote:
On 2011/3/30 上午 12:23, Richard Earnshaw wrote:
On Tue, 2011-03-29 at 22:53 +0800
, are currently not enabled for
NEON struct modes (OI, XI, etc.) This only needs a small patch to
neon_struct_mem_operand() to work. Okay for trunk?
Thanks,
Chung-Lin
2011-03-31 Chung-Lin Tang clt...@codesourcery.com
* config/arm/arm.c (neon_struct_mem_operand):
Support POST_INC/PRE_DEC
On 2011/4/1 01:33 AM, Richard Earnshaw wrote:
On Thu, 2011-03-31 at 22:18 +0800, Chung-Lin Tang wrote:
On 2011/3/31 06:14 PM, Richard Earnshaw wrote:
On Thu, 2011-03-31 at 11:33 +0800, Chung-Lin Tang wrote:
On 2011/3/30 05:28 PM, Richard Earnshaw wrote:
On Wed, 2011-03-30 at 15:35 +0800
On 2011/3/30 上午 12:23, Richard Earnshaw wrote:
On Tue, 2011-03-29 at 22:53 +0800, Chung-Lin Tang wrote:
On 2011/3/29 下午 10:26, Richard Earnshaw wrote:
On Tue, 2011-03-29 at 18:25 +0800, Chung-Lin Tang wrote:
On 2011/3/24 06:51 PM, Richard Earnshaw wrote:
On Thu, 2011-03-24 at 12:56 +0900
On 2011/3/30 05:28 PM, Richard Earnshaw wrote:
On Wed, 2011-03-30 at 15:35 +0800, Chung-Lin Tang wrote:
On 2011/3/30 上午 12:23, Richard Earnshaw wrote:
On Tue, 2011-03-29 at 22:53 +0800, Chung-Lin Tang wrote:
On 2011/3/29 下午 10:26, Richard Earnshaw wrote:
On Tue, 2011-03-29 at 18:25 +0800
On 2011/3/24 06:51 PM, Richard Earnshaw wrote:
On Thu, 2011-03-24 at 12:56 +0900, Chung-Lin Tang wrote:
Hi,
PR48250 happens under TARGET_NEON, where DImode is included within the
valid NEON modes. This turns the range of legitimate constant indexes to
step-4 (coproc load/store), thus
On 2011/3/29 下午 10:26, Richard Earnshaw wrote:
On Tue, 2011-03-29 at 18:25 +0800, Chung-Lin Tang wrote:
On 2011/3/24 06:51 PM, Richard Earnshaw wrote:
On Thu, 2011-03-24 at 12:56 +0900, Chung-Lin Tang wrote:
Hi,
PR48250 happens under TARGET_NEON, where DImode is included within the
valid
On 2011/3/30 06:35 AM, Ramana Radhakrishnan wrote:
Hi Carrot,
On 26/03/11 15:14, Carrot Wei wrote:
Index: arm.md
===
--- arm.md(revision 171337)
+++ arm.md(working copy)
@@ -7115,7 +7115,18 @@
@
cmp%?\\t%0,
On 2011/3/18 12:18 AM, Richard Henderson wrote:
On 03/16/2011 06:55 PM, Chung-Lin Tang wrote:
You have to use DeMorgan's Law to distribute the ~ operator:
Duh. Not sure where my head was yesterday.
Let's enhance the comment for someone else having an off day. Perhaps
/* Given
On 2011/3/20 08:11 PM, Richard Guenther wrote:
On Sun, Mar 20, 2011 at 12:01 PM, Chung-Lin Tang
clt...@codesourcery.com wrote:
Hi,
PR48183 is a case where ARM NEON instrinsics, under -O -g, produce debug
insns that tries to expand OImode (32-byte integer) zero constants, much
too large
?
Thanks,
Chung-Lin
2011-03-20 Chung-Lin Tang clt...@codesourcery.com
* emit-rtl.c (immed_double_const): Allow wider than
2*HOST_BITS_PER_WIDE_INT mode constants when they are
representable as a single const_int RTX.
Index: emit-rtl.c
-tested on ARM-Linux
using QEMU, all with no regressions. Okay for trunk?
Thanks,
Chung-Lin
2011-03-16 Chung-Lin Tang clt...@codesourcery.com
* combine.c (try_combine): Do simplification only call of
subst() on i2 even when i1 is present. Update comments.
testsuite
On 2011/3/17 03:21 AM, Richard Henderson wrote:
On 03/11/2011 06:14 AM, Chung-Lin Tang wrote:
+ /* Given (xor (and A B) C), using P^Q == ~PQ | ~QP (concat as AND),
+ we can transform (AB)^C into:
+ A(~CB) | ~AC | ~BC
+ Attempt a few
On 2011/3/15 02:41 PM, Ramana Radhakrishnan wrote:
On 17/02/11 10:01, Chung-Lin Tang wrote:
Hi,
this PR is a case where we have a leaf function with a zero-size frame,
that calls alloca() (here through a C99 VLA).
The ARM backend recognizes the leaf-and-no-frame opportunity to save
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