Re: RFC [1/2] divmod transform

On Mon, May 30, 2016 at 12:45 AM, Richard Biener wrote: > Joseph - do you know sth about why there's not a full set of divmod > libfuncs in libgcc? Because udivmoddi4 isn't a libfunc, it is a helper function for the div and mov libfuncs. Since we can compute the signed div

Re: [PATCH, AARCH64] add qdf24xx tuning structure

On Mon, Jun 13, 2016 at 1:53 AM, James Greenhalgh <james.greenha...@arm.com> wrote: > On Fri, Jun 10, 2016 at 03:48:38PM -0700, Jim Wilson wrote: >> This adds a tuning structure for qdf24xx. This was tested with an > Have you seen my recent patch for Cortex-A57 that

Re: [PATCH, AARCH64] add qdf24xx tuning structure

On Mon, Jun 13, 2016 at 3:01 AM, Kyrill Tkachov <kyrylo.tkac...@foss.arm.com> wrote: > Hi Jim, > > On 10/06/16 23:48, Jim Wilson wrote: >> >> This adds a tuning structure for qdf24xx. This was tested with an >> aarch64-linux bootstrap and a make check, with

[PATCH, GCC 5] PR 70613, -fabi-version docs don't match implementation

=== --- ChangeLog (revision 234867) +++ ChangeLog (working copy) @@ -1,3 +1,12 @@ +2016-04-11 Jim Wilson <jim.wil...@linaro.org> + + Partial backport from trunk r228017. + 2015-09-22 Jason Merrill <ja...@redhat.com> + + PR c++/70613 + * doc/invoke.texi (-

Re: [PATCH, GCC 5] PR 70613, -fabi-version docs don't match implementation

On 04/18/2016 01:12 PM, Jim Wilson wrote: On 04/11/2016 01:41 PM, Jim Wilson wrote: Here is a patch to correct the -fabi-version docs on the GCC 5 branch. https://gcc.gnu.org/ml/gcc-patches/2016-04/msg00480.html ping^2 Jim

Re: [PATCH][AArch64][wwwdocs] Summarise some more AArch64 changes for GCC6

On Thu, Apr 21, 2016 at 1:15 AM, Kyrill Tkachov wrote: > Jim, you added support for the qdf24xx identifier to -mcpu and -mtune. > Could you please suggest an appropriate entry to describe it? > I think the same format as the Cortex-A35 entry in this patch would be >

Re: [PATCH][AArch64][wwwdocs] Summarise some more AArch64 changes for GCC6

On Wed, Apr 27, 2016 at 3:33 AM, Kyrill Tkachov wrote: > Thanks, I've incorporated your and James' feedback. > Since James ok'd the content of the patch from an AArch64 perspective > I'll commit this later today if I receive no further feedback. There is no paragraph

Re: [PATCH][AArch64] Improve aarch64_case_values_threshold setting

On Mon, May 16, 2016 at 4:30 AM, James Greenhalgh wrote: > As this change will change code generation for all cores (except > Exynos-M1), I'd like to hear from those with more detailed knowledge of > ThunderX, X-Gene and qdf24xx before I take this patch. It looks like a

Re: PING^5 [PATCH, GCC 5] PR 70613, -fabi-version docs don't match implementation

This is my fifth ping. I just need someone to rubber stamp it so I can check it in. Maybe it would be easier if I volunteered to be a doc maintainer so I can self approve it? Jim On Mon, May 9, 2016 at 4:21 PM, Jim Wilson <jim.wil...@linaro.org> wrote: > On Mon, May 2, 2016 at 12:1

[PATCH] misc minor doc fixes

Deletes text claiming that major version changes are rare, and fixes two misspellings of signaling. Tested with make info and make dvi. Jim 2016-05-16 Jim Wilson <jim.wil...@linaro.org> * doc/cpp.texi (__GNUC__): Major version changes are no longer rare. * doc/invoke.texi (-mna

[PATCH, ARM] use vmov.i64 to load 0 into FP reg if neon enabled

For this simple testcase double sub (void) { return 0.0; } Without the attached patch, an ARM compiler with neon support enabled, gives vldr.64 d0, .L2 With the attached patch, an ARM compiler with neon enabled, gives vmov.i64 d0, #0@ float which is faster and smaller, as there is no

Re: [PATCH, GCC 5] PR 70613, -fabi-version docs don't match implementation

On Mon, Apr 25, 2016 at 11:47 AM, Bernd Schmidt wrote: Here is a patch to correct the -fabi-version docs on the GCC 5 branch. >>> https://gcc.gnu.org/ml/gcc-patches/2016-04/msg00480.html ping^3 I put an explanation of the patch history for gcc-5 in the PR

Re: [PATCH, GCC 5] PR 70613, -fabi-version docs don't match implementation

On 04/11/2016 01:41 PM, Jim Wilson wrote: Here is a patch to correct the -fabi-version docs on the GCC 5 branch. Ping https://gcc.gnu.org/ml/gcc-patches/2016-04/msg00480.html Jim

PING^4 [PATCH, GCC 5] PR 70613, -fabi-version docs don't match implementation

On Mon, May 2, 2016 at 12:13 PM, Jim Wilson <jim.wil...@linaro.org> wrote: > Here is a patch to correct the -fabi-version docs on the GCC 5 branch. > https://gcc.gnu.org/ml/gcc-patches/2016-04/msg00480.html Maybe I didn't put enough info in the email the first 3 times? You can see

Re: [PATCH, ARM] use vmov.i64 to load 0 into FP reg if neon enabled

On Fri, May 6, 2016 at 7:29 AM, Kyrill Tkachov wrote: > Since you're modifying the both the ARM and Thumb2 pattern > can you please do two bootstrap and tests, one with --with-mode=arm > and one with --with-mode=thumb. > Ok after adding the assert mentioned above,

Re: 10 x 1036778084 = ??

On 07/07/2016 10:07 PM, Nobby-Hirand wrote: I have just find strange answer, 10 x 1036778084 = 1777846248?? Your target has 32-bit integers. The value 1036778084 is close to the largest representable value. Multiplying by anything larger than 2 causes an overflow, and the result gets

Re: [PATCH/AARCH64] Improve ThunderX code generation slightly with load/store pair

On 08/05/2016 12:18 AM, Andrew Pinski wrote: This patch disables the forming of the load/store pairs for SImode if we are tuning for ThunderX. I used the tuning flags route so it can be overridden if needed later on or if someone else wants to use the same method for their core. + if (mode

[PATCH] loop distribution bug fix

distributions. There is no measurable performance gain from the bug fix on the CPU2006 run time though I plan to spend some more time looking at this code to see if I can find other improvements. OK? Jim 2016-11-09 Jim Wilson <jim.wil...@linaro.org> * tree-loop-distribu

Re: [RFC] Possible folding opportunities for string built-ins

On 10/12/2016 08:55 AM, Joseph Myers wrote: On Wed, 12 Oct 2016, Martin Liška wrote: Last question is whether one can aggressively fold strcasecmp in a host compiler? Or are there any situations where results depends on locale? There are the usual issues with Turkish locales having the

Re: [PATCH] loop distribution bug fix

On Thu, Nov 10, 2016 at 2:53 AM, Richard Biener wrote: > The biggest "lack" of loop distribution is the ability to undo CSE so for I hadn't noticed this problem yet. I will have to take a look. > Then of course the cost model is purely modeled for STREAM (reduce the

Re: Possible bug with switch when optimization is turned on.

On 12/05/2016 03:24 PM, luke B wrote: The following code seems to be correctly executed when compiled with GCC 4.4.7 and LLVM 6.1. It does not correctly compile with gcc version 5.4.0 20160609 (Ubuntu 5.4.0-6ubuntu1~16.04.4). I created a bug report and added some info.

Re: Problem with Factory Generated code g++ 4.x, 5.x, 6.x

On 12/18/2016 12:15 PM, Eduardo Yÿffe1nez via gcc-bugs wrote: >I wish to report a problem with g++ 4.x, g++ 5.x, g++ 6.x. I'm trying >to implement a very classic Factory Method Pattern in C++, I can do it >very easily in MS-Visual C++, but in Linux with g++ the code compiles >but I get

[PATCH] fix aarch64/combine bootstrap miscompare

disabled in some cases. I haven't had a chance to look at this in detail yet. The patch was preapproved by Jeff and has been checked in. Jim 2017-03-17 Jim Wilson <jim.wil...@linaro.org> * combine.c (try_combine): Delete redundant i1 test. Call prev_nonnote_nondebug_insn i

Re: [RFC][PATCH][AArch64] Improve generic branch cost

On Tue, Mar 14, 2017 at 2:37 AM, James Greenhalgh wrote: > I'd like to hear comments from the Exynos-M1, Falkor and > xgene-1 subtarget contributors, particularly as these targets use > generic_branch_costs for their subtarget-sepcific tuning. It may be that > your patch

Re: [PATCH][AArch64] Enable AES fusion with -mcpu=generic

On Thu, Mar 16, 2017 at 11:01 AM, Andrew Pinski wrote: > On Thu, Mar 16, 2017 at 10:22 AM, Wilco Dijkstra > wrote: >> Many supported cores implement fusion of AES instructions. When fusion >> happens it can give a significant performance gain. If

Re: [PATCH][AArch64] Enable AUTOPREFETCHER_WEAK with -mcpu=generic

On Wed, Apr 5, 2017 at 5:38 AM, Wilco Dijkstra wrote: > Many supported cores use the AUTOPREFETCHER_WEAK setting which tries > to order loads and stores to improve streaming performance. Since significant > gains were reported in http://patchwork.ozlabs.org/patch/534469/

[PATCH] handling address mode changes inside extract_bit_field

This is a proposed patch for the bug 79794 which I just submitted. This isn't a regression, so this can wait for after the gcc 7 branch if necessary. The problem here is that a reg+offset MEM target is passed to extract_bit_field with a vector register source. On aarch64, we have an instruction

[PATCH, AArch64] Add falkor pipeline description.

This adds a pipeline description for the Qualcomm Falkor core. This was tested with a bootstrap and make check. There were no regressions. This gives about 0.5% performance gain on SPEC CPU2006 on our internal tree, which has a few other patches that aren't in the FSF tree yet. OK? Jim

Re: [PATCH] skip patchable_function_entry tests on ia64

On Fri, 2017-08-11 at 12:34 +0200, Torsten Duwe wrote: > gcc/testsuite/ChangeLog > 2017-08-11  Torsten Duwe   > > * c-c++-common/patchable_function_entry-default.c: Skip test on > ia64. > * c-c++-common/patchable_function_entry-decl.c: Likewise. > *

[PATCH] scheduler bug fix for AArch64 insn fusing SCHED_GROUP usage

queued. Since sched group insns always sort to the top of the list of insns to schedule, all sched group insns still get scheduled together as before. This has been tested with an Aarch64 bootstrap and make check. OK? Jim 2017-07-13 Jim Wilson <jim.wil...@linaro.org> PR rtl-optimization

Re: [PATCH, AArch64] Add RDMA support to Falkor.

Ping. Jim On Thu, Jun 29, 2017 at 1:53 PM, Jim Wilson <jim.wil...@linaro.org> wrote: > Falkor is an ARMV8-A part, but also includes the RDMA extension from > ARMV8.1-A. > I'd like to enable support for the RDMA instructions when -mcpu=falkor is > used, > and also ma

Re: sanitizer bug maybe.

On 07/10/2017 10:29 AM, George R Goffe via gcc-bugs wrote: ../../../../gcc/libsanitizer/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cc: In function ‘int __sanitizer::TracerThread(void*)’: ../../../../gcc/libsanitizer/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cc:276:22:

Re: [PATCH] Make __FUNCTION__ a mergeable string and do not generate symbol entry.

On Fri, Jul 14, 2017 at 1:35 AM, Martin Liška wrote: > May I ask Jim to test the patch? > Patch can bootstrap on ppc64le-redhat-linux and survives regression tests. I started an aarch64 bootstrap to test. My fast machine is busy with work tasks, so I have to use a slower

Re: [PATCH] Make __FUNCTION__ a mergeable string and do not generate symbol entry.

On Fri, Jul 14, 2017 at 12:59 PM, Jim Wilson <jim.wil...@linaro.org> wrote: > On Fri, Jul 14, 2017 at 1:35 AM, Martin Liška <mli...@suse.cz> wrote: >> May I ask Jim to test the patch? >> Patch can bootstrap on ppc64le-redhat-linux and survives regression tests. > &g

Re: [PATCH] Kill TYPE_METHODS debug 1/9

On 07/14/2017 09:48 AM, Nathan Sidwell wrote: This changes dbxout and dwarf2out. Oh, the patch series survived a bootstrap on x86_64-linux. Changes to the debug info files requires a gdb make check with and without the patch to check for regressions. Since you are changing both dbxout

Re: Deprecate DBX/stabs?

On Fri, Jul 21, 2017 at 12:44 PM, Iain Sandoe wrote: > It ought to be already, in fact anything (powerpc*/x86/x86-64) >= Darwin9 (OS > X 10.5) ought to be defaulting to DWARF already, will check that sometime. Yes, they do default to dwarf2. The comments say pre-darwin9

Re: [PATCH] scheduler bug fix for AArch64 insn fusing SCHED_GROUP usage

Ping. https://gcc.gnu.org/ml/gcc-patches/2017-07/msg00779.html On Thu, Jul 13, 2017 at 3:00 PM, Jim Wilson <jim.wil...@linaro.org> wrote: > The AArch64 port uses SCHED_GROUP to mark instructions that get fused > at issue time, to ensure that they will be issued togeth

Re: [PATCH] Kill TYPE_METHODS 0/9

build, and checked in under the obvious rule. Jim 2017-07-25 Jim Wilson <jim.wil...@linaro.org> gcc/ PR bootstrap/81521 * config/i386/winnt-cxx.c (i386_pe_adjust_class_at_definition): Look for FUNCTION_DECLs in TYPE_FIELDS rather than TYPE_METHODS. Index: gcc/config/i386/winnt

Re: [PATCH] Kill TYPE_METHODS 0/9

build, and checked in under the obvious rule. Jim 2017-07-25 Jim Wilson <jim.wil...@linaro.org> gcc/ PR bootstrap/81521 * config/i386/winnt-cxx.c (i386_pe_adjust_class_at_definition): Look for FUNCTION_DECLs in TYPE_FIELDS rather than TYPE_METHODS. Index: gcc/config/i386/winnt

[PATCH] Delete files unused since openbsd 2 & 3 support was dropped.

Trevor Saunders deleted the x86 openbsd 2 & 3 support here. https://gcc.gnu.org/ml/gcc-patches/2016-06/msg01368.html With that change, there are now 3 unused files that he missed. I noticed the gstabs.h file while looking at debugging info related files, and then did a consistency check and

Re: [PATCH 00/17] RFC: New source-location representation; Language Server Protocol

On 07/24/2017 01:04 PM, David Malcolm wrote: * The LSP implementation is a just a proof-of-concept, to further motivate capturing the extra data. Turning it into a "proper" LSP server implementation would be a *lot* more work, and I'm unlikely to actually do that (but maybe someone on

Re: [PATCH] dwarf2out.c patch for AIX

On 07/22/2017 08:29 PM, David Edelsohn wrote: This patch mirrors the earlier patch to copy debug_section_label into dl_section_ref and append the adjustment when necessary. With this patch, GDB is able to report correct macro information. Bootstrapped on powerpc-ibm-aix7.2.0.0 Debug related

Re: [PATCH, AArch64] Add RDMA support to Falkor.

Ping^2 On Tue, Jul 11, 2017 at 1:49 PM, Jim Wilson <jim.wil...@linaro.org> wrote: > Ping. > > Jim > > On Thu, Jun 29, 2017 at 1:53 PM, Jim Wilson <jim.wil...@linaro.org> wrote: >> Falkor is an ARMV8-A part, but also includes the RDMA extension from >> A

Re: [PATCH] Kill TYPE_METHODS debug 1/9

On Thu, Jul 20, 2017 at 2:00 PM, Nathan Sidwell wrote: > With this patch the gdb stabs test results are still awful, but they are > unchanged awfulness. Yes, the stabs support for C++ is poor. That is one of the reasons why almost everyone has switched to dwarf2. I wasn't sure

Re: Deprecate DBX/stabs?

On Fri, Jul 21, 2017 at 7:15 AM, David Edelsohn wrote: > AIX still uses DBX as the primary debugging format. AIX supports > DWARF but the AIX toolchain does not fully interoperate with DWARF > generated by GCC. We could still deprecate DBX_DEBUG while leaving XCOFF_DEBUG

[PATCH] Add RDMA support to Falkor.

Falkor is an ARMV8-A part, but also includes the RDMA extension from ARMV8.1-A. I'd like to enable support for the RDMA instructions when -mcpu=falkor is used, and also make the RDMA intrisics available. To do that, I need to add rdma as an architecture extension, and modify a few things to use

[PATCH, ARM/AArch64] drop aarch32 support for falkor/qdf24xx

Early steppings had aarch32 support, current steppings don't, so the aarch32 support for falkor/qdf24xx needs to be dropped. This mostly involves removing falkor/qdf24xx references from the arm port. The qdf24xx_extra_costs structure moves from the arm port to the aarch64 port. This was tested

Re: [PATCH] handling address mode changes inside extract_bit_field

On Fri, May 12, 2017 at 7:01 PM, Martin Sebor wrote: > Explicitly passing the additional argument at all the call sites > can be mitigated by giving the new alt_rtl argument a default > value of NULL in the declarations of the extract_bit_field functions. I keep forgetting

Re: [PATCH] handling address mode changes inside extract_bit_field

On Thu, May 4, 2017 at 7:24 PM, Jeff Law <l...@redhat.com> wrote: > On 03/01/2017 03:06 PM, Jim Wilson wrote: > This seems fine to me. A testcase to add to the gcc.target testsuite would > be useful, but I don't think it's strictly necessary. Thanks for the review. It was 2

Re: Record equivalences for spill registers

On Sun, May 7, 2017 at 11:47 PM, Andrew Pinski wrote: > On Sun, May 7, 2017 at 11:37 PM, Richard Sandiford > wrote: >> Really sorry for the breakage. I'd forgotten that this depended on: >> >>

Re: [PATCH, ARM/AArch64] drop aarch32 support for falkor/qdf24xx

On Mon, Jun 12, 2017 at 3:40 AM, James Greenhalgh wrote: > In both the original patch, and the backport, you're modifying the > AArch64 options here. I'd expect the edits to be to the AArch32 options > (these start somewhere around line 15,000). Yes, I screwed this up.

[PATCH, libgfortran] proposed fix for SPEC CPU2017 621.wrf_s failures

As mentioned in bug 81195, I see openmp related failures due to a lack of locking of the newunit_stack and newunit_tos variables. The code locks when pushing onto the stack, but does not lock when popping from the stack. This can cause multiple threads to pop the same structure, which then

Re: [PATCH, ARM/AArch64] drop aarch32 support for falkor/qdf24xx

On Wed, May 24, 2017 at 6:56 AM, Richard Earnshaw (lists) wrote: > OK. does this need to go in the gcc-8 changes file? Falkor hasn't shipped yet. I'm dropping features that only existed in preproduction NDA hardware, so there isn't anything end user visible, and hence

Re: [PATCH, ARM/AArch64] drop aarch32 support for falkor/qdf24xx

On Wed, May 24, 2017 at 8:17 AM, Richard Earnshaw (lists) <richard.earns...@arm.com> wrote: > On 24/05/17 15:18, Jim Wilson wrote: >> On Wed, May 24, 2017 at 6:56 AM, Richard Earnshaw (lists) >> <richard.earns...@arm.com> wrote: >>> OK. does this need to go in

Re: [PATCH] handling address mode changes inside extract_bit_field

I've got a testcase to add for this patch. Sorry about the delay, I took some time off to deal with a medical problem. This was tested with and without the extract_bit_field patch. The testcase fails without the patch and works with the patch. Jim gcc/testsuite/ PR middle-end/79794 *

Re: [PATCH, ARM/AArch64] drop aarch32 support for falkor/qdf24xx

On Thu, May 25, 2017 at 2:25 AM, Richard Earnshaw (lists) wrote: > Having pondered this over night, I think the lowest risk thing to do, > provided it applies cleanly to the gcc-7 branch, is just commit the > entire patch on the branch and be done with it. The risk from

Re: Record equivalences for spill registers

On 05/05/2017 12:23 AM, Richard Sandiford wrote: 2017-05-05 Richard Sandiford gcc/ * lra-constraints.c (lra_copy_reg_equiv): New function. (split_reg): Use it to copy equivalence information from the original register to the spill

[PATCH, AArch64] Disable reg offset in quad-word store for Falkor.

On Falkor, because of an idiosyncracy of how the pipelines are designed, a quad-word store using a reg+reg addressing mode is almost twice as slow as an add followed by a quad-word store with a single reg addressing mode. So we get better performance if we disallow addressing modes using register

Re: [PATCH, AArch64] Disable reg offset in quad-word store for Falkor.

On Fri, Sep 22, 2017 at 8:49 AM, Jim Wilson <jim.wil...@linaro.org> wrote: > On Falkor, because of an idiosyncracy of how the pipelines are designed, a > quad-word store using a reg+reg addressing mode is almost twice as slow as an > add followed by a quad-word store with a single

Re: [PATCH, AArch64] Disable reg offset in quad-word store for Falkor.

On Fri, Sep 22, 2017 at 10:58 AM, Andrew Pinski wrote: > Two overall comments: > * What about splitting register_offset into two different elements, > one for non 128bit modes and one for 128bit (and more; OI, etc.) modes > so you get better address generation right away for

Re: Enable no-exec stacks for more targets using the Linux kernel

On Mon, 2017-09-18 at 22:03 +, Joseph Myers wrote: > Thus, I'd like the architecture maintainers to advise on whether any > such issues apply for their architecture.  If they do, that will > provide the information needed for a comment on XFAILing the test in > glibc.  If no such reasons apply

[PATCH, wwwdocs] update my steering committee info

,v retrieving revision 1.40 diff -u -r1.40 steering.html --- steering.html 17 Mar 2015 21:12:09 - 1.40 +++ steering.html 3 Oct 2017 21:37:21 - @@ -38,7 +38,7 @@ Ramana Radhakrishnan (ARM) Joel Sherrill (OAR Corporation) Ian Lance Taylor (Google) -Jim Wilson (Linaro) +Jim Wilson and

Re: [PATCH, AArch64] Disable reg offset in quad-word store for Falkor.

On Fri, 2017-09-22 at 14:11 -0700, Andrew Pinski wrote: > On Fri, Sep 22, 2017 at 11:39 AM, Jim Wilson <jim.wil...@linaro.org> > wrote: > > > > On Fri, Sep 22, 2017 at 10:58 AM, Andrew Pinski <pins...@gmail.com> > > wrote: > > > > > &

Re: [PATCH] scheduler bug fix for AArch64 insn fusing SCHED_GROUP usage

ping^2 On Fri, Jul 21, 2017 at 3:09 PM, Jim Wilson <jim.wil...@linaro.org> wrote: > Ping. > > https://gcc.gnu.org/ml/gcc-patches/2017-07/msg00779.html > > On Thu, Jul 13, 2017 at 3:00 PM, Jim Wilson <jim.wil...@linaro.org> wrote: >> The AArch64 port uses SCHED_GR

Re: Fwd: [PATCH] scheduler bug fix for AArch64 insn fusing SCHED_GROUP usage

On Sun, 2017-09-10 at 19:45 +0200, Jim Wilson wrote: > -- Forwarded message -- > From: Jim Wilson <jim.wil...@linaro.org> > Date: Tue, Sep 5, 2017 at 8:04 PM > Subject: Re: [PATCH] scheduler bug fix for AArch64 insn fusing > SCHED_GROUP usage > To: "

Re: [PATCH v2] [libcc1] Rename C{,P}_COMPILER_NAME and remove triplet from them

On 11/13/2017 01:10 PM, Sergio Durigan Junior wrote: On Tuesday, September 26 2017, I wrote: Ping^2. Ping^3. I'm sending the updated ChangeLog/patch. I'm also removing gdb-patches from the Cc list. libcc1/ChangeLog: 2017-09-01 Sergio Durigan Junior

Re: [PATCH] Fix hot/cold partitioning with -gstabs{,+} (PR debug/81307)

On 11/27/2017 12:21 AM, Richard Biener wrote: Let's formally deprecate any non-DWARF debugging format support in GCC 8 changes.html? I think we need to be careful about that. I've been looking at the stabs support after I finished removing the sdb/coff debug info support. We have 3 cpu

[PATCH, gcc-7] Fix RISCV ICE on linux kernel build.

This fixes an ICE that occurs during a linux kernel build with gcc-7-branch by backporting a patch from mainline. The problem occurs when using -fpic, as we have patterns with a clobber for loading/storing from/to an address using a symbol. During optimization, it is possible for optimizations

[PATCH, gcc-7] Add riscv musl support.

This adds MUSL support to the riscv port in gcc-7, as we had a request for it. Tested with a glibc toolchain build to verify it doesn't break anything, and a musl gcc build to verify that the dynamic linker names are right for each -mabi option value. Committed. gcc/ Backport

[PATCH, docs] Cleanup riscv option docs.

This patch fixes a number of issues with the RISC-V option docs. Deletes a non-existent option. Adds missing default value info. Deletes some redundant lines that appear to be from a patch merging error. Adds missing docs for the -mexplicit-relocs option. Tested with a make doc, and viewing

[PATCH] Riscv patterns to optimize away some redundant zero/sign extends.

This adds some new patterns to eliminate some unecessary zero/sign extends. This also adds one testcase for each pattern, and one testcase that works only with the rtx_costs change. There is a lot more work to be done here, but this does help. With a toolchain/linux kernel/busybox build, I see

Re: [PATCH, docs] Cleanup riscv option docs.

On Tue, Nov 28, 2017 at 2:17 PM, Jim Wilson <j...@sifive.com> wrote: > I'll wait a few days in case a doc maintainer wants to comment, and then will > check it in as is if I don't get any comments. > gcc/ > * doc/invoke.texi (RISC-V Options): Delete no

[PATCH, gcc-7] Riscv doc fixes and improvements.

gcc/ Backport from mainline 2017-11-30 Jim Wilson <j...@sifive.com> * doc/invoke.texi (RISC-V Options): Delete nonexistent -mmemcpy and -mno-memcpy options. For -mplt, -mfdiv, -mdiv, -msave-restore, and -mstrict-align, add info on default value.

[PATCH, gcc-7] Fix riscv linux kernel boot failure.

This patch is necessary in order to successfully boot a linux kernel on the UCB spike simulator. Riscv loads sign-extend by default, but this wasn't explicitly mentioned in the pic load patterns, resulting in some bad code generation. Fixed by adding an explicit sign_extend operation to the

Re: [PATCH] Fix hot/cold partitioning with -gstabs{,+} (PR debug/81307)

On 11/24/2017 01:53 PM, Jakub Jelinek wrote: Could anybody from the debugger folks test it a little bit (say gdb testsuite if it has any -O2 -gstabs/-O2 -gstabs+ tests)? The gdb testsuite just uses "-g" by default. It doesn't have any tests with optimization by default, though this can be

Re: [PATCH] Fix hot/cold partitioning with -gstabs{,+} (PR debug/81307)

On 11/27/2017 01:54 PM, Jim Wilson wrote: On 11/27/2017 12:21 AM, Richard Biener wrote: Let's formally deprecate any non-DWARF debugging format support in GCC 8 changes.html?   We have two OS targets that only support stabs, though in both cases the cpus do support dwarf and hence

[PATCH, gcc-7] Add riscv -mstrict-align option.

This patch is necessary for proper support of targets that don't directly implement unaligned accesses. Tested with a linux+busybox build and boot, and a gcc testsuite run. There were no regressions. Also tested by hand on some small testcases to verify that it was doing something useful.

[PATCH] Fix typos in riscv register save/restore.

This patch fixes a few typos with computing registers to save/restore in prologue/epilogue. This fixes the github riscv/riscv-gcc issue #111. The typos are harmless, as these registers are call clobbered, but this was a problem for one person modifying gcc for academic reasons, and hence the

[PATCH RISC-V] Use C version of multi3 for RVE support.

This replaces the assembly language version of multi3/muldi3 with a C version, as the assembly version does not work on RVE targets. The C code is using the same basic algorithm as the assembly code. The RVE spec is not finalized yet, so we haven't added the RVE option support yet, but this is

Re: [PATCH] RISC-V: Implement __umulsidi3, umul_ppmm and __muluw3

On 11/17/2017 04:09 PM, Palmer Dabbelt wrote: From: Kito Cheng 2017-11-17 Kito Cheng * longlong.h [__riscv] (__umulsidi3): Define. [__riscv] (umul_ppmm) Likewise. [__riscv] (__muluw3) Likewise. Apparently the point of

Re: [PATCH,doc] Fix latency in pipeline description example

On 11/09/2017 03:44 AM, Luis Machado wrote: Am i missing something or is this example incorrect and this should either have a latency of 9 (patch attached) or a different resource utilization description, say, containing "div*6" instead? The numbers are somewhat arbitrary, but you are right

Re: [PATCH, wwwdocs] sdb removal release note patch

On Mon, 2017-11-06 at 14:07 -0800, Jim Wilson wrote: > The sdb/coff debug info format removal should be mentioned in the > release notes. Here is a patch to do that. I didn't get an comments on this, so I went ahead and checked it in. Jim

Re: Patch ping

On 11/19/2017 11:55 PM, Jakub Jelinek wrote: I'd like to ping the following patches: http://gcc.gnu.org/ml/gcc-patches/2017-10/msg01895.html PR debug/82718 Fix DWARF5 .debug_loclist handling with hot/cold partitioning I already responded to this one.

Re: Patch ping

On 11/20/2017 02:58 PM, Jim Wilson wrote: The dwarf2out.c patch looks good to me, though the testcase does not fail on unpatched mainline anymore.  I had to go back to the 2017-10-22 snapshot to see the failure.  There was a followup from Mark Wielaard mentioning that elfutils still fails

Re: [patches] Re: [PATCH] RISC-V: Implement __umulsidi3, umul_ppmm and __muluw3

On Sun, Nov 19, 2017 at 7:34 PM, Kito Cheng wrote: > > I prefer write more comment in the code instead of ChangeLog, I add > more comment in __muluw3. > btw, long times ago, Vladimir was told me[1] it should contain what is > done but not why it is done? Yes, the ChangeLog

Re: Patch ping^2

On 11/14/2017 08:29 AM, Jakub Jelinek wrote: On Mon, Nov 06, 2017 at 05:22:36PM +0100, Jakub Jelinek wrote: I'd like to ping the: http://gcc.gnu.org/ml/gcc-patches/2017-10/msg01895.html PR debug/82718 Fix DWARF5 .debug_loclist handling with hot/cold partitioning patch. Thanks

Re: [PATCH,RFC] collect2 LTO for AIX

On 10/31/2017 12:11 PM, David Edelsohn wrote: With your recent removal of SDB and -gcoff support, I would appreciate your advice about my patch to incrementally add some preliminary LTO support for AIX to collect2.c: OK. I can take a look. I started a new job this week, so I'm a bit

Re: [PATCH,RFC] collect2 LTO for AIX

On 10/30/2017 12:13 PM, Jeff Law wrote: On 10/13/2017 12:04 PM, David Edelsohn wrote: This patch adds the basic LTO scanning pass to the COFF support in collect2. I don't believe that this change should affect other COFF targets adversely (do they even use collect2?), but I wanted to give

{PATCH, wwwdocs] update employer in steering committee list

A patch to add my new employer to the steering committee page. Verified as XHTML 1.0 transitional and checked in. Jim Index: steering.html === RCS file: /cvs/gcc/wwwdocs/htdocs/steering.html,v retrieving revision 1.41 diff -p -r1.41

[PATCH] Remove obsolete ECOFF support.

While looking at the collect2 COFF support, I noticed that there were two uses of EXTENDED_COFF which is for the obsolete ECOFF support. The last define for EXTENDED_COFF was removed 2012-03-14, so these uses are obsolete and can be removed. Tested with Power AIX C/C++ bootstrap and make check,

Re: [PATCH] RISC-V: Add Jim Wilson as a maintainer

On Mon, Nov 6, 2017 at 6:39 PM, Palmer Dabbelt <pal...@dabbelt.com> wrote: > > +riscv port Jim Wilson <j...@sifive.com> > > It is jimw not jim for the email address. Please fix. Jim

[PATCH, wwwdocs] sdb removal release note patch

The sdb/coff debug info format removal should be mentioned in the release notes. Here is a patch to do that. Verified as XHTML 1.0 transitional. My new employer disclaimer is on file at the FSF as of today, and I have personal assignments, so I'm good to contribute again. OK? Jim Index:

Re: [PATCH,RFC] collect2 LTO for AIX

On 10/31/2017 12:11 PM, David Edelsohn wrote: With your recent removal of SDB and -gcoff support, I would appreciate your advice about my patch to incrementally add some preliminary LTO support for AIX to collect2.c: https://gcc.gnu.org/ml/gcc-patches/2017-10/msg00893.html There don't seem to

[PATCH] Add srodata section support to riscv port.

This adds srodata section support to the RISC-V port, putting small read-only data in the .srodata section instead of the .sdata section. There is already code to put small read-only rtx in .srodata* instead of .rodata*. This does the same for small read-only trees to be consistent. Tested with

[RFA, PATCH] Deprecate stabs if dwarf2 support available.

This is based on an idea from Richard Biener that was mentioned here https://gcc.gnu.org/ml/gcc-patches/2017-11/msg02376.html If we are interested in doing this, it would be accompanied by documentation changes to state that stabs is now deprecated in favor of dwarf2, release notes to

[PATCH] Add .type and .size directives to riscv libgcc functions.

This rewrites the riscv libgcc function to use macros for function definitions, to add the missing type and size directives, and to make future changes easier. This was tested with make check with rv32i and rv64i builds, with and without -msave-restore, to force all of the modified functions to

[PATCH] Delete obsolete DWARF1 references.

I noticed a stray DWARF_DEBUG reference. The DWARF1 support was removed in 2004. So I did a quick find|grep and I found two more. This patch removes them. This was tested with quick x86_64-linux and mips-wrs-vxworks builds just to verify that they still build, and by hand checking the docs to

Re: [RFA, PATCH] Deprecate stabs if dwarf2 support available.

On Mon, Dec 4, 2017 at 2:38 AM, Richard Biener wrote: > Note that "deprecation" doesn't match up with giving an error when using. > We should warn (or maybe just document deprecation) instead. OK. I can warn instead. That makes a lot of things simpler for gcc-8.

[PATCH] fix AIX fortran builds

add a call to gcc_unreachable after the longjmp call, then it builds on both linux and AIX.  Anyone have a better idea on how to fix this?  If I don't get any responses in a few days, I will check it in under the obvious rule, since it fixes a build failure. Jim 2017-10-29 Jim Wilson <

Re: [PATCH] fix cygwin builds

enum memmodel); >  ^ Looks like alpha, sparc, and tilegx have the same problem.  Fixed by including memmodel.h before tm_p.h.  Tested with quick x86_64-linux C only bootstrap, and checked in under the obvious rule. Jim 2017-10-30 Jim Wilson <wil...@tuliptree.org>

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