Re: About implementation of the Negative property of options.

On Fri, Apr 30, 2021 at 1:03 AM gengqi-linux wrote: > Thanks for your replies. > I would suggest filing a bug report, and adding useful info from this thread to the bug report. Then we can track it. Jim

Re: [PATCH] doc/options.texi: Fix the discription of 'Negative'.

On Wed, Apr 28, 2021 at 2:25 AM Geng Qi via Gcc-patches < gcc-patches@gcc.gnu.org> wrote: > gcc/ChangeLog: > * doc/options.texi (Negative): Fix the discription so that it > matches > the code implementation of prune_options(). > This matches my testing as mentioned in another

Re: [PATCH] [RISCV] Add Pattern for builtin overflow

On Tue, Apr 27, 2021 at 12:45 AM Andrew Waterman wrote: > > signed addition (SImode with RV64): > > add t0, t1, t2 > > sext.w t3, t0 > > bne t0, t3, overflow > > The following version has the same instruction count but offers more ILP: > > add t0, t1, t2 > addw t3,

Re: [PATCH 00/10] [RISC-V] Atomics improvements [PR100265/PR100266]

On Mon, Apr 26, 2021 at 5:45 AM Christoph Muellner wrote: > This series provides a cleanup of the current atomics implementation > of RISC-V: > This looks OK to me, other than the issue with address instructions emitted inside the lr/sc loop. That could be fixed with a follow up patch though.

Re: [PATCH] PR target/98878 - Incorrect multilib list for riscv*-rtems

On Thu, Feb 4, 2021 at 2:02 AM Kito Cheng wrote: > * gcc.c (print_multilib_info): Check all required argument is > provided > by default arg. > This looks OK to me, but... > > - /* If this directory requires any default arguments, we can skip > + /* If this directory

Re: [PATCH] RISC-V: Fix -march option parsing when `p` extension exists.

On Thu, Jan 21, 2021 at 10:49 PM Kito Cheng wrote: > I think this patch is small enough to accept without FSF copyright > assignment, and he is also on the way of the process, what do you > think? > I see the copyright assignments on file at the FSF when I checked today. Jim

Re: [RFC] test builtin ratio for loop distribution

On Wed, Jan 27, 2021 at 4:40 AM Alexandre Oliva wrote: > This patch attempts to fix a libgcc codegen regression introduced in > gcc-10, as -ftree-loop-distribute-patterns was enabled at -O2. > > RISC-V doesn't have any setmemM pattern, so the loops above end up > "optimized" into memset calls,

Re: [PATCH v2 0/5] RISC-V big endian support

On Fri, Mar 19, 2021 at 9:22 AM Kito Cheng via Gcc-patches < gcc-patches@gcc.gnu.org> wrote: > On Mon, Mar 15, 2021 at 5:42 AM Marcus Comstedt wrote: > > I've now delved a bit deeper into the failure of the testcase > > gcc.c-torture/compile/pr35318.c on big endian RV32. > Looking at this

Re: add rv64im{,c,fc} multilibs

On Tue, Feb 23, 2021 at 2:17 AM Alexandre Oliva wrote: > I take your response as confirming my expectation that the defaults are > to remain unchanged for now, and I will thus proceed under this > assumption. > If we add default multilibs for you, then to be fair, we need to add default

Re: [PATCH] RISC-V: Add implementation for builtin overflow

On Thu, Jan 21, 2021 at 2:25 AM Levy wrote: > Added implementation for builtin overflow detection, new patterns are > listed below. > For rv32 SImode and rv64 DImode, the unsigned add/sub and signed/unsigned mul patterns seem to give the same result as the default code generation. That has me

Re: [PATCH] RISC-V: Zihintpause: add __builtin_riscv_pause

On Thu, Jan 7, 2021 at 12:50 AM Kito Cheng wrote: > My point is tracking info and consistent behavior/scheme with other > extensions, so personally I strongly prefer it should be guarded with > -march. > It is a hint. We should allow it even if the architecture extension is not enabled. For

[PATCH] RISC-V: Shorten memrefs improvement, partial fix 97417.

We already have a check for riscv_shorten_memrefs in riscv_address_cost. This adds the same check to riscv_rtx_costs. Making this work also requires a change to riscv_compressed_lw_address_p to work before reload by checking the offset and assuming any pseudo reg is OK. Testing shows that this

[PATCH] RISC-V: Avoid zero/sign extend for volatile loads. Fix for 97417.

From: Levy Hsu This expands sub-word loads as a zero/sign extended load, followed by a subreg. This helps eliminate unnecessary zero/sign extend insns after the load, particularly for volatiles, but also in some other cases. Testing shows that it gives consistent code size decreases. Tested

Re: [PATCH 1/2] Add TARGET_COMPUTE_MULTILIB hook to override multi-lib result.

On Wed, Jul 21, 2021 at 2:28 AM Kito Cheng wrote: > Create a new hook to let target could override the multi-lib result, > the motivation is RISC-V might have very complicated multi-lib re-use > rule*, which is hard to maintain and use current multi-lib scripts, > we even hit the "argument list

Re: [PATCH 2/2] RISC-V: Implement TARGET_COMPUTE_MULTILIB

On Tue, Aug 31, 2021 at 5:22 PM Jim Wilson wrote: > On Wed, Jul 21, 2021 at 2:28 AM Kito Cheng wrote: > >> Use TARGET_COMPUTE_MULTILIB to search the multi-lib reuse for >> riscv*-*-elf*, >> according following rules: >> > > I find the other_cond support a

Re: [PATCH 2/2] RISC-V: Implement TARGET_COMPUTE_MULTILIB

On Wed, Jul 21, 2021 at 2:28 AM Kito Cheng wrote: > Use TARGET_COMPUTE_MULTILIB to search the multi-lib reuse for > riscv*-*-elf*, > according following rules: > I find the other_cond support a bit confusing. Is this for -mcmodel perhaps? Why not just say that if so? match_score: weigth ->

Re: [PATCH] Fix SFmode subreg of DImode and TImode

On Tue, Sep 7, 2021 at 12:12 AM Michael Meissner via Gcc-patches < gcc-patches@gcc.gnu.org> wrote: > This patch fixes the breakage in the PowerPC due to a recent change in > SUBREG > behavior. While it is arguable that the patch that caused the breakage > should > be reverted, this patch should

[PATCH] RISC-V: Pattern name fix mul*3_highpart -> smul*3_highpart.

From: Geng Qi No known code changes, just fixes an inconsistency that was noticed. Committed. Jim gcc/ * config/riscv/riscv.md (mulv4): Call gen_smul3_highpart. (mulditi3): Call muldi3_highpart. (muldi3_highpart): Rename to muldi3_highpart. (mulsidi3):

Re: [RFC PATCH 0/8] RISC-V: Bit-manipulation extension.

On Tue, Sep 28, 2021 at 3:05 PM Christoph Muellner < cmuell...@ventanamicro.com> wrote: > We talked about this in the T meeting on Monday. > Philipp Tomsich mentioned, that he has a patchset from earlier this > year, which adds support for Zbs. > He proposed to rebase it and send it to the list

Re: [RFC PATCH 0/8] RISC-V: Bit-manipulation extension.

On Mon, Sep 27, 2021 at 4:20 AM Christoph Muellner < cmuell...@ventanamicro.com> wrote: > In case somebody wants to test this patchset, a patchset for Binutils > is required as well. > AFAIK here would be the Binutils branch with the required changes: > >

Re: [RFC PATCH 0/8] RISC-V: Bit-manipulation extension.

On Thu, Sep 23, 2021 at 12:57 AM Kito Cheng wrote: > Bit manipulation extension[1] is finishing the public review and waiting > for > the rest of the ratification process, I believe that will become a ratified > extension soon, so I think it's time to submit to upstream for review now > :) > We

Re: [PATCH] RISC-V: Pattern name fix mulm3_highpart -> smulm3_highpart.

On Mon, Sep 27, 2021 at 4:38 AM Geng Qi via Gcc-patches < gcc-patches@gcc.gnu.org> wrote: > gcc/ChangeLog: > * config/riscv/riscv.md > (muldi3_highpart): Rename to muldi3_highpart. > (mulditi3): Emit muldi3_highpart. > (mulsi3_highpart): Rename to mulsi3_highpart.

Re: [PATCH] configure: Update --help output for --with-multilib-list

On Fri, Sep 17, 2021 at 4:39 AM Jonathan Wakely via Gcc-patches < gcc-patches@gcc.gnu.org> wrote: > The list of architectures that support the option is incomplete. > > gcc/ChangeLog: > > * configure.ac: Fix --with-multilib-list description. > * configure: Regenerate. > > OK for

Re: RISCV: Add zmmul extension

On Wed, Oct 27, 2021 at 12:14 AM Kito Cheng wrote: > Otherwise it is LGTM, but I'm just surprised it's still 0.1 and not frozen > yet. > We should have binutils support first before we have gcc support. Otherwise that may lead to binutils errors later when zmmul gets passed down to binutils. I

Re: [PATCH 1/2] RISC-V: Add arch flags for T-HEAD.

On Tue, Jul 13, 2021 at 11:06 AM Palmer Dabbelt wrote: > Is there are documentation as to what this "theadc" extension is? > The best doc I know of is https://github.com/isrc-cas/c910-llvm The README is in Chinese, but google translate does a decent job on it. If you want more details, you

[PATCH] Update my email address.

riscv port Andrew Waterman -riscv port Jim Wilson +riscv port Jim Wilson rs6000/powerpc portDavid Edelsohn rs6000/powerpc portSegher Boessenkool rs6000 vector extnsAldy Hernandez

Re: [RFC][PATCH] c++/46476 - implement -Wunreachable-code-return

On Mon, Nov 29, 2021 at 5:21 PM Martin Sebor via Gcc-patches < gcc-patches@gcc.gnu.org> wrote: > There are some other "unusual" cases worth a look, such as missing > context of any kind except for like and column: > > elfnn-riscv.c:3346:7: warning: statement after return is not reachable >

Re: [PATCH v4][GCC13] RISC-V: Provide `fmin'/`fmax' RTL patterns

On Tue, Feb 8, 2022 at 4:35 AM Maciej W. Rozycki wrote: > gcc/ > * config/riscv/riscv.md (UNSPEC_FMIN, UNSPEC_FMAX): New > constants. > (fmin3, fmax3): New insns. > ... I tried testing on some of the hardware I have. Both the HiFive Unleashed (2018) and HiFive

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