[Bug middle-end/113066] Returning from a function marked noreturn allows execution to fall-through

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113066 Luke Geeson changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug translation/113066] New: Returning from a function marked noreturn allows execution to fall-through

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113066 Bug ID: 113066 Summary: Returning from a function marked noreturn allows execution to fall-through Product: gcc Version: 14.0 Status: UNCONFIRMED Severity:

[Bug target/111235] [Armv7-a]: Control-dependency between atomic accesses removed by -O1.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111235 --- Comment #5 from Luke Geeson --- Thank you for fixing this, Wilco! I will now test this bug using the code emitted by Godbolt. Consider again the same source program. When run through gcc with the same flags we get the ARM assembly test:

[Bug target/111235] [Armv7-a]: Control-dependency between atomic accesses removed by -O1.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111235 --- Comment #4 from Luke Geeson --- Hi there, Apologies here you go: https://github.com/llvm/llvm-project/issues/65106

[Bug translation/111416] New: [Armv7/v8 Mixing Bug]: 64-bit Sequentially Consistent Load can be Reordered before Store of RMW when v7 and v7 Implementations are Mixed

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111416 Bug ID: 111416 Summary: [Armv7/v8 Mixing Bug]: 64-bit Sequentially Consistent Load can be Reordered before Store of RMW when v7 and v7 Implementations are Mixed Product:

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #18 from Luke Geeson --- Indeed that is a plus - I have 167k concurrency tests that I feed through LLVM/GCC -O1/2/3/fast and for GCC -Og that test compilation from the C/C++ to PPC memory models. If you are interested I can provide

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 Luke Geeson changed: What|Removed |Added Resolution|--- |INVALID Status|NEW

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #15 from Luke Geeson --- I am sorry to you all - I have wasted your time. It was a bug in the translation tool. In the future I will make absolutely sure that I check everything before submitting a bug - this is an embarrassing

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #13 from Luke Geeson --- Please bear with me whilst I figure out what has happened here.

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #11 from Luke Geeson --- I'm using `powerpc64le-linux-gnu-objdump -Dr --disassemble --section=.text --no-show-raw-insn`. installed using `binutils-powerpc64le-linux-gnu` under Ubuntu 20:04 (in a docker container running on an Arm

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #9 from Luke Geeson --- apologies typos: bc -> bee bee -> beq

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #8 from Luke Geeson --- I have not, but I will contact him and link this discussion. In the meantime, I read that page and provide some more testing. Consider the passage: ``` bc;isync: this is a very low-overhead and very weak form

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #6 from Luke Geeson --- Apologies - I've been thinking in syncs and fences too much! Yes I mean `lwsync`, for clarity I repeat the above so you know it is the correct fix: ``` lukegeeson@machine:~/Dev/tv-dev/herdtools7$ cat

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #4 from Luke Geeson --- Add Wilco also addressed this for AArch64 in GCC: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108891

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #3 from Luke Geeson --- According to the latest C/C++ and PPC models, yes. If x was non-atomic, then this would be a racy (UB) test, but making x atomic with relaxed order is well-defined according to the C model (and therefore

[Bug target/111246] PPC64 Sequentially Consistent Load allows Reordering of Stores

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 --- Comment #1 from Luke Geeson --- Edit: The godbolt link points to the same bug in LLVM I am reporting, here is the GCC godbolt link https://godbolt.org/z/Tan5jrvKa

[Bug target/111246] New: PPC64 Sequentially Consistent Load allows Reordering of Stores

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246 Bug ID: 111246 Summary: PPC64 Sequentially Consistent Load allows Reordering of Stores Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug translation/111235] [Armv7-a]: Control-dependency between atomic accesses removed by -O1.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111235 --- Comment #1 from Luke Geeson --- Correction We will follow up by reporting the bug for GCC. -> We have reported this in LLVM as well

[Bug translation/111235] New: [Armv7-a]: Control-dependency between atomic accesses removed by -O1.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111235 Bug ID: 111235 Summary: [Armv7-a]: Control-dependency between atomic accesses removed by -O1. Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug rtl-optimization/110573] branch delay slots are not filled with atomic stores

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110573 --- Comment #5 from Luke Geeson --- For the record the %registers are symbolic - simply replace them with concrete ones containing the location x,y,etc...

[Bug rtl-optimization/110573] branch delay slots are not filled with atomic stores

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110573 --- Comment #4 from Luke Geeson --- Ah so since atomics are treated as volatile (like LLVM) instructions that access them cannot inhabit a delay slot. Is it still valid to treat atomics as volatile? Consider the following MIPS litmus test: ```

[Bug middle-end/110573] MIPS64: Enhancement PR of load of pointer to atomic

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110573 --- Comment #1 from Luke Geeson --- My apologies - I should have put the ld on the line with L7: ``` .L7:ld $3,%got_disp(P1_r0)($5). ```

[Bug middle-end/110573] New: MIPS64: Enhancement PR of load of pointer to atomic

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110573 Bug ID: 110573 Summary: MIPS64: Enhancement PR of load of pointer to atomic Product: gcc Version: 13.1.0 Status: UNCONFIRMED Keywords: missed-optimization Severity: