[Bug target/106585] RISC-V: Mis-optimized code gen for zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585 --- Comment #11 from Jeffrey A. Law --- Coming back to this. WRT extension elimination. I've been pondering if we want a late pass to do a bit of this that can't be handled by REE. So let's take the case of a Zbs instruction operating on a

[Bug target/106585] RISC-V: Mis-optimized code gen for zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585 --- Comment #10 from palmer at gcc dot gnu.org --- (In reply to Andrew Waterman from comment #9) > On Wed, Dec 7, 2022 at 7:02 PM palmer at gcc dot gnu.org via Gcc-bugs > wrote: > > > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585 > > >

[Bug target/106585] RISC-V: Mis-optimized code gen for zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585 --- Comment #9 from Andrew Waterman --- On Wed, Dec 7, 2022 at 7:02 PM palmer at gcc dot gnu.org via Gcc-bugs wrote: > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585 > > palmer at gcc dot gnu.org changed: > >What|Removed

Re: [Bug target/106585] RISC-V: Mis-optimized code gen for zbs

On Wed, Dec 7, 2022 at 7:02 PM palmer at gcc dot gnu.org via Gcc-bugs wrote: > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585 > > palmer at gcc dot gnu.org changed: > >What|Removed |Added >

[Bug target/106585] RISC-V: Mis-optimized code gen for zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585 palmer at gcc dot gnu.org changed: What|Removed |Added CC||palmer at gcc dot gnu.org

[Bug target/106585] RISC-V: Mis-optimized code gen for zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585 --- Comment #7 from Jeffrey A. Law --- Raphael and I are poking at this a bit. I can't convince myself that it's actually safe to use GPR for the bit manipulation patterns. For rv64 I'm pretty sure the b* instructions are operating on 64bit

[Bug target/106585] RISC-V: Mis-optimized code gen for zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585 Andrew Pinski changed: What|Removed |Added Last reconfirmed||2022-08-11 Ever confirmed|0

[Bug target/106585] RISC-V: Mis-optimized code gen for zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585 --- Comment #5 from Kito Cheng --- bset generated after change X to GPR for most zbs pattern: ``` foo: bseta1,x0,a1 andna0,a0,a1 sext.w a0,a0 ret ```

[Bug target/106585] RISC-V: Mis-optimized code gen for zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585 --- Comment #4 from Kito Cheng --- > It uses X iterator here instead of GPR, hmmm ... I think that because we have w-variant before, so use X rather than GPR here, but apparently we should revise this.

[Bug target/106585] RISC-V: Mis-optimized code gen for zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585 --- Comment #3 from Andrew Pinski --- (define_insn "*bset" [(set (match_operand:X 0 "register_operand" "=r") (ior:X (ashift:X (const_int 1) (match_operand:QI 2 "register_operand" "r"))

[Bug target/106585] RISC-V: Mis-optimized code gen for zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585 --- Comment #2 from Andrew Pinski --- One issue is RV32i_zbb produces: (insn 8 4 9 2 (set (reg:SI 78) (ashift:SI (const_int 1 [0x1]) (subreg:QI (reg/v:SI 76 [ rs2 ]) 0))) "t6.c":3:20 323 {*bsetsi_1} (expr_list:REG_DEAD

[Bug target/106585] RISC-V: Mis-optimized code gen for zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585 --- Comment #1 from Andrew Pinski --- Interesting rv32i_zbb produces: foo: bclra0,a0,a1 ret

[Bug target/106585] RISC-V: Mis-optimized code gen for zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585 Andrew Pinski changed: What|Removed |Added Severity|normal |enhancement