[Bug target/112817] RISC-V: RVV: provide attribute riscv_rvv_vector_bits for VLS codegen
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817 --- Comment #15 from Vineet Gupta --- (In reply to Vineet Gupta from comment #14) > 2. implement gcc toggle -mrvv-vector-bits=zvl which essentially copies the > xxx from -march string Done: commit 0a01d1232ff0a8b094270fbf45c9fd0ea46df19f Author: Pan Li Date: Fri Feb 23 15:37:28 2024 +0800 RISC-V: Introduce gcc option mrvv-vector-bits for RVV This patch would like to introduce one new gcc option for RVV. To appoint the bits size of one RVV vector register. Valid arguments to '-mrvv-vector-bits=' are: * scalable * zvl The scalable will pick up the zvl*b in the march as the minimal vlen. For example, the minimal vlen will be 512 when march=rv64gcv_zvl512b and mrvv-vector-bits=scalable. The zvl will pick up the zvl*b in the march as exactly vlen. For example, the vlen will be 1024 exactly when march=rv64gcv_zvl1024b and mrvv-vector-bits=zvl. The internal option --param=riscv-autovec-preference will be replaced by option -mrvv-vector-bits. Aka: * -mrvv-vector-bits=scalable indicates --param=riscv-autovec-preference=scalable * -mrvv-vector-bits=zvl indicates --param=riscv-autovec-preference=fixed-vlmax You can also take -fno-tree-vectorize for --param=riscv-autovec-preference=none. The internal option --param=riscv-autovec-preference is unavailable after this patch.
[Bug target/112817] RISC-V: RVV: provide attribute riscv_rvv_vector_bits for VLS codegen
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817 Vineet Gupta changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Ever confirmed|0 |1 Last reconfirmed||2024-03-06 --- Comment #14 from Vineet Gupta --- To summarize this needs following 3 things 1. preprocessor macro __riscv_v_fixed_vlen if -march has explicit xxxvl specified 2. implement gcc toggle -mrvv-vector-bits=zvl which essentially copies the xxx from -march string 3. Implement attribute riscv_rvv_vector_bits to specify vector length for user types: cfr. https://godbolt.org/z/5Pc4PzPvs, https://godbolt.org/z/9hdMqh3jf, https://godbolt.org/z/9WKM8s5rq
[Bug target/112817] RISC-V: RVV: provide attribute riscv_rvv_vector_bits for VLS codegen
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817 --- Comment #13 from Vineet Gupta --- Yeah Greg from Rivos started working on it. He'll update here as he makes progress.
[Bug target/112817] RISC-V: RVV: provide attribute riscv_rvv_vector_bits for VLS codegen
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817 --- Comment #12 from JuzheZhong --- Hi, Vineet. Are you going to support VLS compile option and attributes? If not, I can ask other RISC-V folks to do that. Thanks.
[Bug target/112817] RISC-V: RVV: provide attribute riscv_rvv_vector_bits for VLS codegen
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817 --- Comment #11 from Andrew Pinski --- (In reply to Vineet Gupta from comment #9) > I was looking for a new entry in gcc/c-family/c-attribs.cc or would be > somewhere else. It would more likely be in config/riscv/riscv.cc defined in riscv_attribute_table.
[Bug target/112817] RISC-V: RVV: provide attribute riscv_rvv_vector_bits for VLS codegen
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817 --- Comment #10 from JuzheZhong --- Yes. I haven't support VLS attributes. I guess kito may have some ideas.
