Re: [PING] [PATCH] Fix asm X constraint (PR inline-asm/59155)

On 06/21/16 00:06, Jeff Law wrote: > On 06/09/2016 10:45 AM, Jakub Jelinek wrote: >> On Thu, Jun 09, 2016 at 06:43:04PM +0200, Jakub Jelinek wrote: >>> Yes, I'm all in favor in disabling X constraint for inline asm. >>> Especially if people actually try to print it as well, rather than >>> make it

[PATCH,rs6000] Add support for HAVE_AS_POWER9

A "#define HAVE_AS_POWER9" or "#undef HAVE_AS_POWER9" preprocessor directive is emitted into the $GCC_BUILD/gcc/auto-host.h file at configuration time, depending on whether the available assembler supports the Power9 instruction set. This patch arranges to disable Power9-specific compiler

Fix ICE on conditional expression between DFP and non-DFP float (PR c/71601)

A conditional expression between DFP and non-DFP floating-point produces an ICE. This patch fixes this by making build_conditional_expr return early when c_common_type produces an error. Bootstrapped with no regressions on x86_64-pc-linux-gnu. Applied to mainline. gcc/c: 2016-06-20 Joseph

Re: [PATCH, vec-tails 01/10] New compiler options

On 06/17/2016 04:41 AM, Ilya Enkovich wrote: 1. You've got 3 modes for epilogue vectorization. Is this an artifact of not really having good heuristics yet for which mode to apply to a particular loop at this time? 2. Similarly for cost models. All three modes are profitable in different

Re: [PATCH] PR52665 do not let .ident confuse assembler scan tests

On 06/18/2016 01:31 PM, Bernhard Reutner-Fischer wrote: A branch with a name matching scan-assembler pattern triggers inappropriate FAIL. E.g. branch fixups-testsuite and - gcc.target/i386/pr65871-?.c (scan-assembler-not "test") - gcc.target/i386/pr41442.c (scan-assembler-times "test|cmp" 2)

Re: [PATCH] Give up instead of ICE on invalid stringops attributes (PR tree-optimization/71588)

On 06/20/2016 12:35 PM, Jakub Jelinek wrote: Hi! If users use attributes like const or pure incorrectly on stringops builtins, the tree-ssa-strlen.c pass can ICE, because it expects it can e.g. replace a strcpy (which should not be const or pure) with memcpy (which also shouldn't be const/pure)

Re: [PING] [PATCH] Fix asm X constraint (PR inline-asm/59155)

On 06/09/2016 10:45 AM, Jakub Jelinek wrote: On Thu, Jun 09, 2016 at 06:43:04PM +0200, Jakub Jelinek wrote: Yes, I'm all in favor in disabling X constraint for inline asm. Especially if people actually try to print it as well, rather than make it unused. That is a sure path to ICEs. Though,

Re: RFC: pass to warn on questionable uses of alloca().

On 06/18/2016 05:55 PM, Martin Sebor wrote: I think detecting potentially problematic uses of alloca would be useful, especially when done in an intelligent way like in your patch (as opposed to simply diagnosing every call to the function regardless of the value of its argument). At the same

Re: RFC: pass to warn on questionable uses of alloca().

On 06/20/2016 08:56 AM, Joseph Myers wrote: On Sat, 18 Jun 2016, Martin Sebor wrote: the function regardless of the value of its argument). At the same time, it seems that an even more reliable solution than pointing out potentially unsafe calls to the function and relying on users to modify

Re: [PATCH] Don't run -fself-test with -E (PR rtl-optimization/71591)

On 06/20/2016 12:38 PM, Jakub Jelinek wrote: Hi! As mentioned in the PR, with -E (C family and Fortran FEs, others don't preprocess) ask the middle-end not to initialize the backends, so running e.g. RTL tests leads to ICEs, e.g. pc_rtx and many other things just aren't initialized. 2016-06-20

Re: [PATCH] Fix warn uninit ICE with _Complex exprs (PR middle-end/71581)

On 06/20/2016 12:45 PM, Jakub Jelinek wrote: Hi! On the following testcase we ICE during warn_uninit. Normally, has_undefined_value_p returns false for anonymous SSA_NAMEs, so NULL expr/var aren't a problem. If t has a COMPLEX_EXPR as def-stmt, where the first operand is some scalar var's (D)

Re: [PATCH] x86-64: Load external function address via GOT slot

On Mon, Jun 20, 2016 at 12:46 PM, Richard Sandiford wrote: > Uros Bizjak writes: >> On Mon, Jun 20, 2016 at 9:19 PM, H.J. Lu wrote: >>> On Mon, Jun 20, 2016 at 12:13 PM, Uros Bizjak wrote: On Mon, Jun

Re: [PATCH 6/6] loop-iv.c: make cond_list a vec

tbsaunde+...@tbsaunde.org writes: > diff --git a/gcc/loop-iv.c b/gcc/loop-iv.c > index 57fb8c1..21c3180 100644 > --- a/gcc/loop-iv.c > +++ b/gcc/loop-iv.c > @@ -1860,7 +1860,6 @@ simplify_using_initial_values (struct loop *loop, enum > rtx_code op, rtx *expr) > { >bool expression_valid; >

Committed, CRIS: fix target/71571, delay-slot nop in PIC MI thunk

Committed to trunk. Apparently the -fno-inline is key to keeping the test-case small. Thanks go to the reporter, David B. Robins. gcc: PR target/71571 * config/cris/cris.c (cris_asm_output_mi_thunk): Add missing "ba" delay-slot "nop" for PIC with CRIS v32. Also add

Re: [PATCH 5/6] make pattern_regs a vec

tbsaunde+...@tbsaunde.org writes: > @@ -265,18 +261,16 @@ store_ops_ok (const_rtx x, int *regs_set) > /* Returns a list of registers mentioned in X. > FIXME: A regset would be prettier and less expensive. */ > > -static rtx_expr_list * > -extract_mentioned_regs (rtx x) > +static void >

Re: [PATCH] x86-64: Load external function address via GOT slot

Uros Bizjak writes: > On Mon, Jun 20, 2016 at 9:19 PM, H.J. Lu wrote: >> On Mon, Jun 20, 2016 at 12:13 PM, Uros Bizjak wrote: >>> On Mon, Jun 20, 2016 at 7:05 PM, H.J. Lu wrote: Hi, This patch

[PATCH, i386, AVX-512ER] vrsqrt28ps auto generation

Hi! This patch emits vrsqrt28ps instruction in ix86_emit_swsqrtsf for recip case and vrcp28ps(vrsqrt28ps(a)) for !recip. Regtested using various benchmarks on a AVX-512ER machine. OK for trunk? gcc/ * config/i386/i386.c (ix86_emit_swsqrtsf): Emit vrsqrt28ps. *

Re: [PATCH 0/7] remove targets obsoleted in gcc 6

On 06/19/2016 11:47 PM, tbsaunde+...@tbsaunde.org wrote: From: Trevor Saunders Hi, later than I hoped, but here's the series to remove the targets obsoleted during gcc 6. I built and regtested the series as one patch on x86_64-linux-gnu without regressions, ok?

Re: [PATCH, i386, AVX-512ER] vrsqrt28ps auto generation

On Mon, Jun 20, 2016 at 9:35 PM, Ilya Verbin wrote: > Hi! > > This patch emits vrsqrt28ps instruction in ix86_emit_swsqrtsf for recip case > and > vrcp28ps(vrsqrt28ps(a)) for !recip. > Regtested using various benchmarks on a AVX-512ER machine. OK for trunk? > > > gcc/ >

Re: [PATCH] x86-64: Load external function address via GOT slot

On Mon, Jun 20, 2016 at 9:19 PM, H.J. Lu wrote: > On Mon, Jun 20, 2016 at 12:13 PM, Uros Bizjak wrote: >> On Mon, Jun 20, 2016 at 7:05 PM, H.J. Lu wrote: >>> Hi, >>> >>> This patch implements the alternate code sequence recommended

Re: [PATCH] config-list.mk AIX update

On 06/20/2016 12:13 PM, David Edelsohn wrote: This patch removes obsolete AIX 4.3, 5.1 and 5.2 configurations and adds AIX 7.1 configuration. GCC does not yet differentiate AIX 7.2, so I did not include it. Okay? Thanks, David * config-list.mk: Remove rs6000-ibm-aix4.3, rs6000-ibm-aix5.1,

Re: [PATCH] x86-64: Load external function address via GOT slot

On Mon, Jun 20, 2016 at 12:13 PM, Uros Bizjak wrote: > On Mon, Jun 20, 2016 at 7:05 PM, H.J. Lu wrote: >> Hi, >> >> This patch implements the alternate code sequence recommended in >> >> https://groups.google.com/forum/#!topic/x86-64-abi/de5_KnLHxtI >> >>

Re: [PATCH] c++/60760 - arithmetic on null pointers should not be allowed in constant expressions

+ if (TREE_CODE (whole) == INDIRECT_REF + && integer_zerop (TREE_OPERAND (whole, 0)) + && !ctx->quiet) +error ("dereferencing a null pointer in %qE", orig_whole); + if (TREE_CODE (t) == INTEGER_CST + && TREE_CODE (TREE_TYPE (t)) == POINTER_TYPE + &&

Re: [PATCH] x86-64: Load external function address via GOT slot

On Mon, Jun 20, 2016 at 7:05 PM, H.J. Lu wrote: > Hi, > > This patch implements the alternate code sequence recommended in > > https://groups.google.com/forum/#!topic/x86-64-abi/de5_KnLHxtI > > to load external function address via GOT slot with > > movq func@GOTPCREL(%rip),

Re: [PATCH] Fix ix86_fp_cmp_code_to_pcmp_immediate (PR target/71559)

On Mon, Jun 20, 2016 at 09:04:26PM +0200, Uros Bizjak wrote: > OK for mainline and release branches after a week or so without > problems in mainline. Ok, thanks. > (I tried to review usage of all those bits, LGTM, but mistakes can happen...) I really hope the testcase should double check all

Re: [PATCH, i386, AVX-512ER] vrcp28ps auto generation

On Mon, Jun 20, 2016 at 7:09 PM, Ilya Verbin wrote: > Hi! > > This patch emits vrcp28ps and vmulps istructions for ix86_emit_swdivsf. > The relative error is < 2^-23, so no additional iteration is necessary. > Regtested using various benchmarks on a AVX-512ER machine. OK for

Re: [PATCH] Fix ix86_fp_cmp_code_to_pcmp_immediate (PR target/71559)

On Mon, Jun 20, 2016 at 8:31 PM, Jakub Jelinek wrote: > Hi! > > As discussed in the PR, this function is missing a lot of comparison codes > that can validly appear there, and gives wrong values for the others > except for NE. > This patch makes those values match what %D3 emits

Re: [PATCH] PR target/71549: Convert V1TImode register to TImode in debug insn

On Mon, Jun 20, 2016 at 10:31 AM, Ilya Enkovich wrote: > On 20 Jun 09:45, H.J. Lu wrote: >> On Mon, Jun 20, 2016 at 7:30 AM, Ilya Enkovich >> wrote: >> > 2016-06-20 16:39 GMT+03:00 Uros Bizjak : >> >> On Mon, Jun 20, 2016 at

[PATCH] Fix warn uninit ICE with _Complex exprs (PR middle-end/71581)

Hi! On the following testcase we ICE during warn_uninit. Normally, has_undefined_value_p returns false for anonymous SSA_NAMEs, so NULL expr/var aren't a problem. If t has a COMPLEX_EXPR as def-stmt, where the first operand is some scalar var's (D) SSA_NAME and the second operand is 0, which

[PATCH] Don't run -fself-test with -E (PR rtl-optimization/71591)

Hi! As mentioned in the PR, with -E (C family and Fortran FEs, others don't preprocess) ask the middle-end not to initialize the backends, so running e.g. RTL tests leads to ICEs, e.g. pc_rtx and many other things just aren't initialized. 2016-06-20 Jakub Jelinek PR

[PATCH] Give up instead of ICE on invalid stringops attributes (PR tree-optimization/71588)

Hi! If users use attributes like const or pure incorrectly on stringops builtins, the tree-ssa-strlen.c pass can ICE, because it expects it can e.g. replace a strcpy (which should not be const or pure) with memcpy (which also shouldn't be const/pure) etc. The patch just pretends the calls aren't

[PATCH] Fix ix86_fp_cmp_code_to_pcmp_immediate (PR target/71559)

Hi! As discussed in the PR, this function is missing a lot of comparison codes that can validly appear there, and gives wrong values for the others except for NE. This patch makes those values match what %D3 emits for the AVX vcmp*p{s,d}, there is some controversy on whether UN{GT,GE,LT,LE,EQ}

Re: [PATCH] config-list.mk AIX update

Hi David, On Mon, 2016-06-20 14:13:33 -0400, David Edelsohn wrote: > This patch removes obsolete AIX 4.3, 5.1 and 5.2 configurations and > adds AIX 7.1 configuration. GCC does not yet differentiate AIX 7.2, > so I did not include it. > > Okay? Of course, you're AIX

[PATCH] config-list.mk AIX update

This patch removes obsolete AIX 4.3, 5.1 and 5.2 configurations and adds AIX 7.1 configuration. GCC does not yet differentiate AIX 7.2, so I did not include it. Okay? Thanks, David * config-list.mk: Remove rs6000-ibm-aix4.3, rs6000-ibm-aix5.1, rs6000-ibm-aix5.2. Rename rs6000-ibm-aix6.0 as

Re: [Patch, testsuite] Mark some more tests as UNSUPPORTED for avr

On Jun 20, 2016, at 2:13 AM, Senthil Kumar Selvaraj wrote: > > This patch fixes some bogus failures for the avr target by requiring > int32plus or ptr32plus support. > > Ok for trunk? Ok. If you feel comfortable making these sort of "obvious" changes, you

Re: [PATCH] PR target/71549: Convert V1TImode register to TImode in debug insn

On 20 Jun 09:45, H.J. Lu wrote: > On Mon, Jun 20, 2016 at 7:30 AM, Ilya Enkovich wrote: > > 2016-06-20 16:39 GMT+03:00 Uros Bizjak : > >> On Mon, Jun 20, 2016 at 1:55 PM, H.J. Lu wrote: > >>> TImode register referenced in debug

Re: Update probabilities in predict.def to match reality

Hi, On 08/06/16 11:21, Andreas Schwab wrote: Jan Hubicka writes: Bootstrapped/regtested x86_64-linux, will commit it later today. FAIL: gcc.dg/tree-ssa/slsr-8.c scan-tree-dump-times optimized " w?* " 7 This fails for all arm and aarch64 targets as well since the

[PATCH, i386, AVX-512ER] vrcp28ps auto generation

Hi! This patch emits vrcp28ps and vmulps istructions for ix86_emit_swdivsf. The relative error is < 2^-23, so no additional iteration is necessary. Regtested using various benchmarks on a AVX-512ER machine. OK for trunk? gcc/ * config/i386/i386.c (ix86_emit_swdivsf): Emit vrcp28ps.

Re: [patch, avr] Fix PR30417: Wrap -Tdata into %{!Tdata:...}.

2016-06-20 16:36 GMT+03:00 Georg-Johann Lay : > This patch allows to specify -Tdata and -Ttext on the command line for MCUs > where the specs file sets these options. For -mmcu=atmega88 for example, > the respective specs reads: > > *link_data_start: > -Tdata 0x800100 > >

[PATCH] x86-64: Load external function address via GOT slot

Hi, This patch implements the alternate code sequence recommended in https://groups.google.com/forum/#!topic/x86-64-abi/de5_KnLHxtI to load external function address via GOT slot with movq func@GOTPCREL(%rip), %rax so that linker won't create an PLT entry for extern function address. Tested

Re: [PATCH 0/6] remove some usage of rtx_{insn,expr}_list

On 06/20/2016 12:22 PM, tbsaunde+...@tbsaunde.org wrote: In theory I would expect if anything this helps performance since it isn't necessary to malloc every time a node is added, however the data is less clear. Well, we have alloc pools for these lists, so a malloc is not needed for every

Re: [PATCH] PR target/71549: Convert V1TImode register to TImode in debug insn

On Mon, Jun 20, 2016 at 7:30 AM, Ilya Enkovich wrote: > 2016-06-20 16:39 GMT+03:00 Uros Bizjak : >> On Mon, Jun 20, 2016 at 1:55 PM, H.J. Lu wrote: >>> TImode register referenced in debug insn can be converted to V1TImode >>> by

Re: [Patch, Fortran] PR71194 - Fix ICE with pointer assignment

Dear Tobias, Impeccably done, as always :-) OK for trunk. Thanks for the patch. Cheers Paul On 20 June 2016 at 14:10, Tobias Burnus wrote: > Dear all, > > the issue occurs only if the RHS of a pointer assignment is a function and > the ICE is only triggered

Re: [PING] [PATCH] c/69507 - bogus warning: ISO C does not allow ‘__alignof__ (expression)’

Since this patch was committed, I am now seeing failures on: gcc.dg/gnu99-const-expr-1.c gcc.dg/gnu99-static-1.c (targets arm, aarch64, I don't think that it should matter?) Can you have a look? Sorry about that. I missed the test updates in my initial patch. I've committed them in r237606.

Re: RFC: pass to warn on questionable uses of alloca().

On Sat, 18 Jun 2016, Martin Sebor wrote: > the function regardless of the value of its argument). At > the same time, it seems that an even more reliable solution > than pointing out potentially unsafe calls to the function > and relying on users to modify their code to use malloc for >

Re: [PATCH] c/71552 - Confusing error for incorrect struct initialization

On Sat, 18 Jun 2016, Martin Sebor wrote: > The attached patch slightly changes the order in which initializers > are checked for type compatibility to issue the same error for static > initializers of incompatible types as for automatic objects, rather > than rejecting the former for their lack

Re: RFC: 2->2 combine patch

On Mon, Jun 20, 2016 at 02:39:06PM +0100, Kyrill Tkachov wrote: > >So I tried out the patch below. It decreases code size on most targets > >(mostly fixed length insn targets), and increases it a small bit on some > >variable length insn targets (doing an op twice, instead of doing it once > >and

Re: [PATCH] PR target/71549: Convert V1TImode register to TImode in debug insn

2016-06-20 16:39 GMT+03:00 Uros Bizjak : > On Mon, Jun 20, 2016 at 1:55 PM, H.J. Lu wrote: >> TImode register referenced in debug insn can be converted to V1TImode >> by scalar to vector optimization. We need to convert a debug insn if >> it has a

Re: [PATCH]Fix scan-tree-dump-times syntax errors in gcc.dg/tree-ssa/attr-hotcold-2.c

On Mon, Jun 20, 2016 at 03:07:20PM +0100, Renlin Li wrote: > Okay to commit? > > Regards, > Renlin > > gcc/testsuite/ChangeLog: > > 2016-06-20 Renlin Li > > * gcc.dg/tree-ssa/attr-hotcold-2.c: Fix syntax errors. This is obvious. Please check it in. Though, it

[PATCH]Fix scan-tree-dump-times syntax errors in gcc.dg/tree-ssa/attr-hotcold-2.c

Hi, This is a simple patch to fix the syntax errors in dg-final directive lines within this test case. According to the documentation, the syntax of this directive should be: '''scan-tree-dump-times regex num suffix [{ target/xfail selector }]''' Now the test case compilers Okay in arm

Re: [AArch64] Give some new costs for Cortex-A53 floating-point operations

On 20/06/16 14:57, James Greenhalgh wrote: > > Hi, > > As recently done for Cortex-A57 [1], this patch rebases the floating-point > cost table for Cortex-A53 to be relative to the cost of a floating-point move. > I wrote a little more on the justification for doing this in the other patch, > but

[AArch64] Give some new costs for Cortex-A53 floating-point operations

Hi, As recently done for Cortex-A57 [1], this patch rebases the floating-point cost table for Cortex-A53 to be relative to the cost of a floating-point move. I wrote a little more on the justification for doing this in the other patch, but in summary this is what other targets and sub-targets

Re: [PING 2, PATCH] Remove xfail from thread_local-order2.C.

Patch: https://gcc.gnu.org/ml/gcc-patches/2016-04/msg01587.html On Wed, Jan 27, 2016 at 10:39:44AM +0100, Dominik Vogt wrote: > g++.dg/tls/thread_local-order2.C no longer fail with Glibc-2.18 or > newer since this commit: > > 2014-08-01 Zifei Tong > > *

Re: [PATCH] PR target/71549: Convert V1TImode register to TImode in debug insn

On Mon, Jun 20, 2016 at 1:55 PM, H.J. Lu wrote: > TImode register referenced in debug insn can be converted to V1TImode > by scalar to vector optimization. We need to convert a debug insn if > it has a variable in a TImode register. > > Tested on x86-64. OK for trunk?

Re: RFC: 2->2 combine patch

Hi Segher, On 17/06/16 01:07, Segher Boessenkool wrote: On Fri, Jun 10, 2016 at 11:20:22AM +0200, Richard Biener wrote: With the proposed cost change for vector construction we will end up vectorizing the testcase in PR68961 again (on x86_64 and likely on ppc64le as well after that target gets

[patch, avr] Fix PR30417: Wrap -Tdata into %{!Tdata:...}.

This patch allows to specify -Tdata and -Ttext on the command line for MCUs where the specs file sets these options. For -mmcu=atmega88 for example, the respective specs reads: *link_data_start: -Tdata 0x800100 and the patch changes this to *link_data_start: %{!Tdata:-Tdata

Re: [Patch AArch64] Add some more missing intrinsics

On 13/06/16 17:31, James Greenhalgh wrote: > > Hi, > > Inspired by Jiong's recent work, here are some more missing intrinsics, > and a smoke test for each of them. > > This patch covers: > > vcvt_n_f64_s64 > vcvt_n_f64_u64 > vcvt_n_s64_f64 > vcvt_n_u64_f64 > vcvt_f64_s64 >

PING^3: [PATCH] PR33661 Fix problem with register asm in templates

Hi Jason, could you please have a look? https://gcc.gnu.org/ml/gcc-patches/2015-06/msg00904.html Thanks! -Andreas-

Re: [PATCH] Giant concepts patch

On Fri, Mar 25, 2016 at 1:33 AM, Andrew Sutton wrote: > I'll just leave this here... > > This patch significantly improves performance with concepts (i.e., > makes it actually usable for real systems) and improves the > specificity of diagnostics when constraints fail.

Re: [Patch AArch64] Fixup to fcvt patterns added in r237200

On 10/06/16 13:29, James Greenhalgh wrote: > > Hi, > > My autotester picked up some issues with the vcvt{ds}_n_* intrinsics > added in r237200. > > The iterators in this pattern do not resolve, as they have not been > explicitly tied to the mode iterator (rather than the code iterator) > used

Re: [AArch64] Give some new costs for Cortex-A57 floating-point operations

On 03/06/16 09:35, James Greenhalgh wrote: > > Hi, > > This patch rebases the floating-point cost table for Cortex-A57 to be > relative to the cost of a floating-point move. This in response to this > feedback from Richard Sandiford [2] on Ramana's patch to calls.c [1] from > 2014: > > I

[Ada] Reimplementation of type invariants

This patch prevents the insertion of the invariant procedure declaration and body when the context is a generic unit. This ensures that generated code does not permiate the template. -- Source -- -- tester.ads package Tester is type Type_Id is (Ext_1_Id,

[Ada] Adapt treatment of inherited classwide pre/post to GNATprove

In GNATprove mode, inherited classwide pre/post are copied to the overriding subprogram declaration, so that GNATprove can find them to verify Liskov Substitution Principle on SPARK code. The copied pre/post are not turned into pragma checks anymore in GNATprove mode, so that they are added to the

[Ada] Always consider Linker_Options from package System

On full runtimes, this was always the case. On restricted one, force system to be in the closer of the program. No test for full runtimes (as no behaviour change). Tested on x86_64-pc-linux-gnu, committed on trunk 2016-06-20 Tristan Gingold * make.adb

[Ada] Handling of all-digits host names

In Get_Host_By_Name, do not treat a strings consisting of digits only as an IP address whose lookup should actually be done using Get_Host_By_Address. Tested on x86_64-pc-linux-gnu, committed on trunk 2016-06-20 Thomas Quinot * g-socket.adb (Is_IP_Address): A

Re: [PATCH 2/2][v3] Drop excess size used for run time allocated stack variables.

On 06/20/2016 02:19 PM, Dominik Vogt wrote: +/* PR/50938: Check that alloca () reserves the correct amount of stack space. + */ Same here really, even if it's only a test. In this case, the line gets too long with " */" appended. In that case we wrap before the last word. Bernd

Re: [PATCH 2/2][v3] Drop excess size used for run time allocated stack variables.

On Wed, Jun 08, 2016 at 01:21:09PM +0200, Bernd Schmidt wrote: > On 05/25/2016 03:32 PM, Dominik Vogt wrote: > > * explow.c (round_push): Use know adjustment. > > (allocate_dynamic_stack_space): Pass known adjustment to round_push. > >gcc/testsuite/ChangeLog > > > > I was thinking about

[avr, 6, 5, 4.9, committed] Backported PR target/71103

Applied backports to: v6: https://gcc.gnu.org/r237591 v5: https://gcc.gnu.org/r237593 v4.9: https://gcc.gnu.org/r237594 Johann gcc/ Backport from 2016-06-20 trunk r237589, r236558. PR target/71103 * config/avr/avr.md (movqi): Handle loading subreg:qi (const,

[Patch, Fortran] PR71194 - Fix ICE with pointer assignment

Dear all, the issue occurs only if the RHS of a pointer assignment is a function and the ICE is only triggered when a rank remapping is needed. gfc_conv_expr_descriptor calls for a expr2 gfc_conv_procedure_call, which sets "se.expr" to NULL_TREE - and the code later tries to access it. The code

Re: i386/prologues: ROP mitigation for normal function epilogues

Hi, On Fri, 17 Jun 2016, Bernd Schmidt wrote: > > The "0xe9 " essentially is the leave+return opcode, > > after all it jumps to them (let's ignore the possibility that the jump > > target address might contain a 0xc3 byte). So if the attacker finds > > some interesting gadget in I don't see

[PATCH] PR target/71549: Convert V1TImode register to TImode in debug insn

TImode register referenced in debug insn can be converted to V1TImode by scalar to vector optimization. We need to convert a debug insn if it has a variable in a TImode register. Tested on x86-64. OK for trunk? H.J. gcc/ PR target/71549 * config/i386/i386.c

Re: [PATCH v2, PING 1] Allocate constant size dynamic stack space in the prologue

On Fri, May 06, 2016 at 10:44:15AM +0100, Dominik Vogt wrote: > > diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c > > index 21f21c9..4d48afd 100644 > > --- a/gcc/cfgexpand.c > > +++ b/gcc/cfgexpand.c > ... > > @@ -1099,8 +1101,10 @@ expand_stack_vars (bool (*pred) (size_t), struct > >

Re: [Patch AArch64] Add some more missing intrinsics

On Mon, Jun 13, 2016 at 05:31:40PM +0100, James Greenhalgh wrote: > > Hi, > > Inspired by Jiong's recent work, here are some more missing intrinsics, > and a smoke test for each of them. > > This patch covers: > > vcvt_n_f64_s64 > vcvt_n_f64_u64 > vcvt_n_s64_f64 > vcvt_n_u64_f64 >

Re: [Patch AArch64] Fixup to fcvt patterns added in r237200

On Fri, Jun 10, 2016 at 01:29:39PM +0100, James Greenhalgh wrote: > > Hi, > > My autotester picked up some issues with the vcvt{ds}_n_* intrinsics > added in r237200. > > The iterators in this pattern do not resolve, as they have not been > explicitly tied to the mode iterator (rather than the

Re: [AArch64] Give some new costs for Cortex-A57 floating-point operations

On Fri, Jun 10, 2016 at 09:29:46AM +0100, James Greenhalgh wrote: > On Fri, Jun 03, 2016 at 09:35:50AM +0100, James Greenhalgh wrote: > > > > Hi, > > > > This patch rebases the floating-point cost table for Cortex-A57 to be > > relative to the cost of a floating-point move. This in response to

Re: [wwwdocs] Describe behavior of -flifetime-dse in class constructors

On Mon, 20 Jun 2016, Gerald Pfeifer wrote: > I know a short version of this was applied, but am wondering > whether to retain the example (and a note on -flifetime-dse=1), > both per the discussion in February? > > Want to make those enhancements? And here is one small change I just applied...

Re: [wwwdocs] Describe behavior of -flifetime-dse in class constructors

Hi Martin, On Wed, 17 Feb 2016, Martin Liška wrote: > On 02/17/2016 03:23 PM, Jakub Jelinek wrote: >> "has been" looks weird. I'd say that the C++ compiler is now more >> aggressive... > Sending v3. I know a short version of this was applied, but am wondering whether to retain the example (and

RE: [PATCH, fortran, v4] Use Levenshtein spelling suggestions in Fortran FE

From my point of view, would be really nice to have. Joost

Re: [PING] [PATCH] c/69507 - bogus warning: ISO C does not allow ‘__alignof__ (expression)’

On 4 June 2016 at 23:24, Martin Sebor wrote: > Ping: https://gcc.gnu.org/ml/gcc-patches/2016-05/msg02216.html > > > On 05/27/2016 11:34 AM, Martin Sebor wrote: >> >> The patch below adjusts the C alignof pedantic warning to avoid >> diagnosing the GCC extension (__alignof__) and

[PATCH 6/6] loop-iv.c: make cond_list a vec

From: Trevor Saunders gcc/ChangeLog: 2016-06-20 Trevor Saunders * loop-iv.c (simplify_using_initial_values): Make cond_list a vector. --- gcc/loop-iv.c | 55 ++- 1 file

[PATCH 1/6] make antic_stores a vec

From: Trevor Saunders gcc/ChangeLog: 2016-06-20 Trevor Saunders * store-motion.c (struct st_expr): Make antic_stores a vector. (st_expr_entry): Adjust. (free_st_expr_entry): Likewise.

[PATCH 5/6] make pattern_regs a vec

From: Trevor Saunders gcc/ChangeLog: 2016-06-20 Trevor Saunders * store-motion.c (struct st_expr): Make pattern_regs a vector. (st_expr_entry): Adjust. (store_ops_ok): Likewise. (extract_mentioned_regs):

[PATCH 4/6] make side_effects a vec

From: Trevor Saunders gcc/ChangeLog: 2016-06-20 Trevor Saunders * var-tracking.c (struct adjust_mem_data): Make side_effects a vector. (adjust_mems): Adjust. (adjust_insn): Likewise.

[PATCH 0/6] remove some usage of rtx_{insn,expr}_list

From: Trevor Saunders Hi, These few patches to get rid of rtx insn and expr lists should be pretty un controvertial. In each case the list is clearly used as a stack and using a vec as a stack is clearly the same. In theory I would expect if anything this helps

[PATCH 3/6] make stores rtx_insn_list a vec

From: Trevor Saunders gcc/ChangeLog: 2016-06-20 Trevor Saunders * gcse.c (struct ls_expr): Make stores field a vector. (ldst_entry): Adjust. (free_ldst_entry): Likewise. (print_ldst_list): Likewise.

[PATCH 2/6] remove unused loads rtx_insn_list

From: Trevor Saunders gcc/ChangeLog: 2016-06-20 Trevor Saunders * gcse.c (struct ls_expr): Remove loads field. (ldst_entry): Adjust. (free_ldst_entry): Likewise. (print_ldst_list): Likewise.

[PATCH][typo] alignement -> alignment

Hi all, Committing the attached typo fix as obvious (I believe "alignement" is the French form). Thanks, Kyrill 2016-06-20 Kyrylo Tkachov * params.def (PARAM_ALIGN_LOOP_ITERATIONS): Use "alignment" instead of "alignement". * tree.h (TYPE_ALIGN):

Re: [PATCH PR71347][Partial revert r235513]Compute cost for all uses in group

"Bin.Cheng" writes: >>> The test passes on aarch64, but fails on arm targets. Maybe that's >>> easier for Bin to reproduce? >> Hi all, >> Sorry for the inconvenience, I will have a look at the two targets. > Hmm, the failure is because post-increment is enabled in IVOPT on

[Patch, testsuite] Mark some more tests as UNSUPPORTED for avr

Hi, This patch fixes some bogus failures for the avr target by requiring int32plus or ptr32plus support. Ok for trunk? Regards Senthil gcc/testsuite/ChangeLog: 2016-06-20 Senthil Kumar Selvaraj * c-c++-common/pr68657-1.c: Require ptr32plus

Re: [PATCH PR71347][Partial revert r235513]Compute cost for all uses in group

On Mon, Jun 20, 2016 at 9:20 AM, Bin.Cheng wrote: > On Mon, Jun 20, 2016 at 9:18 AM, Christophe Lyon > wrote: >> On 18 June 2016 at 10:59, Andreas Schwab wrote: >>> Bin Cheng writes: >>> diff

Re: [PATCH] Change PRED_LOOP_EXIT from 92 to 85.

On 06/18/2016 06:24 AM, Andrew Pinski wrote: > This caused a 1% decrease of performance on coremarks on > aarch64-linux-gnu on ThunderX. > > Thanks, > Andrew Hi. It would be good if you will run your benchmark with -fprofile-generate and -fprofile-use -fdump-ipa-profile-details. After that,

Re: [PATCH PR71347][Partial revert r235513]Compute cost for all uses in group

On Mon, Jun 20, 2016 at 9:18 AM, Christophe Lyon wrote: > On 18 June 2016 at 10:59, Andreas Schwab wrote: >> Bin Cheng writes: >> >>> diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr71347.c >>>

Re: [PATCH PR71347][Partial revert r235513]Compute cost for all uses in group

On 18 June 2016 at 10:59, Andreas Schwab wrote: > Bin Cheng writes: > >> diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr71347.c >> b/gcc/testsuite/gcc.dg/tree-ssa/pr71347.c >> new file mode 100644 >> index 000..7e5ad49 >> --- /dev/null >> +++

[PATCH 5/7] remove m32-rtems support

From: Trevor Saunders libgcc/ChangeLog: 2016-06-20 Trevor Saunders * config.host: Remove m32r-rtems support. gcc/ChangeLog: 2016-06-20 Trevor Saunders * config.gcc: Remove m32r-rtems

[PATCH 6/7] remove avr-rtems support

From: Trevor Saunders contrib/ChangeLog: 2016-06-20 Trevor Saunders * config-list.mk: Stop testing avr-rtems. libgcc/ChangeLog: 2016-06-20 Trevor Saunders * config.host: Remove support for

[PATCH 3/7] remove knetbsd support

From: Trevor Saunders gcc/ChangeLog: 2016-06-20 Trevor Saunders * config.gcc: Remove support for knetbsd. * configure.ac: Likewise. * config/i386/knetbsd-gnu.h: Remove. * config/i386/knetbsd-gnu64.h: Remove.

[PATCH 4/7] remove h8300-rtems support

From: Trevor Saunders contrib/ChangeLog: 2016-06-20 Trevor Saunders * config-list.mk: Remove h8300-rtems support. libgcc/ChangeLog: 2016-06-20 Trevor Saunders * config.host: Remove

[PATCH 2/7] remove support for targeting openbsd 2 or 3

From: Trevor Saunders contrib/ChangeLog: 2016-06-20 Trevor Saunders * config-list.mk: Stop testing openbsd3.0. libgcc/ChangeLog: 2016-06-20 Trevor Saunders * config.host: Remove support

[PATCH 1/7] remove support for the interix target

From: Trevor Saunders contrib/ChangeLog: 2016-06-20 Trevor Saunders * config-list.mk: Remove interix target. libgcc/ChangeLog: 2016-06-20 Trevor Saunders * config.host: Remove interix

[PATCH 0/7] remove targets obsoleted in gcc 6

From: Trevor Saunders Hi, later than I hoped, but here's the series to remove the targets obsoleted during gcc 6. I built and regtested the series as one patch on x86_64-linux-gnu without regressions, ok? Trev Trevor Saunders (7): remove support for the interix

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