Re: [PATCH] RISC-V: Document the medlow and medany code models

I have to disagree. It's standard to not hyphenate an adverb-adjective compound, since they tend not to be ambiguous. But if the standard in the GCC documentation is to hyphenate, I will not stand in the way! On Tue, Oct 31, 2017 at 8:47 PM, Sandra Loosemore wrote: >

Re: [PATCH] RISC-V: Document the medlow and medany code models

On 10/31/2017 06:54 PM, Palmer Dabbelt wrote: This documentation is patterned off the aarch64 -mcmodel documentation. gcc/ChangeLog: 2017-10-31 Palmer Dabbelt * doc/invoke.texi (RISC-V Options): Explicitly name the medlow and medany code models, and

Re: [09/nn] Add a fixed_size_mode_pod class

On Tue, Oct 31, 2017 at 11:38:48AM -0600, Jeff Law wrote: > On 10/31/2017 11:22 AM, Eric Botcazou wrote: > >> I don't see a reason not to other than a pretty small amount of work > >> each time we make a release. > > > > I'm not sure it would be so small an amount of work, especially on > >

[PATCH] RISC-V: Document the medlow and medany code models

This documentation is patterned off the aarch64 -mcmodel documentation. gcc/ChangeLog: 2017-10-31 Palmer Dabbelt * doc/invoke.texi (RISC-V Options): Explicitly name the medlow and medany code models, and describe what they do. --- gcc/doc/invoke.texi | 17

Re: [committed] diagnostics: get rid of *_at_rich_loc in favor of overloading

On Tue, 2017-10-31 at 23:20 +, Joseph Myers wrote: > To confirm: can you make sure that exgettext (via "make gcc.pot") > still > works to extract messages from these overloaded functions for > translation? > It *should* work, because the msgid argument is at the same position > for > all

Re: [PATCH, AArch64] Disable reg offset in quad-word store for Falkor.

Hi Jim, On 1 November 2017 at 03:12, Jim Wilson wrote: > On Tue, 2017-10-31 at 14:35 +1100, Kugan Vivekanandarajah wrote: >> Ping ? >> >> I see that Jim has clarified the comments from Andrew. > > Andrew also suggested that we add a testcase to the testsuite. I > didn't do

Re: [committed] diagnostics: get rid of *_at_rich_loc in favor of overloading

To confirm: can you make sure that exgettext (via "make gcc.pot") still works to extract messages from these overloaded functions for translation? It *should* work, because the msgid argument is at the same position for all overloads (what definitely doesn't work is overloads of diagnostic

Re: [PATCH][compare-elim] Fix PR rtl-optimization/82597

On Tue, Oct 31, 2017 at 12:02:26PM +0100, Jakub Jelinek wrote: > 2017-10-31 Jakub Jelinek > > PR rtl-optimization/82778 > PR rtl-optimization/82597 > * compare-elim.c (struct comparison): Add in_a_setter field. >

[PR 81702] Remove devirtualization assert

Hi, in PR 81702, both me and Honza came to the conclusion that the assert that is being hit can be removed if it is indeed OK that a particular variable is constructed without a DECL_INITIAL. Yesterday Nathan confirmed that in this case it is fine. So the patch below removes the assert.

Re: [PATCH] RFC: Preserving locations for variable-uses and constants (PR 43486)

On Tue, 2017-10-24 at 09:53 -0400, Jason Merrill wrote: > On Fri, Oct 20, 2017 at 5:53 PM, David Malcolm > wrote: > > Design questions: > > > > * The patch introduces a new kind of tree node, currently called > > DECL_WRAPPER_EXPR (although it's used for wrapping constants

Re: [patch, fortran] Index interchange for FORALL and DO CONCURRENT

On Tue, Oct 31, 2017 at 09:50:37PM +0100, Bernhard Reutner-Fischer wrote: > On Tue, Oct 31, 2017 at 09:30:27PM +0100, Thomas Koenig wrote: > > > > Or maybe emit diagnostics into the frontend optimize dump file and scan > > > that? > > > > If we could check the Fortran tree dumps with dejagnu,

Re: [patch, fortran] Index interchange for FORALL and DO CONCURRENT

On Tue, Oct 31, 2017 at 09:30:27PM +0100, Thomas Koenig wrote: > > Or maybe emit diagnostics into the frontend optimize dump file and scan > > that? > > If we could check the Fortran tree dumps with dejagnu, that would be > doable. Unfortunately, we don't have that in place. Well that should be

[committed] jit: add a way to preserve testsuite executables

The jit documentation has instructions on running testsuite executables under the debugger, but I realize now that the executables were always being deleted after being run, and I've always been hacking up my jit.exp to prevent this, to allow for debugging them. This patch adds a

[committed] pt.c: add missing %< and %>

This patch fixes some missing quoting of a source code element within a diagnostic: a reference to "#include ". Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu; Commited to trunk as r254281. gcc/cp/ChangeLog: * pt.c (listify): Use %< and %> for description of #include.

Re: [patch, fortran] Index interchange for FORALL and DO CONCURRENT

Hi Bernhard, Regression-tested. OK for trunk? s/shoud/should/; s/acessed/accessed/; s/indces/indices/; Fixed. why are struct ind_type "n" and "num" int and not unsigned int? I tend not to use signed variables unless the special overflow semantics are required. I like Fortran, which

[committed] diagnostics: get rid of *_at_rich_loc in favor of overloading

Adding a fix-it hint currently involves changing e.g.: error_at (token->location, "unknown type name %qE; did you mean %qs?", token->value, hint); to: gcc_rich_location richloc (token->location); richloc.add_fixit_replace (hint); error_at_rich_loc (,

Re: [006/nnn] poly_int: tree constants

On 10/29/2017 09:14 PM, Trevor Saunders wrote: On Sun, Oct 29, 2017 at 10:25:38AM -0600, Martin Sebor wrote: On 10/27/2017 02:08 AM, Richard Sandiford wrote: Martin Sebor writes: On 10/26/2017 11:52 AM, Richard Sandiford wrote: Martin Sebor writes: For

[C++ PATCH] overloaded operator fns [5/N]

This patch replaces the separate operator_name_info & assignment_operator_name_info arrays with a single 2D ovl_op_info array. I also add a tree_code field to the renamed ovl_op_info_t, which although in this instance is simply a 1:1 mapping to the array index, will morph soon as the indices

Re: [patch][x86] GFNI enabling [2/4]

On Mon, Oct 30, 2017 at 07:02:23PM +, Koval, Julia wrote: > gcc/testsuite/ > * gcc.target/i386/avx-1.c: Handle new intrinsics. > * gcc.target/i386/avx512-check.h: Check GFNI bit. > * gcc.target/i386/avx512f-gf2p8affineinvqb-2.c: Runtime test. > *

Re: [PATCH,RFC] collect2 LTO for AIX

On Mon, Oct 30, 2017 at 3:13 PM, Jeff Law wrote: > On 10/13/2017 12:04 PM, David Edelsohn wrote: >> The attached patch is an incremental step toward GCC LTO on AIX. The >> recent Libiberty Simple Object improvements for XCOFF provide more >> capabilities for operations on XCOFF

Re: [PATCH v3] Add asan and ubsan support on NetBSD/amd64

On 31.10.2017 19:45, Jakub Jelinek wrote: > On Tue, Oct 31, 2017 at 07:28:23PM +0100, Kamil Rytarowski wrote: >> I'm giving it a try. I took the asan part and skipped >> "%{!shared:libasan_preinit%O%s} ". If I understand this correctly, it >> attempts to use the ELF section with preinit property

Re: [PATCH][AArch64] Improve aarch64_legitimate_constant_p

James Greenhalgh wrote: > This is mostly OK, but I think you lose one case we previosuly permitted, > buried in aarch64_classify_address (the CONST case). > > OK with that case handled too (assuming that passes a bootstrap and test). That case is already handled. The CONST case handles the

Re: [PATCH v3] Add asan and ubsan support on NetBSD/amd64

On Tue, Oct 31, 2017 at 07:28:23PM +0100, Kamil Rytarowski wrote: > I'm giving it a try. I took the asan part and skipped > "%{!shared:libasan_preinit%O%s} ". If I understand this correctly, it > attempts to use the ELF section with preinit property in order to > bootstrap asan quickly. The

[C++ PATCH] overloaded operator fns [4/N]

The overloaded operator table conflates a couple of things -- both mangling and special names. Entries just for mangling do not need a special name. This sets them to NULL and no associated identifier is created. init_operators created a bunch of pseudo entries, ostensibly 'because errors',

Fix PR rtl-optimization/81803

This is a regression present on the mainline and 7 branch for little-endian 64-bit MIPS platforms under the form of incorrect spill/reload pairs generated by the LRA pass, i.e. for which the spill instruction is a narrower access than the reload instruction. That's incorrect for accesses no

Re: [PATCH v3] Add asan and ubsan support on NetBSD/amd64

On 31.10.2017 15:04, Jakub Jelinek wrote: > On Tue, Oct 31, 2017 at 02:53:26PM +0100, Kamil Rytarowski wrote: http://netbsd.org/~kamil/gcc/test_summary.log.8-20171022.txt >>> >>> That seems that asan pretty much doesn't work at all in GCC for netbsd. >>> A few FAILs might be acceptable, but

Re: [PATCH, version 5a], Add support for _Float and _FloatX sqrt, fma, fmin, fmax built-in functions

On Tue, 31 Oct 2017, Michael Meissner wrote: > On Mon, Oct 30, 2017 at 11:30:12PM +, Joseph Myers wrote: > > On Mon, 30 Oct 2017, Michael Meissner wrote: > > > > > This patch fixes exporting the non __builtin_ names to be done by default > > > only > > > for the C language. I added a

Re: [10/nn] [AArch64] Minor rtx costs tweak

On Fri, Oct 27, 2017 at 02:30:18PM +0100, Richard Sandiford wrote: > aarch64_rtx_costs uses the number of registers in a mode as the basis > of SET costs. This patch makes it get the number of registers from > aarch64_hard_regno_nregs rather than repeating the calcalation inline. > Handling SVE

Re: [PATCH, version 5a], Add support for _Float and _FloatX sqrt, fma, fmin, fmax built-in functions

On Mon, Oct 30, 2017 at 11:30:12PM +, Joseph Myers wrote: > On Mon, 30 Oct 2017, Michael Meissner wrote: > > > This patch fixes exporting the non __builtin_ names to be done by default > > only > > for the C language. I added a target hook in case a port needs to enable > > built-ins for

Re: [04/nn] [AArch64] Rename the internal "Upl" constraint

On Fri, Oct 27, 2017 at 02:25:56PM +0100, Richard Sandiford wrote: > The SVE port uses the public constraints "Upl" and "Upa" to mean > "low predicate register" and "any predicate register" respectively. > "Upl" was already used as an internal-only constraint by the > addition patterns, so this

Re: [02/nn] [AArch64] Move code around

On Fri, Oct 27, 2017 at 02:23:30PM +0100, Richard Sandiford wrote: > This patch simply moves code around, in order to make the later > patches easier to read, and to avoid forward declarations. > It doesn't add the missing function comments because the interfaces > will change in a later patch.

Re: [01/nn] [AArch64] Generate permute patterns using rtx builders

On Fri, Oct 27, 2017 at 02:22:39PM +0100, Richard Sandiford wrote: > This patch replaces switch statements that call specific generator > functions with code that constructs the rtl pattern directly. > This seemed to scale better to SVE and also seems less error-prone. > > As a side-effect, the

Re: [PATCH] PR debug/81570: dwarf2cfi.c: Update cfa.offset in create_pseudo_cfg

On Tue, Oct 24, 2017 at 8:26 PM, Jason Merrill wrote: > On Thu, Jul 27, 2017 at 3:50 PM, H.J. Lu wrote: >> execute_dwarf2_frame is called for each funtion. But create_cie_data >> is called only once to initialize cie_cfi_row for all functions. Since >>

Re: [09/nn] Add a fixed_size_mode_pod class

On 10/31/2017 11:22 AM, Eric Botcazou wrote: >> I don't see a reason not to other than a pretty small amount of work >> each time we make a release. > > I'm not sure it would be so small an amount of work, especially on non-Linux > platforms, so this would IMO divert our resources for little

Re: [PATCH][GCC][testsuite][mid-end][ARM][AARCH64] Fix failing vec align tests.

On Mon, Oct 23, 2017 at 10:37:39AM +0100, Tamar Christina wrote: > Ping OK for backport, but I'm not sure why you want to backport a patch which you know is going to break something. When you commit, just roll everything up in to one patch, rather than three patches, two of which cause breaks.

[Ada] Fix PR ada/82785

Small typo libgnarl->libgnat. Applied on the mainline. 2017-10-31 Eric Botcazou PR ada/82785 * gcc-interface/Makefile.in (m68k/Linux): Fix typo. -- Eric BotcazouIndex: gcc-interface/Makefile.in

Re: [09/nn] Add a fixed_size_mode_pod class

> I don't see a reason not to other than a pretty small amount of work > each time we make a release. I'm not sure it would be so small an amount of work, especially on non-Linux platforms, so this would IMO divert our resources for little benefit. > Well first this would only matter to the

Re: RFA: PATCH to tell gdb to skip over is-a.h inlines

On Thu, Apr 28, 2016 at 3:04 PM, Jason Merrill wrote: > On 04/25/2016 01:28 PM, Jason Merrill wrote: >> >> There doesn't seem to be any need to step through the is-a inline >> functions. OK for trunk? > > Likewise line-map.h. And timevar.h. Jason commit

[PATCH][AArch64] Define MALLOC_ABI_ALIGNMENT

The AArch64 backend currently doesn't set MALLOC_ABI_ALIGNMENT, so add this to enable alignment optimizations on malloc pointers. OK for commit? 2017-10-31 Wilco Dijkstra * config/aarch64/aarch64.h (MALLOC_ABI_ALIGNMENT): New define. -- diff --git

Re: [PATCH PR79868 ][aarch64] Fix error calls in aarch64 code so they can be translated (version 2)

On Tue, 2017-10-31 at 09:57 +, Richard Earnshaw (lists) wrote: >  > This is looking better... > > I may have missed some discussion on this topic, but what's the > reasoning behind changing the quoting around the 'str' parameter > value in > > - error ("unknown value %qs for 'cpu' target

Re: [patch, fortran] Index interchange for FORALL and DO CONCURRENT

On Tue, Oct 31, 2017 at 02:24:39PM +0100, Thomas Koenig wrote: > Hello world, > > here is a version of the patch for index interchange for FORALL > and DO CONCURRENT that I would like to commit. > > It introduces a new option for selecting (or deselecting) > the option,

RE: [PATCH 21/22] Enable building libitm with Intel CET

Actually I did changes to add the new field for linux under ifdef __linux__. > -Original Message- > From: Jeff Law [mailto:l...@redhat.com] > Sent: Tuesday, October 31, 2017 12:21 AM > To: Tsimbalist, Igor V ; gcc- > patc...@gcc.gnu.org > Cc:

[C++ PATCH] overloaded operator fns [3/N]

This patch replaces the operator info 'arity' field with a 'flags' field that encodes more information. Adjusted the few places that look at this. More use will be made in future patches. nathan -- Nathan Sidwell 2017-10-31 Nathan Sidwell * cp-tree.h (enum

Re: [C++ Patch] PR 80955 (Macros expanded in definition of user-defined literals)

On 10/25/2017 6:44 PM, Mukesh Kapoor wrote: On 10/25/2017 4:20 AM, Nathan Sidwell wrote: On 10/25/2017 12:03 AM, Mukesh Kapoor wrote: Thanks for pointing this out. Checking in the front end will be difficult because the front end gets tokens after macro expansion. I think the difficulty of

Re: [PATCH, AArch64] Disable reg offset in quad-word store for Falkor.

On Tue, 2017-10-31 at 14:35 +1100, Kugan Vivekanandarajah wrote: > Ping ? > > I see that Jim has clarified the comments from Andrew. Andrew also suggested that we add a testcase to the testsuite.  I didn't do that.  I did put a testcase to reproduce in the bug report.  See     

Re: [006/nnn] poly_int: tree constants

On 10/30/2017 04:19 AM, Pedro Alves wrote: On 10/27/2017 12:29 AM, Martin Sebor wrote: IMO, a good rule of thumb to follow in class design is to have every class with any user-defined ctor either define a default ctor that puts the object into a determinate state, or make the default ctor

Re: [PATCH, rs6000] Add Power 9 support for vec_first builtins

On Tue, Oct 31, 2017 at 08:46:09AM -0700, Carl Love wrote: > 2017-10-31 Carl Love > > * config/rs6000/rs6000-c.c: Add support for builtins: > unsigned int vec_first_match_index (vector signed char, > vector signed char);

Re: [PATCH] rs6000: Fix crash with big stack clash interval (PR82674)

On 10/31/2017 09:32 AM, Segher Boessenkool wrote: > On Tue, Oct 31, 2017 at 09:12:25AM -0600, Jeff Law wrote: >> On 10/31/2017 03:41 AM, Segher Boessenkool wrote: >>> If the user asks for a stack clash probe interval of 64kB, we currently >>> generate a "stdu rX,-65536(r1)" instruction. That

[PATCH] GCOV: create one intermediate file per a gcno file (PR gcov-profile/82702).

Hi. This is partial revert of r246804 where I accidentally changed behavior so that each intermediate file is written to a source file. That's not intended for example for header files. As mentioned in documentation: "The output is a single ‘.gcov’ file per ‘.gcda’ file". Outer loop in main

Re: [PATCH, rs6000] Add Power 9 support for vec_first builtins

GCC maintainers: The patch has been updated to fix the typo and retested. Unfortunately the names of the builtins are rather long and unwieldy to begin with. Please let me know if the following patch is acceptable. Thanks. Carl Love

Re: [PATCH] rs6000: Fix crash with big stack clash interval (PR82674)

On Tue, Oct 31, 2017 at 09:12:25AM -0600, Jeff Law wrote: > On 10/31/2017 03:41 AM, Segher Boessenkool wrote: > > If the user asks for a stack clash probe interval of 64kB, we currently > > generate a "stdu rX,-65536(r1)" instruction. That instruction does not > > exist (the offset is a 16-bit

Re: [PATCH 4/7] GCOV: add -j argument (human readable format).

On 10/31/2017 03:35 PM, Nathan Sidwell wrote: On 10/31/2017 10:04 AM, Martin Liška wrote: Do you mean numbers a bit smaller than 1000 or bit bigger? Do you have an example that will be handled in a different way? A count like 999500 would have been scaled to 999.5 and then rounded to 1000. 

RE: [PATCH 07/22] Enable building libgcc with CET options.

Ok, just did it :) Igor > -Original Message- > From: Andreas Schwab [mailto:sch...@linux-m68k.org] > Sent: Tuesday, October 31, 2017 4:00 PM > To: Tsimbalist, Igor V > Cc: Joseph Myers ; gcc-patches@gcc.gnu.org; > Jeff Law

Re: [PATCH] rs6000: Fix crash with big stack clash interval (PR82674)

On 10/31/2017 03:41 AM, Segher Boessenkool wrote: > If the user asks for a stack clash probe interval of 64kB, we currently > generate a "stdu rX,-65536(r1)" instruction. That instruction does not > exist (the offset is a 16-bit signed number). If the offset is too big > we should force it into

Re: [PATCH 07/22] Enable building libgcc with CET options.

On Okt 31 2017, "Tsimbalist, Igor V" wrote: > Fixed. > > - i[34567]86-*-linux* | x86_64-*-linux*) > + i[[34567]]86-*-linux* | x86_64-*-linux*) Don't forget to regenerate all configure scripts. Andreas. -- Andreas Schwab, sch...@linux-m68k.org GPG Key

Re: [PATCH][AArch64] Restrict POST_INC operand in aarch64_simd_mem_operand_p to register

> On 31 Oct 2017, at 15:47, Kyrill Tkachov wrote: > > > On 31/10/17 14:44, Dominik Inführ wrote: >>> On 31 Oct 2017, at 15:10, Kyrill Tkachov >>> wrote: >>> >>> [cc'ing aarch64 maintainers] >>> >>> Hi Dominik, >>> >>> On 31/10/17

RE: [PATCH 07/22] Enable building libgcc with CET options.

Fixed. - i[34567]86-*-linux* | x86_64-*-linux*) + i[[34567]]86-*-linux* | x86_64-*-linux*) Igor > -Original Message- > From: Andreas Schwab [mailto:sch...@linux-m68k.org] > Sent: Tuesday, October 31, 2017 2:30 PM > To: Tsimbalist, Igor V > Cc: Joseph

Re: [PATCH][AArch64] Restrict POST_INC operand in aarch64_simd_mem_operand_p to register

On 31/10/17 14:44, Dominik Inführ wrote: On 31 Oct 2017, at 15:10, Kyrill Tkachov wrote: [cc'ing aarch64 maintainers] Hi Dominik, On 31/10/17 13:47, Dominik Inführ wrote: Hi, I have a custom optimization pass, that moves an expression into an

Re: [PATCH][AArch64] Restrict POST_INC operand in aarch64_simd_mem_operand_p to register

> On 31 Oct 2017, at 15:10, Kyrill Tkachov wrote: > > [cc'ing aarch64 maintainers] > > Hi Dominik, > > On 31/10/17 13:47, Dominik Inführ wrote: >> Hi, >> >> I have a custom optimization pass, that moves an expression into an >> POST_INC-expression. GCC then

[C++ PATCH] overloaded operator fns [2/N]

This patch removes cp_operator_id(C) and cp_assignment_operator_id(C), replacing them with a singlle ovl_op_identifier(A,C) macro. There's also OVL_OP_INFO(A,C) to get at the other information. The implementation of that macro will change later in this patch series, so don't freak on the (A

Re: [PATCH 4/7] GCOV: add -j argument (human readable format).

On 10/31/2017 10:04 AM, Martin Liška wrote: Do you mean numbers a bit smaller than 1000 or bit bigger? Do you have an example that will be handled in a different way? A count like 999500 would have been scaled to 999.5 and then rounded to 1000. We'd print 1000k rather than 1M. I've

Re: [PATCH][AArch64] Restrict POST_INC operand in aarch64_simd_mem_operand_p to register

[cc'ing aarch64 maintainers] Hi Dominik, On 31/10/17 13:47, Dominik Inführ wrote: Hi, I have a custom optimization pass, that moves an expression into an POST_INC-expression. GCC then ICE’s in df-scan.c since it expects REG_P to be true for POST_INC’s operand. aarch64_simd_mem_operand_p

Re: [PATCH v3] Add asan and ubsan support on NetBSD/amd64

On Tue, Oct 31, 2017 at 02:53:26PM +0100, Kamil Rytarowski wrote: > >> http://netbsd.org/~kamil/gcc/test_summary.log.8-20171022.txt > > > > That seems that asan pretty much doesn't work at all in GCC for netbsd. > > A few FAILs might be acceptable, but so many FAILs certainly aren't. > > The

Re: [PATCH 4/7] GCOV: add -j argument (human readable format).

On 10/31/2017 01:05 PM, Nathan Sidwell wrote: On 10/31/2017 07:49 AM, Martin Liška wrote: On 10/30/2017 01:35 PM, Nathan Sidwell wrote: Is the patch fine to be installed? not quite ... +  gcov_type divisor = 1; +  for (unsigned i = 0; i < strlen (units); i++) +    { +  if (v < (1000 *

Re: [PATCH v3] Add asan and ubsan support on NetBSD/amd64

On 31.10.2017 14:22, Jakub Jelinek wrote: > On Mon, Oct 30, 2017 at 09:01:25PM +0100, Kamil Rytarowski wrote: >> On 30.10.2017 08:24, Jakub Jelinek wrote: >>> On Thu, Oct 26, 2017 at 09:50:43PM +0200, Kamil Rytarowski wrote: $ make check-asan $ make check-asan-dynamic $ make

[PATCH][AArch64] Restrict POST_INC operand in aarch64_simd_mem_operand_p to register

Hi, I have a custom optimization pass, that moves an expression into an POST_INC-expression. GCC then ICE’s in df-scan.c since it expects REG_P to be true for POST_INC’s operand. aarch64_simd_mem_operand_p doesn’t seem to check POST_INC’s operand. Here is a patch that fixes this for me,

Re: [PATCH 07/22] Enable building libgcc with CET options.

On Okt 31 2017, "Tsimbalist, Igor V" wrote: > diff --git a/config/cet.m4 b/config/cet.m4 > new file mode 100644 > index 000..c903791 > --- /dev/null > +++ b/config/cet.m4 > @@ -0,0 +1,40 @@ > +dnl > +dnl GCC_CET_FLAGS > +dnl(SHELL-CODE_HANDLER) > +dnl >

[patch, fortran] Index interchange for FORALL and DO CONCURRENT

Hello world, here is a version of the patch for index interchange for FORALL and DO CONCURRENT that I would like to commit. It introduces a new option for selecting (or deselecting) the option, -ffrontend-loop-interchange. The reason for this is simple: It is always possible that the heurisics

Re: [PATCH v3] Add asan and ubsan support on NetBSD/amd64

On Mon, Oct 30, 2017 at 09:01:25PM +0100, Kamil Rytarowski wrote: > On 30.10.2017 08:24, Jakub Jelinek wrote: > > On Thu, Oct 26, 2017 at 09:50:43PM +0200, Kamil Rytarowski wrote: > >> $ make check-asan > >> $ make check-asan-dynamic > >> $ make check-ubsan > > > > That is testing of the upstream

[libgomp, hsa,committed] Remove semicolon after do {} while (false) in HSA_LOG

Hi, this patch removes a semicolon after "do {} while (false)" in HSA_LOG, making sure we can use it in if-then-elses without curly braces. Build hsa plugin. Committed as trivial. Thanks, - Tom Remove semicolon after do {} while (false) in HSA_LOG 2017-10-31 Tom de Vries

[C++ PATCH] overloaded operator fns [1/N]

This patch breaks DECL_OVERLOADED_OPERATOR_P apart into a predicate (as its name suggests) and DECL_OVERLOADED_OPERATOR_CODE, an accessor. I also add DECL_OVERLOADED_OPERATOR_IS, whose current implementation is a stepping stone to more a compressed operator enumeration. Also add

RE: [PATCH 20/22] Enable building libobjc with Intel CET

The revised patch is attached. The differences are in what options are defined and propagated to Makefile for CET enabling.   Ok for trunk? Igor > -Original Message- > From: Jeff Law [mailto:l...@redhat.com] > Sent: Wednesday, October 18, 2017 1:43 AM > To: Tsimbalist, Igor V

RE: [PATCH 19/22] Enable building libgfortran with Intel CET

The revised patch is attached. The differences are in what options are defined and propagated to Makefile for CET enabling.   Ok for trunk? Igor > -Original Message- > From: Jeff Law [mailto:l...@redhat.com] > Sent: Wednesday, October 18, 2017 1:43 AM > To: Tsimbalist, Igor V

RE: [PATCH 18/22] Enable building libmpx with Intel CET

The revised patch is attached. The differences are in what options are defined and propagated to Makefile for CET enabling.   Ok for trunk? Igor > -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches- > ow...@gcc.gnu.org] On Behalf Of Jeff Law > Sent: Wednesday,

RE: [PATCH 17/22] Enable building libquadmath with Intel CET

The revised patch is attached. The differences are in what options are defined and propagated to Makefile for CET enabling.   Ok for trunk? Igor > -Original Message- > From: Jeff Law [mailto:l...@redhat.com] > Sent: Wednesday, October 18, 2017 1:41 AM > To: Tsimbalist, Igor V

RE: [PATCH 16/22] Enable building libssp with Intel CET

The revised patch is attached. The differences are in what options are defined and propagated to Makefile for CET enabling.   Ok for trunk? Igor > -Original Message- > From: Jeff Law [mailto:l...@redhat.com] > Sent: Wednesday, October 18, 2017 1:38 AM > To: Tsimbalist, Igor V

RE: [PATCH 15/22] Enable building libvtv with Intel CET

The revised patch is attached. The differences are in what options are defined and propagated to Makefile for CET enabling.   Ok for trunk? Igor > -Original Message- > From: Jeff Law [mailto:l...@redhat.com] > Sent: Wednesday, October 18, 2017 1:38 AM > To: Tsimbalist, Igor V

Re: [PATCH 4/7] GCOV: add -j argument (human readable format).

On 10/31/2017 07:49 AM, Martin Liška wrote: On 10/30/2017 01:35 PM, Nathan Sidwell wrote: Is the patch fine to be installed? not quite ... + gcov_type divisor = 1; + for (unsigned i = 0; i < strlen (units); i++) +{ + if (v < (1000 * divisor)) + { + gcov_type r =

RE: [PATCH 13/22] Enable building libstdc++-v3 with Intel CET

The revised patch is attached. The differences are in what options are defined and propagated to Makefile for CET enabling.   Ok for trunk? Igor > -Original Message- > From: Tsimbalist, Igor V > Sent: Friday, October 13, 2017 2:09 PM > To: gcc-patches@gcc.gnu.org; libstd...@gcc.gnu.org

RE: [PATCH 12/22] Enable building libgomp with Intel CET

The revised patch is attached. The differences are in what options are defined and propagated to Makefile for CET enabling.   Ok for trunk? Igor > -Original Message- > From: Jeff Law [mailto:l...@redhat.com] > Sent: Wednesday, October 18, 2017 1:36 AM > To: Tsimbalist, Igor V

RE: [PATCH 11/22] Enable building libatomic with Intel CET

The revised patch is attached. The differences are in what options are defined and propagated to Makefile for CET enabling.   Ok for trunk? Igor > -Original Message- > From: Jeff Law [mailto:l...@redhat.com] > Sent: Wednesday, October 18, 2017 1:35 AM > To: Tsimbalist, Igor V

RE: [PATCH 10/22] Enable building libcilkrts with Intel CET

The revised patch is attached. The differences are in what options are defined and propagated to Makefile for CET enabling. Ok for trunk? Igor > -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches- > ow...@gcc.gnu.org] On Behalf Of Jeff Law > Sent: Wednesday,

Re: [PATCH 4/7] GCOV: add -j argument (human readable format).

On 10/30/2017 01:35 PM, Nathan Sidwell wrote: On 10/26/2017 04:11 AM, marxin wrote: Human readable format is quite useful in my opinion. There's example: -:    1:unsigned     14.00K:    2:loop (unsigned n, int value) My first thought is 'why 2 decimal places'?  That seems excessive. 

RE: [PATCH 09/22] Enable building libbacktrace with Intel CET

The revised patch is attached. The differences are in what options are defined and propagated to Makefile for CET enabling. -iclude option is dropped, each needed asm file is processed separately. Igor > -Original Message- > From: Ian Lance Taylor [mailto:i...@airs.com] > Sent:

RE: [PATCH 07/22] Enable building libgcc with CET options.

The revised patch is attached. The differences are in what options are defined and propagated to Makefile for CET enabling, also needed asm files are updated. Igor > -Original Message- > From: Tsimbalist, Igor V > Sent: Friday, October 13, 2017 1:02 AM > To: Joseph Myers

Re: [PATCH 3/7] GCOV: add support for lines with an unexecuted lines.

On 10/30/2017 01:21 PM, Nathan Sidwell wrote: Looks good otherwise, WDYT? Hi. Works for me, it's more precise! Thanks, Martin nathan

Re: [PATCH 2/7] GCOV: introduce usage of terminal colors.

On 10/30/2017 03:49 PM, David Malcolm wrote: On Mon, 2017-10-30 at 08:17 -0400, Nathan Sidwell wrote: On 10/26/2017 04:11 AM, marxin wrote: I consider using colors in context of gcov as very useful. There's example for tramp3d: https://pste.eu/p/Tl2D.html nice! gcc/ChangeLog: 2017-10-23

Re: [PATCH 1/7] GCOV: document behavior of -fkeep-{static,inline}-functions (PR gcov-profile/82633).

On 10/30/2017 01:15 PM, Nathan Sidwell wrote: On 10/26/2017 04:11 AM, marxin wrote: gcc/ChangeLog: +++ b/gcc/doc/gcov.texi @@ -327,6 +327,11 @@ non-exceptional paths or only exceptional paths such as C++ exception   handlers, respectively. Given @samp{-a} option, unexecuted blocks are  

Re: [PATCH][compare-elim] Fix PR rtl-optimization/82597

On Tue, Oct 31, 2017 at 10:35:59AM +0100, Jakub Jelinek wrote: > > 2017-10-18 Michael Collison > > > > PR rtl-optimization/82597 > > * compare-elim.c: (try_validate_parallel): Constrain operands > > of recognized insn. > > That just duplicates more of

[PATCH, alpha]: Fix PR 82772, could not split atomic_andsi insn

The constraint for atomic_andsi didn't fit predicate. 2017-10-31 Uros Bizjak PR target/82772 * config/alpha/sync.md (fetchop_constr) : Change to "rINM". Bootstrapped on alphaev68-linux-gnu, committed to mainline SVN and release branches under obvious rule. Uros.

Re: [09/nn] Add a fixed_size_mode_pod class

On Mon, Oct 30, 2017 at 11:11:12AM +0100, Eric Botcazou wrote: > > It sounds like people are mostly concerned about sun studio and xlc? It > > doesn't seem that hard to provide precompiled binaries for those two > > platforms, and maybe 4.8 binaries for people who want to compile theire > > own

Re: [PATCH PR79868 ][aarch64] Fix error calls in aarch64 code so they can be translated (version 2)

On 30/10/17 20:50, Steve Ellcey wrote: > On Thu, 2017-10-26 at 13:56 +0100, Richard Earnshaw (lists) wrote: >>   >> I can't help feeling that all this logic is somewhat excessive and >> changing the wording of each message to include "pragma or attribute" >> would solve it equally well.  With the

[C++ Patch] PR 81957 ("ICE decltype")

Hi, this ICE on valid seems rather easy to fix, one of those bugs where we aren't propagating the tsubst_flags_t argument. In this case, we aren't propagating from tsubst_pack_expansion to make_pack_expansion. Doing it, fixes the ICE and we actually accept the code as we should. In general,

[PATCH] rs6000: Fix crash with big stack clash interval (PR82674)

If the user asks for a stack clash probe interval of 64kB, we currently generate a "stdu rX,-65536(r1)" instruction. That instruction does not exist (the offset is a 16-bit signed number). If the offset is too big we should force it into a register and generate a "stdux rX,rY,r1" instruction,

Re: [PATCH 2/2] [i386] PR82002 Part 2: Correct non-immediate offset/invalid INSN

On Tue, Oct 31, 2017 at 3:09 AM, Daniel Santos wrote: > When we are realigning the stack pointer, making an ms_abi to sysv_abi > call and alllocating 2GiB or more on the stack we end up with an invalid > INSN due to a non-immediate offset. This occurs both with and

Re: [PATCH][compare-elim] Fix PR rtl-optimization/82597

On Fri, Oct 20, 2017 at 04:10:15AM +, Michael Collison wrote: > This patch fixes an ICE on x86 because we were not constraining the operands > of a recognized insn. Bootstrapped and tested on aarch64-none-linux-gnu and > x86_64. > > Also successfully compiled the failing test cases in 82597

Re: [PATCH, Makefile] improve libsubdir variable transmission to sub-makes on Windows

> On Oct 31, 2017, at 00:07 , Jeff Law wrote: >> * Makefile.in (FLAGS_TO_PASS): Add libsubdir. > OK. :-) Thanks Jeff!

[PATCH v2] Fix Incorrect ASan global variables alignment on arm (PR sanitizer/81697)

Hi, this is the second attempt to fix PR sanitizer/81697. For architectures that use section anchors there is a problem with asan_protect_global because it's involved in a circular dependency: 1) categorize_decl_for_section calls asan_protect_global that returns false because DECL_RTL is not

Re: [PATCH 2/2] [i386] PR82002 Part 2: Correct non-immediate offset/invalid INSN

On Tue, Oct 31, 2017 at 4:23 AM, Daniel Santos wrote: > On 10/30/2017 09:09 PM, Daniel Santos wrote: >> 3. Modify choose_baseaddr to take an optional scratch_regno argument >>and never return rtx that cannot be used as an immediate. > > I should amend this, it

Re: [PATCH 1/2] [i386] PR82002 Part 1: Correct ICE caused by wrong calculation.

On Tue, Oct 31, 2017 at 3:09 AM, Daniel Santos wrote: > This is a residual problem caused by the off-by-one error in sp_valid_at > and fp_valid_at originally corrected in r252099. However, adding tests > that include an ms_abi to sysv_abi call reveals an additional, more

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