[PATCH v3] Introduce -finline-stringops

On Sep 21, 2023, Alexandre Oliva wrote: > On Sep 15, 2023, Alexandre Oliva wrote: >> On Jun 22, 2023, Alexandre Oliva wrote: >>> On Jun 2, 2023, Alexandre Oliva wrote: Introduce -finline-stringops >>> Ping? https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620472.html >> Ping? >

Re: [PATCH] RISC-V/testsuite: Fix ILP32 RVV failures from missing

On 9/22/23 17:18, Maciej W. Rozycki wrote: In non-multilib installations system headers may not be available for compilation options using a non-default model, causing build errors such as: In file included from .../include/features.h:527, from .../include/assert.h:35,

Re: Re: [Committed] RISC-V: Support VLS INT <-> FP conversions

Confirm it is a latent bug already existed long time ago but we were lucky that we didn't trigger this issue before. This patch didn't involve a new bug. Li pan from intel will send a patch fix it soon. Thanks for report. juzhe.zh...@rivai.ai From: Edwin Lu Date: 2023-09-23 06:38 To:

[Committed] RISC-V: Add VLS unary combine patterns

gcc/ChangeLog: * config/riscv/autovec-opt.md: Add VLS modes for conditional ABS/SQRT. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/cond_abs-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_sqrt-1.c: New test. --- gcc/config/riscv/autovec-opt.md

Re: [PATCH v3] RISC-V: Suport FP floor auto-vectorization

LGTM. juzhe.zh...@rivai.ai From: pan2.li Date: 2023-09-23 09:19 To: gcc-patches CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v3] RISC-V: Suport FP floor auto-vectorization From: Pan Li This patch would like to support auto-vectorization for the floor API in math.h.

[PATCH v3] RISC-V: Suport FP floor auto-vectorization

From: Pan Li This patch would like to support auto-vectorization for the floor API in math.h. It depends on the -ffast-math option. When we would like to call floor/floorf like v2 = floor (v1), we will convert it into below insns (reference the implementation of llvm). * vfcvt.x.f v3, v1, RDN

RE: [PATCH v1] RISC-V: Remove FP run test for ceil.

Committed, thanks Juzhe. Pan From: 钟居哲 Sent: Saturday, September 23, 2023 9:07 AM To: Li, Pan2 ; gcc-patches Cc: Li, Pan2 ; Wang, Yanzhang ; kito.cheng Subject: Re: [PATCH v1] RISC-V: Remove FP run test for ceil. Ok

Re: [PATCH v1] RISC-V: Remove FP run test for ceil.

Ok juzhe.zh...@rivai.ai From: pan2.li Date: 2023-09-23 09:06 To: gcc-patches CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] RISC-V: Remove FP run test for ceil. From: Pan Li FP16 is not well reconciled when linking. gcc/testsuite/ChangeLog: *

[PATCH v1] RISC-V: Remove FP run test for ceil.

From: Pan Li FP16 is not well reconciled when linking. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/unop/math-ceil-run-0.c: Remove. Signed-off-by: Pan Li --- .../riscv/rvv/autovec/unop/math-ceil-run-0.c | 39 --- 1 file changed, 39 deletions(-) delete

[PATCH] PHIOPT: Fix minmax_replacement for three way

So when diamond bb support was added to minmax_replacement in r13-1950-g9bb19e143cfe, the code was not expecting the alt_middle_bb not to exist if it was empty (for threeway_p). So when factor_out_conditional_conversion was used to factor out conversions, it turns out the assumption for

Re: [PATCH v2] RISC-V: Suport FP floor auto-vectorization

LGTM. But I think you should remove FP16 run tests. So plz send a patch first remove FP16 run test of CEIL first. juzhe.zh...@rivai.ai From: pan2.li Date: 2023-09-23 08:40 To: gcc-patches CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v2] RISC-V: Suport FP floor

[PATCH v2] RISC-V: Suport FP floor auto-vectorization

From: Pan Li This patch would like to support auto-vectorization for the floor API in math.h. It depends on the -ffast-math option. When we would like to call floor/floorf like v2 = floor (v1), we will convert it into below insns (reference the implementation of llvm). * vfcvt.x.f v3, v1, RDN

[PATCH v4] c++: Check for indirect change of active union member in constexpr [PR101631,PR102286]

Now that bootstrap has finished, I have gotten regressions in the following libstdc++ tests: Running libstdc++:libstdc++-dg/conformance.exp ... FAIL: 20_util/bitset/access/constexpr.cc -std=gnu++23 (test for excess errors) FAIL: 20_util/bitset/access/constexpr.cc -std=gnu++26 (test for excess

Re: [Committed] RISC-V: Extend VLS modes in 'VWEXTI' iterator

Hi Juzhe, I'm seeing a few new regressions from this patch on glibc rv32gcv. I filed a bugzilla for the ICE: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111546 Patrick On 9/19/23 19:24, Juzhe-Zhong wrote: This patch extends 'VWEXT' iterator so that we will support integer extension/integer

[PATCH] RISC-V/testsuite: Fix ILP32 RVV failures from missing

In non-multilib installations system headers may not be available for compilation options using a non-default model, causing build errors such as: In file included from .../include/features.h:527, from .../include/assert.h:35, from

Re: [Committed] RISC-V: Support VLS INT <-> FP conversions

Hi Juzhe, I was testing this patch and found it introduced a gfortran regression in gfortran.dg/host_assoc_function_7.f90. More info here: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111545 Edwin On 9/20/2023 7:17 PM, Juzhe-Zhong wrote: Support INT <-> FP VLS auto-vectorization patterns.

[PATCH] fortran: error recovery on duplicate declaration of class variable [PR95710]

Dear all, the attached simple and obvious patch fixes several NULL pointer dereferences that are encountered for a duplicate declaration of a class variable. Another one from Gerhard's torture tests... Regtested on x86_64-pc-linux-gnu. I intend to commit within 24h unless there are comments.

Re: [pushed] c++: unroll pragma in templates [PR111529]

On Fri, Sep 22, 2023 at 6:01 AM Jason Merrill wrote: > > Tested x86_64-pc-linux-gnu, applying to trunk. > > -- 8< -- > > We were failing to handle ANNOTATE_EXPR in tsubst_copy_and_build, leading to > problems with substitution of any wrapped expressions. > > Let's also not tell users that lambda

Re: [PATCH 02/13] [APX EGPR] middle-end: Add index_reg_class with insn argument.

On 9/22/23 06:56, Hongyu Wang wrote: Like base_reg_class, INDEX_REG_CLASS also does not support backend insn. Add index_reg_class with insn argument for lra/reload usage. gcc/ChangeLog: * addresses.h (index_reg_class): New wrapper function like base_reg_class. *

Re: [PATCH 01/13] [APX EGPR] middle-end: Add insn argument to base_reg_class

On 9/22/23 06:56, Hongyu Wang wrote: From: Kong Lingling Current reload infrastructure does not support selective base_reg_class for backend insn. Add new macros with insn parameters to base_reg_class for lra/reload usage. gcc/ChangeLog: * addresses.h (base_reg_class): Add insn

[PATCH v4] c++: Check for indirect change of active union member in constexpr [PR101631,PR102286]

On Fri, Sep 22, 2023 at 02:21:15PM +0100, Jason Merrill wrote: > On 9/21/23 09:41, Nathaniel Shead wrote: > > I've updated the error messages, and also fixed another bug I found > > while retesting (value-initialised unions weren't considered to have any > > active member yet). > > > >

[pushed] c++ __integer_pack conversion again [PR111357]

Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- As Jakub pointed out, the real problem here is that in a partial substitution we're forgetting the conversion to the type of the non-type template argument, because maybe_convert_nontype_argument doesn't do anything with value-dependent

[pushed] c++: constexpr and designated initializer

Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- The change of active member being non-constant (before C++20) results in a CONSTRUCTOR with a null value for the first field, don't crash. gcc/cp/ChangeLog: * constexpr.cc (free_constructor): Handle null ce->value.

Re: [PATCH v3] c++: Catch indirect change of active union member in constexpr [PR101631]

On 9/21/23 09:41, Nathaniel Shead wrote: I've updated the error messages, and also fixed another bug I found while retesting (value-initialised unions weren't considered to have any active member yet). Bootstrapped and regtested on x86_64-pc-linux-gnu. -- >8 -- This patch adds checks for

[pushed] c++: unroll pragma in templates [PR111529]

Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- We were failing to handle ANNOTATE_EXPR in tsubst_copy_and_build, leading to problems with substitution of any wrapped expressions. Let's also not tell users that lambda templates are available in C++14. PR c++/111529

RE: [PATCH v2] RISC-V: Refine the code gen for ceil auto vectorization.

Committed, thanks Juzhe. Pan From: juzhe.zh...@rivai.ai Sent: Friday, September 22, 2023 8:19 PM To: Li, Pan2 ; gcc-patches Cc: Li, Pan2 ; Wang, Yanzhang ; kito.cheng Subject: Re: [PATCH v2] RISC-V: Refine the code gen for ceil auto vectorization. LGTM.

Re: [PATCH v2] RISC-V: Refine the code gen for ceil auto vectorization.

LGTM. juzhe.zh...@rivai.ai From: pan2.li Date: 2023-09-22 20:16 To: gcc-patches CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v2] RISC-V: Refine the code gen for ceil auto vectorization. From: Pan Li We vectorized below ceil code already. void test_ceil (float *out,

[PATCH v2] RISC-V: Refine the code gen for ceil auto vectorization.

From: Pan Li We vectorized below ceil code already. void test_ceil (float *out, float *in, int count) { for (unsigned i = 0; i < count; i++) out[i] = __builtin_ceilf (in[i]); } Before this patch: vfmv.v.xv4,fa0 // can be removed vfabs.v v0,v1 vmv1r.v v2,v1 // can be

RE: [PATCH v1] RISC-V: Refine the code gen for ceil auto vectorization.

Sure thing, will send V2 for this. Pan From: juzhe.zh...@rivai.ai Sent: Friday, September 22, 2023 7:26 PM To: Li, Pan2 ; gcc-patches Cc: Li, Pan2 ; Wang, Yanzhang ; kito.cheng Subject: Re: [PATCH v1] RISC-V: Refine the code gen for ceil auto vectorization. I prefer change

Re: [PATCH v2 1/2] c++: Initial support for P0847R7 (Deducing This) [PR102609]

On 9/21/23 07:28, waffl3x wrote: This seems like a reasonable place for it since 'this' is supposed to precede the decl-specifiers, and since we are parsing initial attributes here rather than in the caller. You will want to give an error if found_decl_spec is set. And elsewhere complain about

Re: [PATCH v1] RISC-V: Refine the code gen for ceil auto vectorization.

I prefer change expand_vec_copysign into emit_vec_copysign。 Likewise， emit_fabs. ...etc. juzhe.zh...@rivai.ai From: pan2.li Date: 2023-09-22 19:19 To: gcc-patches CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] RISC-V: Refine the code gen for ceil auto vectorization.

[PATCH v1] RISC-V: Refine the code gen for ceil auto vectorization.

From: Pan Li We vectorized below ceil code already. void test_ceil (float *out, float *in, int count) { for (unsigned i = 0; i < count; i++) out[i] = __builtin_ceilf (in[i]); } Before this patch: vfmv.v.xv4,fa0 // can be removed vfabs.v v0,v1 vmv1r.v v2,v1 // can be

[PATCH 09/13] [APX EGPR] Handle legacy insn that only support GPR16 (1/5)

From: Kong Lingling These legacy insn in opcode map0/1 only support GPR16, and do not have vex/evex counterpart, directly adjust constraints and add gpr32 attr to patterns. insn list: 1. xsave/xsave64, xrstor/xrstor64 2. xsaves/xsaves64, xrstors/xrstors64 3. xsavec/xsavec64 4.

[PATCH 13/13] [APX EGPR] Handle vex insns that only support GPR16 (5/5)

From: Kong Lingling These vex insn may have legacy counterpart that could support EGPR, but they do not have evex counterpart. Split out its vex part from patterns and set the vex part to non-EGPR supported by adjusting constraints and attr_gpr32. insn list: 1. vmovmskpd/vmovmskps 2. vpmovmskb

[PATCH 08/13] [APX EGPR] Handle GPR16 only vector move insns

For vector move insns like vmovdqa/vmovdqu, their evex counterparts requrire explicit suffix 64/32/16/8. The usage of these instruction are prohibited under AVX10_1 or AVX512F, so for we select vmovaps/vmovups for vector load/store insns that contains EGPR if ther is no AVX512VL, and keep the

[PATCH 10/13] [APX EGPR] Handle legacy insns that only support GPR16 (2/5)

From: Kong Lingling These legacy insns in opcode map2/3 have vex but no evex counterpart, disable EGPR for them by adjusting alternatives and attr_gpr32. insn list: 1. phaddw/vphaddw, phaddd/vphaddd, phaddsw/vphaddsw 2. phsubw/vphsubw, phsubd/vphsubd, phsubsw/vphsubsw 3. psignb/vpsginb,

[PATCH 06/13] [APX EGPR] Add backend hook for base_reg_class/index_reg_class.

From: Kong Lingling Add backend helper functions to verify if a rtx_insn can adopt EGPR to its base/index reg of memory operand. The verification rule goes like 1. For asm insn, enable/disable EGPR by ix86_apx_inline_asm_use_gpr32. 2. Disable EGPR for unrecognized insn. 3. If

[PATCH 12/13] [APX_EGPR] Handle legacy insns that only support GPR16 (4/5)

From: Kong Lingling The APX enabled hardware should also be AVX10 enabled, thus for map2/3 insns with evex counterpart, we assume auto promotion to EGPR under APX_F if the insn uses GPR32. So for below insns, we disabled EGPR usage for their sse mnenomics, while allowing egpr generation of their

[PATCH 04/13] [APX EGPR] Add 16 new integer general purpose registers

From: Kong Lingling Extend GENERAL_REGS with extra r16-r31 registers like REX registers, named as REX2 registers. They will only be enabled under TARGET_APX_EGPR. gcc/ChangeLog: * config/i386/i386-protos.h (x86_extended_rex2reg_mentioned_p): New function prototype. *

[PATCH 11/13] [APX EGPR] Handle legacy insns that only support GPR16 (3/5)

From: Kong Lingling Disable EGPR usage for below legacy insns in opcode map2/3 that have vex but no evex counterpart. insn list: 1. phminposuw/vphminposuw 2. ptest/vptest 3. roundps/vroundps, roundpd/vroundpd, roundss/vroundss, roundsd/vroundsd 4. pcmpestri/vpcmpestri, pcmpestrm/vpcmpestrm

[PATCH 01/13] [APX EGPR] middle-end: Add insn argument to base_reg_class

From: Kong Lingling Current reload infrastructure does not support selective base_reg_class for backend insn. Add new macros with insn parameters to base_reg_class for lra/reload usage. gcc/ChangeLog: * addresses.h (base_reg_class): Add insn argument and new macro

[PATCH 03/13] [APX_EGPR] Initial support for APX_F

From: Kong Lingling Add -mapx-features= enumeration to separate subfeatures of APX_F. -mapxf is treated same as previous ISA flag, while it sets -mapx-features=apx_all that enables all subfeatures. gcc/ChangeLog: * common/config/i386/cpuinfo.h (XSTATE_APX_F): New macro.

[PATCH 07/13] [APX EGPR] Map reg/mem constraints in inline asm to non-EGPR constraint.

From: Kong Lingling In inline asm, we do not know if the insn can use EGPR, so disable EGPR usage by default via mapping the common reg/mem constraint to non-EGPR constraints. The full list of mapping goes like "g" -> "jrjmi" "r" -> "jr" "m" -> "jm" "<" -> "j<" ">" -> "j>" "o" ->

[PATCH 05/13] [APX EGPR] Add register and memory constraints that disallow EGPR

From: Kong Lingling For APX, as we extended the GENERAL_REG_CLASS, new constraints are needed to restrict insns that cannot adopt EGPR either in its reg or memory operands. We added a series of constraints for general/backend ones that related to GPR usage. All of them are prefixed with "j" to

[PATCH 02/13] [APX EGPR] middle-end: Add index_reg_class with insn argument.

Like base_reg_class, INDEX_REG_CLASS also does not support backend insn. Add index_reg_class with insn argument for lra/reload usage. gcc/ChangeLog: * addresses.h (index_reg_class): New wrapper function like base_reg_class. * doc/tm.texi: Document INSN_INDEX_REG_CLASS.

[PATCH v2 00/13] Support Intel APX EGPR

Hi, This is a v2 patch for APX support which follows-up previous discussion in https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628904.html As discussed in previous thread, the inverse approach to extend base/index reg support with new memory constraints requrires much more effort both in

[PATCH] light expander sra

Hi, There are a few PRs (meta-bug PR101926) on various targets. The root causes of them are similar: the aggeragte param/ returns are passed by multi-registers, but they are stored to stack from registers first; and then, access the parameter through stack slot. This would lead to generating

RE: [PATCH v1] RISC-V: Move ceil test cases to unop folder

Committed, thanks Juzhe. Pan From: juzhe.zh...@rivai.ai Sent: Friday, September 22, 2023 5:14 PM To: Li, Pan2 ; gcc-patches Cc: Li, Pan2 ; Wang, Yanzhang ; kito.cheng Subject: Re: [PATCH v1] RISC-V: Move ceil test cases to unop folder ok

Re: [PATCH] c++: improve class NTTP object pretty printing [PR111471]

On 9/21/23 11:53, Jason Merrill wrote: On 9/20/23 10:13, Patrick Palka wrote: On Tue, 19 Sep 2023, Patrick Palka wrote: On Tue, 19 Sep 2023, Jason Merrill wrote: On 9/19/23 12:40, Patrick Palka wrote: Tested on x86_64-pc-linux-gnu, does this look OK for trunk/13? OK for trunk.  What's

Re: [PATCH v1] RISC-V: Move ceil test cases to unop folder

ok juzhe.zh...@rivai.ai From: pan2.li Date: 2023-09-22 17:11 To: gcc-patches CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] RISC-V: Move ceil test cases to unop folder From: Pan Li gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/math-ceil-0.c: Moved

[PATCH v1] RISC-V: Move ceil test cases to unop folder

From: Pan Li gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/math-ceil-0.c: Moved to... * gcc.target/riscv/rvv/autovec/unop/math-ceil-0.c: ...here. * gcc.target/riscv/rvv/autovec/math-ceil-1.c: Moved to... *

[PING] [PATCH v2] aarch64: Fine-grained ldp and stp policies with test-cases.

Kind ping for reviewing this patch. It's tested and does not cause regressions: https://patchwork.sourceware.org/project/gcc/patch/20230828143744.7574-1-manos.anagnosta...@vrull.eu/ Thank you in advance! On Mon, Aug 28, 2023 at 5:37 PM Manos Anagnostakis < manos.anagnosta...@vrull.eu> wrote: >

[Committed] RISC-V: Remove @ of vec_duplicate pattern

It's obvious the @ of vec_duplicate pattern is duplicate. Regression passed. Committed. gcc/ChangeLog: * config/riscv/riscv-v.cc (gen_const_vector_dup): Use global expand function. * config/riscv/vector.md (@vec_duplicate): Remove @. (vec_duplicate): Ditto. ---

[PATCH 3/3] aarch64: Convert aarch64 multi choice patterns to new syntax

[Resending this with the patch compressed as it's more than 400 KB...] Hi all, this patch converts a number of multi multi choice patterns within the aarch64 backend to the new syntax. The list of the converted patterns is in the Changelog. For completeness here follows the list of multi choice

[PATCH 1/3] recog: Improve parser for pattern new compact syntax

From: Richard Sandiford Hi all, this is to add support to the new compact pattern syntax for the case where the constraints do appear unsorted like: (define_insn "*si3_insn_uxtw" [(set (match_operand:DI 0 "register_operand") (zero_extend:DI (SHIFT_no_rotate:SI

[PATCH 2/3] recog: Support space in "[ cons"

Hi all, this is to allow for spaces before "cons:" in the definitions of patterns using the new compact syntax, ex: (define_insn "aarch64_simd_dup" [(set (match_operand:VDQ_I 0 "register_operand") (vec_duplicate:VDQ_I (match_operand: 1 "register_operand")))] "TARGET_SIMD"

[PATCH] RISC-V: Add VLS conditional patterns support

Regression passed. Committed. gcc/ChangeLog: * config/riscv/autovec.md: Add VLS conditional patterns. * config/riscv/riscv-protos.h (expand_cond_unop): Ditto. (expand_cond_binop): Ditto. (expand_cond_ternop): Ditto. * config/riscv/riscv-v.cc

[PATCH 2/2] RISC-V: Fix ICE by expansion and register coercion

From: Tsukasa OI A "prefetch" instruction on RISC-V GCC emits a machine hint instruction directly when the 'Zicbop' extension is enabled but it could cause an ICE when the address argument of __builtin_prefetch is a integral constant (such like 0 [NULL] or some other [but possibly not all] fixed

[PATCH 1/2] RISC-V: Define not broken prefetch builtins

From: Tsukasa OI __builtin_riscv_zicbop_cbo_prefetchi (corresponding "prefetch.i" instruction from the 'Zicbop' extension) is completely broken and new builtin is required for replacement. However, it required more than defining new builtin and/or instruction. 1. Support for variable argument

[PATCH 0/2] RISC-V: Define not broken prefetch builtins

Hello, As I explained earlier: , the builtin function for RISC-V "__builtin_riscv_zicbop_cbo_prefetchi" is completely broken. Instead, this patch set (in PATCH 1/2) creates three new, working builtin intrinsics. void

[PATCH v1] RISCV-V: Suport FP floor auto-vectorization

From: Pan Li This patch would like to support auto-vectorization for the floor API in math.h. It depends on the -ffast-math option. When we would like to call floor/floorf like v2 = floor (v1), we will convert it into below insns (reference the implementation of llvm). * vfcvt.x.f v3, v1, RDN