Re: [PATCH 1/7] ira: Refactor the handling of register conflicts to make it more general

On Wed, Nov 8, 2023 at 4:48 AM Lehua Ding wrote: > > This patch does not make any functional changes. It mainly refactor two parts: > > 1. The ira_allocno's objects field is expanded to an scalable array, and > multi-word >pseduo registers are split and tracked only when necessary. > 2.

Re: [V2 PATCH] Handle bitop with INTEGER_CST in analyze_and_compute_bitop_with_inv_effect.

On Wed, Nov 8, 2023 at 2:18 AM Hongtao Liu wrote: > > On Tue, Nov 7, 2023 at 10:34 PM Richard Biener > wrote: > > > > On Tue, Nov 7, 2023 at 2:03 PM Hongtao Liu wrote: > > > > > > On Tue, Nov 7, 2023 at 4:10 PM Richard Biener > > > wrote: > > > > > > > > On Tue, Nov 7, 2023 at 7:08 AM liuhongt

RE: [PATCH V2] test: Fix bb-slp-33.c for RVV

Committed, thanks Richard. Pan -Original Message- From: Richard Biener Sent: Wednesday, November 8, 2023 2:58 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org Subject: Re: [PATCH V2] test: Fix bb-slp-33.c for RVV On Tue, 7 Nov 2023, Juzhe-Zhong wrote: > gcc/testsuite/ChangeLog: OK.

Re: [PATCH] [i386] APX: Fix ICE due to movti postreload splitter [PR112394]

On Tue, Nov 7, 2023 at 3:33 PM Hongyu Wang wrote: > > Hi, > > When APX EGPR enabled, the TImode move pattern *movti_internal allows > move between gpr and sse reg using constraint pair ("r","Yd"). Then a > post-reload splitter transform such move to vec_extractv2di, while under > -msse4.1

Re: [PATCH v2] c: Add -Wreturn-mismatch warning, split from -Wreturn-type

* Florian Weimer: > The existing -Wreturn-type option covers both constraint violations > (which are mandatory to diagnose) and warnings that have known > false positives. The new -Wreturn-mismatch warning is only about > the constraint violations (missing or extra return expressions), > and

Re: [PATCH V2] test: Fix bb-slp-33.c for RVV

On Tue, 7 Nov 2023, Juzhe-Zhong wrote: > gcc/testsuite/ChangeLog: OK. > * gcc.dg/vect/bb-slp-33.c: Rewrite the condition. > > --- > gcc/testsuite/gcc.dg/vect/bb-slp-33.c | 35 --- > 1 file changed, 26 insertions(+), 9 deletions(-) > > diff --git

[PATCH] libgcc: Add {unsigned ,}__int128 <-> _Decimal{32,64,128} conversion support [PR65833]

Hi! The following patch adds the missing {unsigned ,}__int128 <-> _Decimal{32,64,128} conversion support into libgcc.a on top of the _BitInt support (doing it without that would be larger amount of code and I hope all the targets which support __int128 will eventually support _BitInt, after all

Re: Re: [PATCH] RISC-V: Normalize user vsetvl intrinsics[PR112092]

On Wed, Nov 8, 2023 at 2:37 PM juzhe.zh...@rivai.ai wrote: > > Another question raise to me. > > Is it necessary we have such many variant of vsetvls? > > I am thinking about redesign: > > __riscv_vsetvl_e8mf8 > __riscv_vsetvl_e16mf4 > __riscv_vsetvl_e32mf2 > __riscv_vsetvl_e64m1 > > They are

Re: [PATCH] RISC-V: Nan-box the result of movhf on soft-fp16

Thanks for the patch!! We also found the same issue on internal testing works and trying to figure out how to resolve that issue yet, this patch is little bit magic, let me take a closer look.. :P On Wed, Nov 8, 2023 at 11:08 AM KuanLin Chen wrote: > > According to spec, fmv.h checks if the

Re: Re: [PATCH] RISC-V: Normalize user vsetvl intrinsics[PR112092]

Another question raise to me. Is it necessary we have such many variant of vsetvls? I am thinking about redesign: __riscv_vsetvl_e8mf8 __riscv_vsetvl_e16mf4 __riscv_vsetvl_e32mf2 __riscv_vsetvl_e64m1 They are quite redundant. They have the same result. May be just design as :

Re: Re: [PATCH] RISC-V: Normalize user vsetvl intrinsics[PR112092]

OK, then LGTM, thanks for the explanation :) On Wed, Nov 8, 2023 at 2:33 PM juzhe.zh...@rivai.ai wrote: > > More details: > > bb 1 bb 2 > \/ >bb 3 > > VSETVL PASS can only do VSETVL demand fusion, fuse demand from bb 3 to bb 1, > and fuse demand from bb 3 to bb2. > We are not able

Re: Re: [PATCH] RISC-V: Normalize user vsetvl intrinsics[PR112092]

More details: bb 1 bb 2 \/ bb 3 VSETVL PASS can only do VSETVL demand fusion, fuse demand from bb 3 to bb 1, and fuse demand from bb 3 to bb2. We are not able to remove block bb 1 and bb 2 and create new bb 4 to hold the vsetvl if bb 1 and bb 2 has the same vsetvl: bb 4 (new block)

Re: Re: [PATCH] RISC-V: Normalize user vsetvl intrinsics[PR112092]

before VSETVL PASS. The code is as follows: bb 1: vsetvli e16mf2 -> set a6 bb 2: vsetvli e32m1 -> set a6 bb 3: ... vle (use a6) e32m1 TU vle (use a6) e32m1 TU vse (use a6) e32m1 TU VSETVL PASS only do VSETVL information fusion, it doesn't do the CFG block fusion. VSETVL PASS succeed on

Re: [PATCH] RISC-V: Normalize user vsetvl intrinsics[PR112092]

I thought vsetvli insertion will try to merge them into one for those cases? Could you explain few more reasons why they are not fused now? Not an objection since I could imageing that would be easier to process, just wondering why. On Wed, Nov 8, 2023 at 2:11 PM Juzhe-Zhong wrote: > > Since our

[PATCH] RISC-V: Normalize user vsetvl intrinsics[PR112092]

Since our user vsetvl intrinsics are defined as just calculate the VL output which is the number of the elements to be processed. Such intrinsics do not have any side effects. We should normalize them when they have same ratio. E.g __riscv_vsetvl_e8mf8 result is same as __riscv_vsetvl_e64m1.

Re: [PATCH][_Hashtable] Add missing destructor call

On 07/11/2023 00:28, Jonathan Wakely wrote: On Mon, 6 Nov 2023 at 21:39, François Dumont wrote: Noticed looking for other occasion to replace __try/__catch with RAII helper. libstdc++: [_Hashtable] Add missing node destructor call libstdc++-v3/ChangeLog: *

Re: [PATCH 0/7] ira/lra: Support subreg coalesce

Thanks Lehua. Appreciate for supporting subreg liveness tracking with tons of work. A nit comments, I think you should mention these following PRs: 106694 89967 106146 99161 No need send V2 now. You can send V2 after Richard and Vlad reviewed. juzhe.zh...@rivai.ai From: Lehua Ding Date:

[PATCH 6/7] lra: Apply live_subreg df_problem to lra pass

This patch change the use of old live data to the new live_subreg data. gcc/ChangeLog: * lra-coalesce.cc (update_live_info): Update. (lra_coalesce): Update. * lra-constraints.cc (update_ebb_live_info): Update. (get_live_on_other_edges): Update.

[PATCH 4/7] ira: Support subreg copy

This patch change the copy between allocno and allocno to the copy between object and object, that is, allow partial copy between pseudo registers. gcc/ChangeLog: * ira-build.cc (find_allocno_copy): Removed. (ira_create_object): Adjust. (find_object): New.

[PATCH 3/7] ira: Support subreg live range track

This patch extends the reg live range in ira to track the lifecycle of subreg, thus enabling more granular tracking of the live range and conflict of a pseudo subreg part. This patch will divide allocno into two categories: one has single object, and the other is the case where it contains subreg

[PATCH 7/7] lra: Support subreg live range track and conflict detect

This patch implements tracking of the live range of subregs and synchronously modifies conflict detection. gcc/ChangeLog: * ira-build.cc (print_copy): Adjust print. (setup_pseudos_has_subreg_object): New. (ira_build): collect subreg object allocno. *

[PATCH 5/7] ira: Add all nregs >= 2 pseudos to tracke subreg list

This patch completely relax to track all eligible subregs. gcc/ChangeLog: * ira-build.cc (get_reg_unit_size): New. (has_same_nregs): New. (ira_set_allocno_class): Relax. --- gcc/ira-build.cc | 41 - 1 file changed, 36

[PATCH 2/7] ira: Add live_subreg problem and apply to ira pass

This patch adds a live_subreg problem to extend the original live_reg to track the lifecycle of subreg. At the same time, this old live data is replaced by the new live data in ira pass. gcc/ChangeLog: * Makefile.in: Add subreg-live-range.o * df-problems.cc (struct

[PATCH 1/7] ira: Refactor the handling of register conflicts to make it more general

This patch does not make any functional changes. It mainly refactor two parts: 1. The ira_allocno's objects field is expanded to an scalable array, and multi-word pseduo registers are split and tracked only when necessary. 2. Since the objects array has been expanded, there will be more

[PATCH 0/7] ira/lra: Support subreg coalesce

Hi, These patchs try to support subreg coalesce feature in register allocation passes (ira and lra). Let's consider a RISC-V program (https://godbolt.org/z/ec51d91aT): ``` #include void foo (int32_t *in, int32_t *out, size_t m) { vint32m2_t result = __riscv_vle32_v_i32m2 (in, 32);

[PATCH] diagnostics: pch: Remember diagnostic pragmas in a PCH [PR64117]

Hello- https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64117 This fixes an old PR / enhancement request. Bootstrap + regtest all languages on x86-64 Linux. Please let me know if it looks OK? Thanks! -Lewis -- >8 -- As the PR points out, we do not currently record in a PCH whether any diagnostics

[PATCH] RISC-V: Nan-box the result of movhf on soft-fp16

According to spec, fmv.h checks if the input operands are correctly NaN-boxed. If not, the input value is treated as an n-bit canonical NaN. This patch fixs the issue that operands returned by soft-fp16 libgcc (i.e., __truncdfhf2) was not correctly NaN-boxed. *gcc/ChangeLog:* *

PING^4 [PATCH v2] rs6000: Don't use optimize_function_for_speed_p too early [PR108184]

Hi, Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2023-January/609993.html BR, Kewen >>> on 2023/1/16 17:08, Kewen.Lin via Gcc-patches wrote: Hi, As Honza pointed out in [1], the current uses of function optimize_function_for_speed_p in

PING^6 [PATCH 0/9] rs6000: Rework rs6000_emit_vector_compare

Hi, Gentle ping this series: https://gcc.gnu.org/pipermail/gcc-patches/2022-November/607146.html BR, Kewen > on 2022/11/24 17:15, Kewen Lin wrote: >> Hi, >> >> Following Segher's suggestion, this patch series is to rework >> function rs6000_emit_vector_compare for vector

PING^1 [PATCH v3] sched: Change no_real_insns_p to no_real_nondebug_insns_p [PR108273]

Hi, Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2023-October/634201.html BR, Kewen on 2023/10/25 10:45, Kewen.Lin wrote: > Hi, > > This is almost a repost for v2 which was posted at[1] in March > excepting for: > 1) rebased from r14-4810 which is relatively up-to-date, >

Re: [PATCH 07/12] mode-switching: Allow targets to set the mode for EH handlers

On 11/7/23 17:15, Richard Sandiford wrote: Thanks for the reviews. Jeff Law writes: On 11/5/23 11:48, Richard Sandiford wrote: The mode-switching pass already had hooks to say what mode an entity is in on entry to a function and what mode it must be in on return. For SME, we also want to

Re: [PATCH 10/12] mode-switching: Use 1-based edge aux fields

On 11/7/23 17:35, Richard Sandiford wrote: I could have sworn that there was something that checked that passes left edge aux fields clear, but it looks like I misremembered. So I probably need to stick a clear_aux_for_edges () call above the first main loop (for 12/12) and keep the

Re: [PATCH] LoongArch: Remove redundant barrier instructions before LL-SC loops

在 2023/11/6 下午7:36, Xi Ruoyao 写道: This is isomorphic to the LLVM changes [1-2]. On LoongArch, the LL and SC instructions has memory barrier semantics: - LL: + - SC: + But the compare and swap operation is allowed to fail, and if it fails the SC instruction is not executed, thus the

Re: [V2 PATCH] Handle bitop with INTEGER_CST in analyze_and_compute_bitop_with_inv_effect.

On Tue, Nov 7, 2023 at 10:34 PM Richard Biener wrote: > > On Tue, Nov 7, 2023 at 2:03 PM Hongtao Liu wrote: > > > > On Tue, Nov 7, 2023 at 4:10 PM Richard Biener > > wrote: > > > > > > On Tue, Nov 7, 2023 at 7:08 AM liuhongt wrote: > > > > > > > > analyze_and_compute_bitop_with_inv_effect

Re: [PATCH 1/2] libdiagnostics: header and examples

On Tue, 2023-11-07 at 19:02 -0500, Lewis Hyatt wrote: > On Mon, Nov 6, 2023 at 8:29 PM David Malcolm > wrote: > > > > Here's a work-in-progress patch for GCC that adds a > > libdiagnostics.h > > header describing the public interface, along with various > > testcases > > that show usage examples

Re: [PATCH 10/12] mode-switching: Use 1-based edge aux fields

Jeff Law writes: > On 11/5/23 11:49, Richard Sandiford wrote: >> The pass used the edge aux field to record which mode change >> should happen on the edge, with -1 meaning "none". It's more >> convenient for later patches to leave aux zero for "none", >> and use numbers based at 1 to record a

[committed] testsuite: Rename c2x-*, gnu2x-* tests to c23-*, gnu23-*

Completing the move to refer to C23 in place of C2X, rename all tests with "c2x" or "gnu2x" in their names to use "c23" or "gnu23" instead. 17 files in the testsuite that referred to such tests (or, in one case, a generated .i file to be scanned) by those names are updated for the renaming.

Re: [PATCH 07/12] mode-switching: Allow targets to set the mode for EH handlers

Thanks for the reviews. Jeff Law writes: > On 11/5/23 11:48, Richard Sandiford wrote: >> The mode-switching pass already had hooks to say what mode >> an entity is in on entry to a function and what mode it must >> be in on return. For SME, we also want to say what mode an >> entity is

Re: [PATCH 1/2] libdiagnostics: header and examples

On Mon, Nov 6, 2023 at 8:29 PM David Malcolm wrote: > > Here's a work-in-progress patch for GCC that adds a libdiagnostics.h > header describing the public interface, along with various testcases > that show usage examples for the API. Various aspects of this need > work; posting now for early

Re: [C PATCH 6/6] c23: construct composite type for tagged types

On Sat, 26 Aug 2023, Martin Uecker via Gcc-patches wrote: > @@ -501,9 +510,61 @@ composite_type (tree t1, tree t2) > return build_type_attribute_variant (t1, attributes); >} > > -case ENUMERAL_TYPE: > case RECORD_TYPE: > case UNION_TYPE: > + if (flag_isoc2x &&

Re: [PATCH v1] RISC-V: Support FP rint to i/l/ll diff size autovec

Thanks for pointing this out Juzhe, we're investigating how the CI got confused here. We'll let you know what we find out. Patrick On 11/7/23 14:48, 钟居哲 wrote: Plz note those FAILs are not caused by this patch. They are caused by this commit:

Re: [C PATCH 4/6] c23: tag compatibility rules for enums

On Sat, 26 Aug 2023, Martin Uecker via Gcc-patches wrote: > Allow redefinition of enum types and enumerators. > > gcc/c: > * c-decl.cc (start_num): Allow redefinition. start_enum not start_num. > @@ -9606,9 +9624,15 @@ start_enum (location_t loc, struct c_enum_contents > *the_enum, tree

Re: [PATCH 2/5] aarch64: Add support for GCS system registers with the +gcs modifier

Victor Do Nascimento writes: > Given the introduction of system registers associated with the Guarded > Control Stack extension to Armv9.4-a in Binutils and their reliance on > the `+gcs' modifier, we implement the necessary changes in GCC to > allow for them to be recognized by the compiler. > >

Re: [C PATCH 3/6] c23: tag compatibility rules for struct and unions

On Sat, 26 Aug 2023, Martin Uecker via Gcc-patches wrote: > types (convert_for_assignment): Ingore qualifiers. "Ignore". > @@ -1993,6 +1993,24 @@ locate_old_decl (tree decl) > decl, TREE_TYPE (decl)); > } > > +static tree > +previous_tag (tree type) This function needs a

Re: [PATCH 1/5] aarch64: Add march flags for +the and +d128 arch extensions

Victor Do Nascimento writes: > Given the introduction of optional 128-bit page table descriptor and > translation hardening extension support with the Arm9.4-a > architecture, this introduces the relevant flags to enable the reading > and writing of 128-bit system registers. > > The `+d128'

Re: [PATCH 3/5] aarch64: Sync `aarch64-sys-regs.def' with Binutils.

Victor Do Nascimento writes: > This patch updates `aarch64-sys-regs.def', bringing it into sync with > the Binutils source. > > gcc/ChangeLog: > > * config/aarch64/aarch64-sys-regs.def (par_el1): New. > (rcwmask_el1): Likewise. > (rcwsmask_el1): Likewise. > (ttbr0_el1):

Re: [PATCH 4/5] aarch64: Implement 128-bit extension to ACLE sysreg r/w builtins

Victor Do Nascimento writes: > Implement the ACLE builtins for 128-bit system register manipulation: > > * __uint128_t __arm_rsr128(const char *special_register); > * void __arm_wsr128(const char *special_register, __uint128_t value); > > gcc/ChangeLog: > > *

RE: [PATCH 5/21]middle-end: update vectorizer's control update to support picking an exit other than loop latch

> -Original Message- > From: Richard Biener > Sent: Tuesday, November 7, 2023 3:04 PM > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org; nd ; j...@ventanamicro.com > Subject: Re: [PATCH 5/21]middle-end: update vectorizer's control update to > support picking an exit other than loop

Re: [C PATCH 2/6] c23: recursive type checking of tagged type

On Sat, 26 Aug 2023, Martin Uecker via Gcc-patches wrote: > Adapt the old and unused code for type checking for C23. > > gcc/c/: > * c-typeck.c (struct comptypes_data): Add anon_field flag. > (comptypes, comptypes_check_unum_int, > comptypes_check_different_types): Remove old

Re: [PATCH 5/5] aarch64: Add rsr128 and wsr128 ACLE tests

Victor Do Nascimento writes: > Extend existing unit tests for the ACLE system register manipulation > functions to include 128-bit tests. > > gcc/testsuite/ChangeLog: > > * gcc/testsuite/gcc.target/aarch64/acle/rwsr.c (get_rsr128): New. > (set_wsr128): Likewise. > --- >

Re: Re: [PATCH v1] RISC-V: Support FP rint to i/l/ll diff size autovec

Plz note those FAILs are not caused by this patch. They are caused by this commit: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=0c42741ad95af3a1e3ac07350da4c3a94865ed63 It seems that precommit CI faild to locate the real root cause. juzhe.zh...@rivai.ai From: Patrick O'Neill Date:

Re: [PATCH] openmp: Add support for the 'indirect' clause in C/C++

Yes, I believe that is the right fix. The version in libgomp/config/accel/ should then override the version in libgomp/ for accelerator targets. I'll do a quick check that this works as expected and push it ASAP. Sorry for breaking the build for so many targets! Kwok On 07/11/2023 9:51 pm,

Re: [PATCH] openmp: Add support for the 'indirect' clause in C/C++

On Tue, Nov 07, 2023 at 09:37:22PM +, Joseph Myers wrote: > This looks like targets that libgomp/configure.tgt does *not* have any > special handling for, and so never adds "linux" to config_path for. Indeed, I don't really see anything linux specific about the

Re: [PATCH] openmp: Add support for the 'indirect' clause in C/C++

I'm seeing build failures "make[5]: *** No rule to make target 'target-indirect.c', needed by 'target-indirect.lo'. Stop." for many targets in my glibc bot. https://sourceware.org/pipermail/libc-testresults/2023q4/012061.html FAIL: compilers-arc-linux-gnu gcc build FAIL:

Re: [PATCH v3] c-family: Enable -fpermissive for C and ObjC

On Tue, 7 Nov 2023, Florian Weimer wrote: > Future changes will treat some C front end warnings similar to > -Wnarrowing. > > gcc/ > > * doc/invoke.texi (Warning Options): Mention C diagnostics > for -fpermissive. > > gcc/c-family/ > > * c.opt (fpermissive): Enable for C and

[committed] c: Change T2X_* format checking macros to T23_*

Analogous to previous changes to code that matched "c2x" (case-insensitive), also update T2X_* macros used in format checking tables to be named T23_*. Bootstrapped with no regressions for x86_64-pc-linux-gnu. gcc/c-family/ * c-format.h (T2X_UI): Rename to T23_UI. (T2X_UL):

Re: [PATCH] c++: decltype of (by-value captured reference) [PR79620]

On Tue, 7 Nov 2023, Patrick Palka wrote: > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look > OK for trunk? > > -- >8 -- > > The capture decltype handling in finish_decltype_type wasn't looking > through implicit INDIRECT_REF (added by convert_from_reference), which > caused us

[PATCH] c++: decltype of (by-value captured reference) [PR79620]

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- The capture decltype handling in finish_decltype_type wasn't looking through implicit INDIRECT_REF (added by convert_from_reference), which caused us to incorrectly resolve decltype((x)) to float& below. We

[PATCH] c++: decltype of capture proxy [PR79378, PR96917]

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- We usually don't see capture proxies in finish_decltype_type because process_outer_var_ref is a no-op inside an unevaluated context and so a use of a capture inside decltype refers directly to the captured

Re: [PATCH v1] RISC-V: Support FP rint to i/l/ll diff size autovec

Ah sorry for the noise - I just saw that this was resolved with a subsequent patch: Precommit run: https://github.com/ewlu/gcc-precommit-ci/issues/608#issuecomment-1798058721 Patrick On 11/7/23 11:17, Patrick O'Neill wrote: Hi Pan, This patch (9acea4376fd98696ba51e59f417c94911a4d8248)

Re: [PATCH v1] RISC-V: Support FP rint to i/l/ll diff size autovec

Hi Pan, This patch (9acea4376fd98696ba51e59f417c94911a4d8248) causes|||cond_widen_reduc-2.c to start failing on: linux/newlib: rv32/64gc ||linux/newlib: ||rv32gcv ||linux/newlib: ||rv32/64gc|_zba_zbb_zbc_zbs|||FAIL: gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c scan-assembler-times

[PATCH v3] c-family: Enable -fpermissive for C and ObjC

Future changes will treat some C front end warnings similar to -Wnarrowing. gcc/ * doc/invoke.texi (Warning Options): Mention C diagnostics for -fpermissive. gcc/c-family/ * c.opt (fpermissive): Enable for C and ObjC. * c-opts.cc (c_common_post_options): Enable

[committed] i386: Make flags_reg_operand a special predicate

There is no need to check the mode in flags_reg_operand predicate. The mode in flags setting instructions is checked with ix86_match_ccmode. The patch avoids "warning: operand X missing mode?" warnings with VOIDmode flags_reg_operand predicate. gcc/ChangeLog: * config/i386/predicates.md

Re: [PATCH v2 0/3] libgfortran: empty array fixes

Hi Mikael, this is OK. Thanks for the patches! Harald On 11/7/23 11:24, Mikael Morin wrote: Hello, Harald's review of the previous version [1] of these patches spotted a possible misbehaving case in one patch, and a latent bug in the area of the second patch. So here is the second try,

[PATCH] gcc/configure: Regenerate

On Mon, Nov 06 2023, Martin Jambor wrote: > [...] > > I'm not sure what that means, whether a wrong version of > autoconf/automake was used (though when I accidentally tried that, it > has always complained loudly) or if some environment difference can > cause this. Perhaps I should change the

Re: [PATCH] RISC-V: Use stdint-gcc.h in rvv testsuite

On Tue, 07 Nov 2023 01:45:19 PST (-0800), christoph.muell...@vrull.eu wrote: From: Christoph Müllner stdint.h can be replaced with stdint-gcc.h to resolve some missing system headers in non-multilib installations. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadmemidx-helpers.h:

[PATCH] aarch64: New RTL optimization pass avoid-store-forwarding.

This is an RTL pass that detects store forwarding from stores to larger loads (load pairs). This optimization is SPEC2017-driven and was found to be beneficial for some benchmarks, through testing on ampere1/ampere1a machines. For example, it can transform cases like str d5, [sp, #320] fmul

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Re: [PATCH] attribs: Fix ICE with -Wno-attributes= [PR112339]

On Fri, Nov 03, 2023 at 06:43:49PM -0400, Jason Merrill wrote: > LGTM but I'd like Marek to approve it. Both hunks look correct to me. Patch is OK, thanks! > On Fri, Nov 3, 2023, 3:12 PM Jakub Jelinek wrote: > > > Hi! > > > > The following testcase ICEs, because with

Re: [pushed] [RA]: Modify cost calculation for dealing with pseudo equivalences

Hey, This is causing an ICE. Bug here: 112337 � arm: ICE in arm_effective_regno when compiling for MVE (gnu.org) Regards, Saurabh From: Vladimir Makarov Sent: Thursday, October 26, 2023 3:00 PM To:

Re: [PATCH] binutils: experimental use of libdiagnostics in gas

On Tue, 2023-11-07 at 16:57 +0100, Clément Chigot wrote: > > > However, I'm not sure how you're planning to make the transition. > > > But > > > currently, it looks like libdiagnostics is either enabled and > > > thus > > > the > > > new format being produced, either it's not and we do have the >

Re: [PATCH] binutils: experimental use of libdiagnostics in gas

> > However, I'm not sure how you're planning to make the transition. But > > currently, it looks like libdiagnostics is either enabled and thus > > the > > new format being produced, either it's not and we do have the legacy > > format. I think the transition should be smoother than that, there >

Re: [PATCH] testsuite: nodiscard-reason-nonstring.C FAIL in C++26

On Tue, Nov 07, 2023 at 10:50:42AM -0500, Marek Polacek wrote: > Tested on x86_64-pc-linux-gnu, ok for trunk? > > -- >8 -- > Since r14-5071, we emit an extra error for this test (the first one): > > nodiscard-reason-nonstring.C:5:13: error: expected string-literal before > numeric constant >

[PATCH] testsuite: nodiscard-reason-nonstring.C FAIL in C++26

Tested on x86_64-pc-linux-gnu, ok for trunk? -- >8 -- Since r14-5071, we emit an extra error for this test (the first one): nodiscard-reason-nonstring.C:5:13: error: expected string-literal before numeric constant nodiscard-reason-nonstring.C:5:36: error: 'nodiscard' attribute argument must be

Re: [PATCH 2/2] libdiagnostics: work-in-progress implementation

Am 07.11.2023 um 15:59 schrieb David Malcolm: On Tue, 2023-11-07 at 08:54 +0100, Simon Sobisch wrote: Thank you for our work and providing this patch. GCC related questions: Is it planned to change GCC diagnostics to use libdiagnostic itself? No. GCC uses C++ internally, and the

[committed] OpenMP: invoke.texi - mention C attribute syntax for -fopenmp(-simd)

This is a followup to Jakub's commits that add OpenMP [[omp::...]] C23 attribute support; namely, this updates invoke.texi's -fopenmp/-fopenmp-simd entries. Cf. https://gcc.gnu.org/onlinedocs/gcc/C-Dialect-Options.html#index-fopenmp Committed as r14-5224-g75e5a467811da4 as obvious. Tobias PS:

[pushed] aarch64: Add a %Z operand modifier for SVE registers

This patch adds a %Z operand modifier that prints registers as SVE z registers. The SME patches need this, but so do Tamar's patches. I'm separating this out to unblock those. We should probably document the [wxbhsdqZ] modifiers as user-facing, but doing that for all of them is a separate patch.

Re: Re: [PATCH V2] test: Fix FAIL of pr97428.c for RVV

Yes! Thanks a lot. Fix as you suggested in V3: https://gcc.gnu.org/pipermail/gcc-patches/2023-November/635591.html juzhe.zh...@rivai.ai From: Richard Biener Date: 2023-11-07 21:50 To: Juzhe-Zhong CC: gcc-patches; jeffreyalaw Subject: Re: [PATCH V2] test: Fix FAIL of pr97428.c for RVV On

Re: Re: [PATCH] test: Fix bb-slp-33.c for RVV

Thanks Richi. Adapt condtion in V2: https://gcc.gnu.org/pipermail/gcc-patches/2023-November/635589.html juzhe.zh...@rivai.ai From: Richard Biener Date: 2023-11-07 21:48 To: Juzhe-Zhong CC: gcc-patches; jeffreyalaw Subject: Re: [PATCH] test: Fix bb-slp-33.c for RVV On Tue, 7 Nov 2023,

[PATCH V3] test: Fix FAIL of pr97428.c for RVV

gcc/testsuite/ChangeLog: * gcc.dg/vect/pr97428.c: Add additional compile option for riscv. --- gcc/testsuite/gcc.dg/vect/pr97428.c | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/testsuite/gcc.dg/vect/pr97428.c b/gcc/testsuite/gcc.dg/vect/pr97428.c index

[PATCH] c++: fix tf_decltype manipulation for COMPOUND_EXPR

bootstrapped and regtested on x86_64-pc-linxu-gnu, does this look OK for trunk? -- >8 -- In the COMPOUND_EXPR case of tsubst_expr, we were redundantly clearing the tf_decltype flag when substituting the LHS and also neglecting to propagate it when substituting the RHS. This patch corrects this

[PATCH V2] test: Fix bb-slp-33.c for RVV

gcc/testsuite/ChangeLog: * gcc.dg/vect/bb-slp-33.c: Rewrite the condition. --- gcc/testsuite/gcc.dg/vect/bb-slp-33.c | 35 --- 1 file changed, 26 insertions(+), 9 deletions(-) diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-33.c

Re: [PATCH] test: Recover sdiv_pow2 check and remove test of RISC-V

On Tue, 7 Nov 2023, Juzhe-Zhong wrote: > gcc/testsuite/ChangeLog: OK. > * gcc.dg/vect/vect-sdiv-pow2-1.c: Recover scan check. > * lib/target-supports.exp: Remove riscv. > > --- > gcc/testsuite/gcc.dg/vect/vect-sdiv-pow2-1.c | 2 +- > gcc/testsuite/lib/target-supports.exp|

Re: [PATCH 5/21]middle-end: update vectorizer's control update to support picking an exit other than loop latch

On Mon, 6 Nov 2023, Tamar Christina wrote: > Hi All, > > As requested, the vectorizer is now free to pick it's own exit which can be > different than what the loop CFG infrastucture uses. The vectorizer makes use > of this to vectorize loops that it previously could not. > > But this means

Re: [PATCH] binutils: experimental use of libdiagnostics in gas

On 07.11.2023 15:32, David Malcolm wrote: > On Tue, 2023-11-07 at 11:03 +0100, Jan Beulich wrote: >> On 06.11.2023 23:29, David Malcolm wrote: >>> All of the locations are just lines; does gas do column numbers at >>> all? >>> (or ranges?) >> >> It currently doesn't, which is primarily related to

Re: [PATCH 2/2] libdiagnostics: work-in-progress implementation

On Tue, 2023-11-07 at 08:54 +0100, Simon Sobisch wrote: > Thank you for our work and providing this patch. > > GCC related questions: > > Is it planned to change GCC diagnostics to use libdiagnostic itself? No. GCC uses C++ internally, and the internal diagnostic API is written in C++.

Re: [PATCH 6/21]middle-end: support multiple exits in loop versioning

On Mon, 6 Nov 2023, Tamar Christina wrote: > Hi All, > > This has loop versioning use the vectorizer's IV exit edge when it's available > since single_exit (..) fails with multiple exits. > > Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. > > Ok for master? > > Thanks, >

Re: [PATCH] binutils: experimental use of libdiagnostics in gas

On Tue, 2023-11-07 at 08:04 +0100, Simon Sobisch wrote: > Thank you very much for this proof-of-concept use! > > Inspecting it raises the following questions to me, both for a > possible > binutils implementation and for the library use in general: > > * How should the application set the

Re: Re: [PATCH] test: Fix FAIL of vect-sdiv-pow2-1.c for RVV test: Fix FAIL of vect-sdiv-pow2-1.c for RVV#

Ok. Sorry for inconvenience. Here is the patch to fix as you suggested: https://gcc.gnu.org/pipermail/gcc-patches/2023-November/635580.html I disabled this test, instead, I will add it into riscv specific testsuite list. Thanks. juzhe.zh...@rivai.ai From: Richard Biener Date: 2023-11-07

Re: [PATCH v4 1/2] c++: Initial support for P0847R7 (Deducing this) [PR102609]

I guess I'll be attaching all new e-mails here. I found a new, kinda scary issue. ``` bool start_preparsed_function (tree decl1, tree attrs, int flags) { tree ctype = NULL_TREE; bool doing_friend = false; /* Sanity check. */ gcc_assert (VOID_TYPE_P (TREE_VALUE (void_list_node)));

[PATCH] test: Recover sdiv_pow2 check and remove test of RISC-V

gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-sdiv-pow2-1.c: Recover scan check. * lib/target-supports.exp: Remove riscv. --- gcc/testsuite/gcc.dg/vect/vect-sdiv-pow2-1.c | 2 +- gcc/testsuite/lib/target-supports.exp| 4 +--- 2 files changed, 2 insertions(+), 4

Re: [PATCH] Do not prepend target triple to -fuse-ld=lld,mold.

On Tue, 7 Nov 2023, Tatsuyuki Ishi wrote: > > On Oct 16, 2023, at 18:16, Richard Biener wrote: > > > > On Mon, 16 Oct 2023, Tatsuyuki Ishi wrote: > > > >> > >> > >>> On Oct 16, 2023, at 17:55, Richard Biener wrote: > >>> > >>> On Mon, 16 Oct 2023, Tatsuyuki Ishi wrote: > >>> > >

Re: Re: [PATCH] test: Fix FAIL of vect-sdiv-pow2-1.c for RVV test: Fix FAIL of vect-sdiv-pow2-1.c for RVV#

On Tue, 7 Nov 2023, ??? wrote: > Hi, Richi. > > We don't have explicit SDIV_POW2 pattern but we still want to test it to make > sure > we can vectorize SDIV_POW2 pattern which will be recognized. > > Maybe we should add another target check ? No, you should simply _not_ add riscv*-*-* to

Re: [V2 PATCH] Handle bitop with INTEGER_CST in analyze_and_compute_bitop_with_inv_effect.

On Tue, Nov 7, 2023 at 2:03 PM Hongtao Liu wrote: > > On Tue, Nov 7, 2023 at 4:10 PM Richard Biener > wrote: > > > > On Tue, Nov 7, 2023 at 7:08 AM liuhongt wrote: > > > > > > analyze_and_compute_bitop_with_inv_effect assumes the first operand is > > > loop invariant which is not the case when

Re: [PATCH v1] ISC-V: Support FP floor to i/l/ll diff size autovec

LGTM juzhe.zh...@rivai.ai From: pan2.li Date: 2023-11-07 22:30 To: gcc-patches CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] ISC-V: Support FP floor to i/l/ll diff size autovec From: Pan Li This patch would like to support the FP below API auto vectorization with

Re: [PATCH] binutils: experimental use of libdiagnostics in gas

On Tue, 2023-11-07 at 11:03 +0100, Jan Beulich wrote: > On 06.11.2023 23:29, David Malcolm wrote: > > Here's a patch for gas in binutils that makes it use libdiagnostics > > (with some nasty hardcoded paths to specific places on my hard > > drive > > to make it easier to develop the API). > > > >

[PATCH v1] ISC-V: Support FP floor to i/l/ll diff size autovec

From: Pan Li This patch would like to support the FP below API auto vectorization with different type size +--+---+--+ | API | RV64 | RV32 | +--+---+--+ | ifloor | DF => SI | DF => SI | | ifloorf | - | -| | lfloor

Re: [PATCH] Do not prepend target triple to -fuse-ld=lld,mold.

> On Oct 16, 2023, at 18:16, Richard Biener wrote: > > On Mon, 16 Oct 2023, Tatsuyuki Ishi wrote: > >> >> >>> On Oct 16, 2023, at 17:55, Richard Biener wrote: >>> >>> On Mon, 16 Oct 2023, Tatsuyuki Ishi wrote: >>> > On Oct 16, 2023, at 17:39, Richard Biener wrote: >

RE: [PATCH 3/21]middle-end: Implement code motion and dependency analysis for early breaks

On Tue, 7 Nov 2023, Tamar Christina wrote: > > -Original Message- > > From: Richard Biener > > Sent: Tuesday, November 7, 2023 10:53 AM > > To: Tamar Christina > > Cc: gcc-patches@gcc.gnu.org; nd ; j...@ventanamicro.com > > Subject: Re: [PATCH 3/21]middle-end: Implement code motion and

Re: [PATCH] vect/ifcvt: Add vec_cond fallback and check for vector versioning.

> isn't is_cond_op implied by mask != NULL? That said, if we ever end > up here with a non-cond op but a loop mask we effectively want the > same behvior so I think eliding is_cond_op and instead checking > mask != NULL_TREE below is more future proof. > > OK with that change. Thanks, attached

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