Re: [RS6000] Correct PIC_OFFSET_TABLE_REGNUM

On Wed, May 4, 2016 at 1:30 AM, Alan Modra wrote: > Leaving this as r30 results in pic_offset_table_rtx of (reg 30) > for -m64, which is completely bogus. Various rtl analysis predicate > functions treat pic_offset_table_rtx specially.. > > Bootsrapped etc. OK to apply? > >

Re: Enabling -frename-registers?

On Tue, May 3, 2016 at 6:52 PM, Bernd Schmidt <bschm...@redhat.com> wrote: > On 05/03/2016 11:26 PM, David Edelsohn wrote: >> >> Optimizations enabled by default at -O2 should show an overall net >> benefit -- that is the general justification that we have used

Re: Enabling -frename-registers?

On Fri, Apr 29, 2016 at 10:21 AM, Richard Biener <richard.guent...@gmail.com> wrote: > On April 29, 2016 3:48:37 PM GMT+02:00, David Edelsohn <dje@gmail.com> > wrote: >>On Fri, Apr 29, 2016 at 9:44 AM, Bernd Schmidt <bschm...@redhat.com> >>wrote: >&

[wwwdocs] 2015 ACM Software System Award announcement

*** index.html 27 Apr 2016 13:06:08 - 1.1005 --- index.html 29 Apr 2016 17:44:45 - *** mission statement. *** 47,52 --- 47,56 News + http://www.acm.org/awards/2015-technical-awards;>2015 ACM Software System Award + [2016-04-29] + + GCC 6.1

Re: Enabling -frename-registers?

On Fri, Apr 29, 2016 at 9:44 AM, Bernd Schmidt <bschm...@redhat.com> wrote: > > > On 04/29/2016 03:42 PM, David Edelsohn wrote: >> >> On Fri, Apr 29, 2016 at 9:32 AM, Bernd Schmidt <bschm...@redhat.com> >> wrote: >>> >>> On 04/29/20

Re: Enabling -frename-registers?

On Fri, Apr 29, 2016 at 9:32 AM, Bernd Schmidt <bschm...@redhat.com> wrote: > On 04/29/2016 03:02 PM, David Edelsohn wrote: >> >> How has this show general benefit for all architectures to deserve >> enabling it by default at -O2? > > > It should impr

Re: Enabling -frename-registers?

How has this show general benefit for all architectures to deserve enabling it by default at -O2? As an aside, this change seems to be the source of a new code generation bug affecting the PPC kernel. Thanks, David

[PATCH] Fix PR target/69810 (GCC 7)

This PR was fixed earlier with a patch that was deemed safe for GCC 6 through the removal of splitters for zero extend and sign extend to HImode. Now that trunk has opened for GCC 7 development, the following patch restores the splitters and fixes the bug in the more aggressive manner originally

Re: [PATCH 2/2] (header usage fix) include c++ headers in system.h

On Fri, Apr 22, 2016 at 6:02 AM, Szabolcs Nagy wrote: > Some gcc source files include standard headers after > "system.h" but those headers may declare and use poisoned > symbols, they also cannot be included before "system.h" > because they might depend on macro

Re: [PATCH] Fix PR target/70669 (allow __float128 to use direct move)

On Thu, Apr 14, 2016 at 6:43 PM, Michael Meissner wrote: > When adding the basic __float128 support, I forgot to enable direct move > support for moving __float128 between VSX registers and GPR registers. > > This patch enables using direct move for __float128

Re: [PATCH, rs6000] Add support for int versions of vec_adde

On Wed, Apr 13, 2016 at 10:47 AM, Bill Seurer wrote: > Here is an updated patch: > > > This patch adds support for the signed and unsigned int versions of the > vec_adde altivec builtins from the Power Architecture 64-Bit ELF V2 ABI > OpenPOWER ABI for Linux Supplement

Re: [PATCH], PR target/70640, Fix thinkos in PowerPC IEEE 128-bit floating point emulation

On Tue, Apr 12, 2016 at 3:11 PM, Michael Meissner wrote: > After I moved the patches for the 70381 to my internal branch for GCC 7.0 > submissions, I noticed test float128-1.c was failing. I tracked it down to the > fact that the pre-gcc7 branch defaults to using LRA

Re: [PATCH], Re-fix PR 70381 (disable -mfloat128 by default) and add workaround for PR 70589

On Thu, Apr 7, 2016 at 7:44 PM, Michael Meissner wrote: > After applying the fix for PR 70381 to not enable -mfloat128 by default, I > discovered the IEEE 128-bit floating point emulation routines in libgcc are no > longer being built. > > The reason for this is the

Re: [PATCH] PR70117, ppc long double isinf

On Thu, Apr 7, 2016 at 10:17 AM, Alan Modra wrote: > On Thu, Apr 07, 2016 at 11:32:58AM +0200, Richard Biener wrote: >> That's good to know. I think the patch is OK but please seek approval from >> a ppc maintainer as well > > There's only one of those. David? Thread starts

Re: [PATCH, rs6000] Add support for int versions of vec_adde

On Tue, Apr 5, 2016 at 3:36 PM, Bill Seurer wrote: > This patch adds support for the signed and unsigned int versions of the > vec_adde altivec builtins from the Power Architecture 64-Bit ELF V2 ABI > OpenPOWER ABI for Linux Supplement (16 July 2015 Version 1.1). There

Re: [PATCH] Disable guality tests for powerpc*-linux*

On Mon, Mar 28, 2016 at 8:38 PM, Bill Schmidt wrote: > Hi, > > For a long time we've had hundreds of failing guality tests. These > failures don't seem to have any correlation with gdb functionality for > POWER, which is working fine. At this point the value of

Re: [RS6000, PATCH] PR70052, ICE compiling _Decimal128 test case

On Tue, Mar 29, 2016 at 6:14 AM, Alan Modra wrote: > On Fri, Mar 25, 2016 at 07:36:34PM +1030, Alan Modra wrote: >> +2016-03-25 Alan Modra >> + >> + PR target/70052 >> + * config/rs6000/constraints.md (j): Simplify. >> + *

Re: [RS6000, PATCH] PR70052, ICE compiling _Decimal128 test case

On Thu, Mar 24, 2016 at 7:01 AM, Alan Modra wrote: > This fixes the PR70052 ICE by modifying easy_fp_constant to correctly > return false for decimal floating point zero. 0.0D is not an all-zero > bit pattern, at least, not the canonical form. > > I've also taken on Mike's

Re: rs6000 stack_tie mishap again

First, SPE has not been maintained and little participation from Freescale. I would rather deprecate all SPE support. SPE ABI is broken by design. I find the approach very heavy-handed. If you want to enable the target hook for SPE *only*, that's fine with me. The description and references

Re: [PATCH] PR libgcc/70363, fix __float128 problem with non ISA-3.0 assembler

On Tue, Mar 22, 2016 at 4:33 PM, Michael Meissner wrote: > This patch fixes PR libgcc/70363, which is a configuration issue if you build > GCC 6.x with an assembler that does not support the ISA 3.0 instructions. I > missed one emulation function that needed to be a

Re: [PATCH 4/4] [RS6000] Allow saving of fixed regs.

On Mon, Mar 21, 2016 at 9:08 AM, Alan Modra wrote: > As I noted a long time ago in the comment on fixed_reg_p, the real > problem with saving fixed/global regs is that exception frame > unwinding might restore them. So don't emit eh_frame info for any > such reg, and the

Re: [PATCH 3/4] [RS6000] Split SAVRES_STRATEGY

On Mon, Mar 21, 2016 at 9:07 AM, Alan Modra wrote: > No functional change here. A single bit becomes two bits, which > always have the same value at the moment. In preparation for the > next patch. > > * config/rs6000/rs6000.c (SAVRES_MULTIPLE): Replace with.. >

Re: [PATCH 2/4] [RS6000] PR69645, -ffixed-reg ignored

On Mon, Mar 21, 2016 at 9:06 AM, Alan Modra wrote: > Treat -ffixed-reg as we do for global asm regs. The only slightly > complicated part of this patch is that the rs6000 backend itself sets > fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] in some cases, which means > we can't

Re: [PATCH 1/4] [RS6000] Simplify setting of fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]

On Mon, Mar 21, 2016 at 9:06 AM, Alan Modra wrote: > This makes the conditions look the same as other places that deal with > RS6000_PIC_OFFSET_TABLE_REGNUM, eg. first_reg_to_save. No functional > changes. > > * config/rs6000/rs6000.c

Re: [PATCH] Fix rs6000 vector builtin macro handling if it is followed by a fn-like macro without arguments (PR target/70296)

On Fri, Mar 18, 2016 at 5:34 PM, Jakub Jelinek wrote: > Hi! > > The following testcase is diagnosed as errorneous, because the preprocessor > mishandles > > #define c(x) x > vector c; > > and > > #define int(x) x > vector int n; > > The thing is if a function-like macro is not

Re: [PATCH, rs6000] Add support for xxpermr and vpermr instructions

On Thu, Mar 17, 2016 at 2:58 PM, Kelvin Nilsen wrote: > > This patch adds support for two new Power9 instructions, xxpermr and vpermr, > providing more efficient vector permutation operations on > little-endian configurations. These new instructions are described in >

Re: [PATCH, testsuite] Fix ifcvt-4.c for PowerPC

On Mon, Mar 14, 2016 at 4:23 PM, Pat Haugen wrote: > As stated in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68232, this test > needs -misel on powerpc to pass. Verified the following fixes the test on > both powerpc64/powerpc64le. Ok for trunk? > > -Pat > >

Re: [PATCH, testsuite] Fix ifcvt-4.c for PowerPC

On Mon, Mar 14, 2016 at 7:35 PM, Jeff Law wrote: > On 03/14/2016 02:23 PM, Pat Haugen wrote: >> >> As stated in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68232, this >> test needs -misel on powerpc to pass. Verified the following fixes the >> test on both

Re: [PATCH] rs6000: Handle "d" output in the bd*z patterns (PR70098)

On Sun, Mar 13, 2016 at 2:52 PM, Segher Boessenkool <seg...@kernel.crashing.org> wrote: > On Sat, Mar 12, 2016 at 09:59:12AM -0500, David Edelsohn wrote: >> > 2016-03-12 Segher Boessenkool <seg...@kernel.crashing.org> >> > >> > PR target/70

Re: [PATCH] rs6000: Handle "d" output in the bd*z patterns (PR70098)

On Sat, Mar 12, 2016 at 8:55 AM, Segher Boessenkool wrote: > In the rs6000 port, FLOAT_REGS can contain DImode values when compiling > for 64-bit targets. Some instructions (like "fcfid" in the testcase, > convert from integer to DP float) only work on floating point

Re: [PATCH], Fix PR 70131, disable (double)(int) optimization for power8

On Fri, Mar 11, 2016 at 5:41 PM, Michael Meissner wrote: > As I was auditing rs6000.md for power9 changes, I noticed that changes I had > made in 2010 for power7 weren't as effective with power8. > > The FCTIWZ/FCTIWUZ instructions convert the scalar floating point

Re: [PATCH, rs6000] Fix PR target/70168

On Thu, Mar 10, 2016 at 6:10 PM, Ulrich Weigand wrote: > Hello, > > this patch fixes PR target/70168, a wrong code generation problem > caused by rs6000_expand_atomic_compare_and_swap not properly handling > the case where changing retval clobbers newval due to a register

Re: [PATCH, rs6000] Add support for xxpermr and vpermr instructions

On Tue, Mar 8, 2016 at 11:24 AM, Kelvin Nilsen wrote: > > This patch adds support for two new Power9 instructions, xxpermr and vpermr, > providing more efficient vector permutation operations on little-endian > configurations. These new instructions are described in

Re: libgcc: On AIX, increase chances to find landing pads for exceptions

On Tue, Mar 1, 2016 at 7:09 AM, Michael Haubenwallner wrote: > Hi David, > > On 02/10/2016 10:52 AM, Michael Haubenwallner wrote: > >>> There are two remaining issues: >>> >>> 1) FDEs with overlapping ranges causing problems with exceptions. I'm >>> not

Re: [PATCH] Fix PR70011 (backlevel test case)

On Mon, Feb 29, 2016 at 11:49 AM, Bill Schmidt wrote: > Hi, > > PR70011 identifies an old vectorization test that recently started > failing on GCC 6 with POWER8 hardware. This "failure" is that we now > find vectorization of the test case to be profitable, where it

Re: [PATCH] Fix "no-vsx" target attribute handling (PR target/69969)

On Fri, Feb 26, 2016 at 2:27 PM, Jakub Jelinek wrote: > Hi! > > Most of the errors and warnings in rs6000_option_override_internal > are emitted only if the particular option is explicit, e.g. > if (TARGET_P9_DFORM && !TARGET_P9_VECTOR) > { > if

Re: [PATCH] powerpc: Handle DImode rotatert implemented with rlwinm (PR69946)

On Fri, Feb 26, 2016 at 1:52 PM, Segher Boessenkool <seg...@kernel.crashing.org> wrote: > On Thu, Feb 25, 2016 at 10:52:29AM -0500, David Edelsohn wrote: >> Please add a short comment explaining why rs6000_insn_for_shift_mask >> doesn't need to match the logic in rs600

Re: [PATCH] Fix powerpc shift/rotate/mask insn handling (PR target/69946)

On Fri, Feb 26, 2016 at 11:02 AM, Jakub Jelinek wrote: > Hi! > > Segher has added last year a few routines for the shift/rotate + mask > patterns, insns always have one predicate which tests if PowerPC supports > such pattern, and another that emits the instruction for it. > >

Re: [PATCH, rs6000] Fix PR61397 (test case update for P8 vector loads/stores)

On Fri, Feb 26, 2016 at 9:18 AM, Bill Schmidt wrote: > Hi, > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61397 was almost resolved a > year ago, but had a proposed patch by Mike Meissner that was never > vetted and committed. I've reviewed the patch and tested it

Re: [PATCH, rs6000] Fixing PR 67145

On Fri, Feb 26, 2016 at 12:08 AM, Richard Henderson wrote: > It's the simplify-rtx.c portion of the patch that fixes the i686 regression. > > In the PR, Alan raises some good points, but I don't believe that we can > address those for gcc6. A new rtl reassoc optimization that

Re: [PATCH] powerpc: Handle DImode rotatert implemented with rlwinm (PR69946)

On Wed, Feb 24, 2016 at 5:57 PM, Segher Boessenkool wrote: > Some DImode rotate-right-and-mask can be implemented best with a rlwinm > instruction: those that could be a lshiftrt instead of a rotatert, while > the mask is not right-aligned. Why the rotate in the

[PATCH] Fix PR target/69810

Anton reported a latent bug in the rs6000 port discovered with csmith. Splitters for extendqihi2 and zero_extendqihi2 can generate invalid compare RTL. PowerPC can load and store bytes or halfwords, but computations operate on registers. Currently the extend patterns exist for HImode, although

Re: PPC libgcc IEEE128 soft-fp exception/rounding fixes

libgcc * config/rs6000/sfp-machine.h: (_FP_DECL_EX): Declare _fpsr as a union of u64 and double. (FP_TRAPPING_EXCEPTIONS): Return a bitmask of trapping exceptions. (FP_INIT_ROUNDMODE): Read the fpscr instead of writing a mystery value. (FP_ROUNDMODE): Update the usage of _fpscr. Okay. Thanks,

Re: [PATCH, rs6000] PR 66337: Improve Compliance with Power ABI

> Ulrich Weigand wrote: >> Kevin Nilsen wrote: > >> This patch has bootstrapped and tested on powerpc64le-unknown-linux-gnu and= >> powerpc64be-unknown-linux-gnu (both 32-bit and 64-bit) and=20 >> powerpc64-unknown-freebsd11.0 (big endian) with no regressions. Is it ok to >> fix this on

Re: [PATCH], PR 68404 patch #4 (fix earlyclobber problem on power8 fusion)

On Thu, Feb 18, 2016 at 11:45 AM, Michael Meissner wrote: > This patch to rs6000.md (which is essentially the same as #3) fixes the > problem > by removing the early clobber. The patches to predicates.md, and the fusion > tests revert my changes on February 9th that

Re: [PATCH, rs6000] Fix pasto resulting in wrong instruction from builtins for lvxl

On Tue, Feb 16, 2016 at 4:44 PM, Bill Schmidt <wschm...@linux.vnet.ibm.com> wrote: > On Tue, 2016-02-16 at 11:40 -0800, David Edelsohn wrote: >> This is okay, but how about starting with a testcase for this? > > Fair enough. Here's the revised patch with a test, which I've ve

Re: [RS6000] reload_vsx_from_gprsf splitter

On Mon, Feb 15, 2016 at 4:24 PM, Alan Modra <amo...@gmail.com> wrote: > On Mon, Feb 15, 2016 at 06:42:35AM -0800, David Edelsohn wrote: >> Is there still an issue with the constraints used for movdi_internal64? > > Yes and no. No because we shouldn't be attempting DI mov

Re: [RS6000] reload_vsx_from_gprsf splitter

On Mon, Feb 15, 2016 at 4:36 AM, Alan Modra wrote: > On Fri, Feb 12, 2016 at 02:57:22PM +0100, Ulrich Weigand wrote: >> > On Fri, Feb 12, 2016 at 08:54:19AM +1030, Alan Modra wrote: >> > > Another concern I had about this, besides using %L in asm output (what >> > > forces

Re: [PATCH], PR 68404 patch #2 (disable power8/power9 fusion on PowerPC)

On Wed, Feb 10, 2016 at 2:46 PM, Jakub Jelinek wrote: > On Wed, Feb 10, 2016 at 05:42:17PM -0500, Michael Meissner wrote: >> This patch disables -mcpu=power8/-mtune=power8 from setting -mpower8-fusion >> and >> -mcpu=power9/-mtune=power9 from setting -mpower9-fusion. I will

Re: [PATCH], PR 68404 patch #3 (fix earlyclobber problem on power8 fusion)

On Thu, Feb 11, 2016 at 1:43 PM, Michael Meissner wrote: > After looking at Bernd Schmidt and Jakub Jelinek's suggestions, I came to > conclusion that earlyclobber was not needed in this case, and I removed it. I > bootstrapped the compiler using profiledbootstrap

Re: [RS6000] reload_vsx_from_gprsf splitter

On Thu, Feb 11, 2016 at 10:38 AM, Ulrich Weigand <uweig...@de.ibm.com> wrote: > David Edelsohn wrote: >> On Thu, Feb 11, 2016 at 6:04 AM, Alan Modra <amo...@gmail.com> wrote: >> > This is PR68973 part 2, the failure of a boost test, caused by a >>

Re: [RS6000] reload_vsx_from_gprsf splitter

On Thu, Feb 11, 2016 at 6:04 AM, Alan Modra wrote: > This is PR68973 part 2, the failure of a boost test, caused by a > splitter emitting an invalid move in reload_vsx_from_gprsf: > emit_move_insn (op0_di, op2); > > op0 can be any vsx reg, but the mtvsrd destination constraint

Re: libgcc: On AIX, increase chances to find landing pads for exceptions

On Wed, Feb 10, 2016 at 1:52 AM, Michael Haubenwallner <michael.haubenwall...@ssi-schaefer.com> wrote: > > On 02/08/2016 02:59 PM, David Edelsohn wrote: >> Runtime linking is disabled by default on AIX, and I disabled it for >> libstdc++. > > For large applications m

Re: [PATCH], PR target/68404, Fix PowerPC fusion error

On Tue, Feb 9, 2016 at 9:49 AM, Michael Meissner wrote: > This bug fixes PR 68404, which created an insn for the fusion operation when > accessing an array with a large constant offset that the downstream passes > (regrenam in particular don't like). Because fusion

Re: libgcc: On AIX, increase chances to find landing pads for exceptions

Runtime linking is disabled by default on AIX, and I disabled it for libstdc++. There are two remaining issues: 1) FDEs with overlapping ranges causing problems with exceptions. I'm not sure of the best way to work around this. Your patch is one possible solution. 2) AIX linker garbage

Re: [PATCH] PR rtl-optimization/64081: Enable RTL loop unrolling for duplicated exit blocks and back edges.

On Fri, Feb 5, 2016 at 3:27 PM, Jeff Law wrote: > On 02/05/2016 06:43 AM, Alexander Fomin wrote: >> >> Hi! >> >> Some kind of this patch was submitted about a year ago by Igor >> Zamyatin. It's an attempt to fix PR rtl-optimization/64081 by enabling >> RTL loop unrolling for

Re: [PATCH, rs6000] Fix type attribute for a few insns

On Thu, Feb 4, 2016 at 9:33 PM, Pat Haugen wrote: > The following patch fixes a few insns that were specifying an incorrect > 'type' attribute. > > Bootstrap/regtest on powerpc64-linux with no new regressions. Ok for trunk? > > -Pat > > > 2016-02-04 Pat Haugen

Re: [PATCH] Fix -mcpu=power8 atomic expansion (PR target/69644)

On Thu, Feb 4, 2016 at 6:33 AM, Alan Modra <amo...@gmail.com> wrote: > On Wed, Feb 03, 2016 at 05:34:17PM -0500, David Edelsohn wrote: >> On Wed, Feb 3, 2016 at 5:28 PM, Jakub Jelinek <ja...@redhat.com> wrote: >> > Hi! >> > >> > rs6000_exp

Re: [PATCH], PR 69667, Fix PowerPC long double failure with -mlra

On Thu, Feb 4, 2016 at 3:39 PM, Michael Meissner wrote: > This patch fixes a bug where LRA would abort when compiling a C++ program with > -mlra. I tracked this down to using the "ws" constraint for TFmode, TDmode, > and IFmode, but those types are limited to just

Re: [PATCH] bootstrap/69611

this patch fixes bootstrap on FreeBSD PowerPC and hopefully all other PowerPC targets which do not have float128 support. The patch itself is a bandaid to survive stage4. We have to come up with a better solution for FreeBSD and all other soft float targets which do not support float128. The

Re: [PATCH] Fix -mcpu=power8 atomic expansion (PR target/69644)

On Wed, Feb 3, 2016 at 5:28 PM, Jakub Jelinek wrote: > Hi! > > rs6000_expand_atomic_compare_and_swap uses oldval directly in > a comparison instruction, but oldval might be a CONST_INT not suitable > for the instruction (such as in the testcase below in SImode comparison >

Re: [PATCH], PR 69461, PowerPC specific fix for toc-fusion

On Wed, Feb 3, 2016 at 6:34 PM, Michael Meissner wrote: > In PR 69461, Vlad mentioned that in rs6000_legitimate_address_p, I was trying > to validate an address for TOC fusion, but I was using a predicate that looked > for a MEM instead of an address. > > I

Re: [RS6000] ABI_V4 init of toc section

On Fri, Jan 29, 2016 at 11:38 AM, Alan Modra wrote: > Since 4c4a180d, LTO has turned off flag_pic when linking a fixed > position executable. This results in flag_pic being zero in > rs6000_file_start, and no definition of ".LCTOC1". > > However, when we get to actually

Re: [RS6000] lqarx and stqcx. registers

On Sun, Jan 31, 2016 at 5:28 PM, Alan Modra wrote: > lqarx RT and stqcx. RS are valid only with even numbered gprs. The > predicate to enforce this happens to allow a loophole, closed by this > patch. > > This pattern created by combine: > Trying 8 -> 9: > Successfully matched

Re: [PATCH, rs6000] Fix PR65546

On Thu, Jan 28, 2016 at 5:41 PM, Bill Schmidt wrote: > Hi, > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65546 identifies a failure > in gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c. The test case hasn't > kept up with changes in the vectorizer, so it's looking

Re: [RS6000] ABI_V4 init of toc section

On Fri, Jan 29, 2016 at 11:38 AM, Alan Modra wrote: > Since 4c4a180d, LTO has turned off flag_pic when linking a fixed > position executable. This results in flag_pic being zero in > rs6000_file_start, and no definition of ".LCTOC1". > > However, when we get to actually

Re: [PATCH, rs6000] Disable static branch prediction in absence of real profile data

On Wed, Jan 27, 2016 at 6:10 PM, Pat Haugen wrote: > The following patch prevents static prediction if we don't have real profile > data. Testing on SPEC CPU2006 showed a couple improvements in specint and > specfp neutral. Bootstrap/regtest on powerpc64 with no new

Re: [PATCH] add test for target/17381 - Unnecessary register move for float extend

On Wed, Jan 27, 2016 at 5:38 PM, Martin Sebor wrote: > The attached patch adds a test for the apparently long fixed > bug. > > FWIW, I've been trying to close out some of these old bugs and > while it doesn't seem to be done consistently, it occurs to me > that it might be nice

Re: [PATCH 1/4] Make SRA scalarize constant-pool loads

On Wed, Jan 27, 2016 at 6:36 PM, Jeff Law <l...@redhat.com> wrote: > On 01/27/2016 12:39 PM, David Edelsohn wrote: >> >> The new sra-17.c and sra-18.c tests fail on AIX because the regex is >> too restrictive -- AIX labels don't have exactly the same format. On >

Re: [PATCH 1/4] Make SRA scalarize constant-pool loads

The new sra-17.c and sra-18.c tests fail on AIX because the regex is too restrictive -- AIX labels don't have exactly the same format. On AIX, the labels in the dumps look like "LC..0" instead of ".LC0". This patch adds "*" and ".*" so that the "." prepended to LC is optional and to allow

Re: [PATCH, 4.9, rs6000, testsuite] Fix PR69479

On Tue, Jan 26, 2016 at 4:46 PM, Bill Schmidt wrote: > Hi, > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69479 notes that > gcc.dg/and-1.c fails a scan-assembler-not test for nand, but the test > does pass in subsequent releases. The test author indicates in

Re: [PATCH] rs6000: Put back the 's' output modifier

On Mon, Jan 25, 2016 at 9:39 PM, Segher Boessenkool wrote: > It turns out the 's' output modifier is used in some glibc math code, > and is in an installed header even. So let's put it back, it is much > less of a burden supporting it a bit longer than to deal with

Re: [PATCH], PowerPC IEEE 128-bit fp, #12 (default -mfloat128 on PowerPC-Linux)

On Thu, Jan 21, 2016 at 4:25 PM, Michael Meissner wrote: > This is the final patch (at least so far) that turns on -mfloat128 by default > for PowerPC Linux systems where the VSX instruction set is enabled. As I > mentioned in the last email, because we don't build

Re: [PATCH] Partial fix for PR target/68662

On Tue, Jan 26, 2016 at 2:15 PM, Jakub Jelinek wrote: > Hi! > > As Alan mentioned in the PR, there is some other issue still around, but > by the time I've noticed that, I already had this patch being > bootstrapped/regtested on powerpc64{,le}-linux (which just passed). > Ok for

Re: [PATCH, 4.9, rs6000, testsuite] Fix PR69479

On Tue, Jan 26, 2016 at 4:46 PM, Bill Schmidt wrote: > Hi, > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69479 notes that > gcc.dg/and-1.c fails a scan-assembler-not test for nand, but the test > does pass in subsequent releases. The test author indicates in

Re: [PATCH, rs6000] Fix PR63354

On Sun, Jan 24, 2016 at 9:17 PM, Bill Schmidt wrote: > Hi Jan, thanks for the report! Patch below that should fix the problem. > Bootstrapped and tested on powerpc64le-unknown-linux-gnu, no > regressions. David, is this ok for trunk? > > Thanks, > Bill > > >

Re: [PATCH] Fix a typo in ppc libgcc (PR target/69444)

On Mon, Jan 25, 2016 at 3:34 PM, Jakub Jelinek wrote: > Hi! > > The soft-fp multilib of powerpc libgcc doesn't build because of a typo > in the conditional - the guarded code uses inline asm that assumes hard > float. > > Ok for trunk? > > 2016-01-25 Jakub Jelinek

Re: [PATCH, rs6000] Fix PR63354

On Fri, Jan 22, 2016 at 12:42 AM, Bill Schmidt wrote: > Hi, > > On Thu, 2016-01-21 at 21:21 -0600, Bill Schmidt wrote: >> The testcase will need a slight adjustment, as currently it fails on >> powerpc64 with -m32 testing. Working on a fix. >> >> Bill >> > > This

Re: [PATCH, rs6000] Add Power9 asm entries

On Wed, Jan 20, 2016 at 4:21 PM, Pat Haugen wrote: > The following adds a couple missed Power9 assembler option entries. > Bootstrapped on ppc64. Ok for trunk? > > -Pat > > 2016-01-20 Pat Haugen > > * config/rs6000/aix71.h

Re: [PATCH], PowerPC IEEE 128-bit fp, #11-rev4 (enable libgcc conversions)

On Wed, Jan 20, 2016 at 8:00 PM, Michael Meissner wrote: > This is revision 4 of the IEEE 128-bit floating point libgcc support. > > Since revision 3, I have removed the gcc changes that broke AIX. I rewrote > the > IBM extended double pack/unpack support to not use

[PATCH] Detangle gcc/configure for Darwin

A gcc/configure stanza to test for PowerPC mfcrf support became tangled with Darwin test for .machine directive. This patch detangles and separates the two tests. I don't have a Darwin system to test. * configure.ac (gcc_cv_as_powerpc_mfcrf, gcc_cv_as_machine_directive): Detangle. Okay?

Re: [PATCH, rs6000] Fix PR63354

On Thu, Jan 21, 2016 at 11:48 AM, Bill Schmidt wrote: > Hi, > > Anton Blanchard proposed a fix to his own bug report in > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63354, but never submitted > the patch upstream. I've added a formal test case and am submitting on

Re: [PATCH] gcc/configure test for AIX DWARF

On Thu, Jan 21, 2016 at 12:47 PM, Bernd Schmidt <bschm...@redhat.com> wrote: > On 01/18/2016 08:30 PM, David Edelsohn wrote: >> >> Bootstrapped on powerpc-ibm-aix7.1.2.0 with and without the corrected >> assembler. >> >> Okay? > > > The change

Re: [PATCH, rs6000] Fix PR67489

On Thu, Jan 21, 2016 at 6:00 PM, Bill Schmidt wrote: > Hi, > > The test case gcc.target/powerpc/p8vector-builtin-8.c needs to be > restricted to targets that support the __int128 keyword. This was > wrongly being attempted with { dg-do compile { target int128 } }

[PATCH] PR target/68609 vector swsqrt

This patch finishes PR target/68609 to use reciprocal estimate for vector sqrt. PR target/68609 * config/rs6000/rs6000.c (rs6000_emit_swsqrt): Add vector domain check. * config/rs6000/vector.md (sqrt2): Call rs6000_emit_swsqrt for V4SFmode. Thanks, David Index: rs6000.c

Re: [PATCH, rs6000] Add support for __builtin_cpu_is() and __builtin_cpu_supports()

On Thu, Jan 14, 2016 at 10:50 PM, Peter Bergner wrote: > This patch adds support for __builtin_cpu_init(), __builtin_cpu_is() and > __builtin_cpu_supports() builtins for PowerPC. We use the same API as the > x86* builtins of the same name. These builtins uses the new GLIBC

Re: [PATCH] xfail one ppc testcase (PR tree-optimization/66612)

On Wed, Jan 20, 2016 at 9:28 AM, Jakub Jelinek wrote: > Hi! > > As per discussion in the PR, I'd like to xfail this test for GCC6 and > change it to 7.0 milestone, because it is too late/too risky to change > this for gcc 6 now. > > Bootstrapped/regtested on

[PATCH] gcc/configure test for AIX DWARF

AIX7 has added support for DWARF to XCOFF, but complete and correct support did not occur with a single update and the initial release of AIX7. The initial support defined a subset of common DWARF debug sections. A later update added most of the remaining sections for location lists and frames,

Re: [PATCH v2] libstdc++: Make certain exceptions transaction_safe.

On Sun, Jan 17, 2016 at 3:21 PM, Torvald Riegel <trie...@redhat.com> wrote: > On Sat, 2016-01-16 at 15:38 -0500, David Edelsohn wrote: >> On Sat, Jan 16, 2016 at 8:35 AM, Jakub Jelinek <ja...@redhat.com> wrote: >> > On Sat, Jan 16, 2016 at 07:47:33AM -0500, Davi

Re: [PATCH v2] libstdc++: Make certain exceptions transaction_safe.

stage1 libstdc++ builds just fine. the problem is stage2 configure fails due to missing ITM_xxx symbols when configure tries to compile and run conftest programs. Thanks, David On Sat, Jan 16, 2016 at 7:43 AM, Jonathan Wakely wrote: > What are the errors? > > I can build

Re: [PATCH v2] libstdc++: Make certain exceptions transaction_safe.

This patch broke bootstrap on AIX. Not all targets support TM. This patch makes libstdc++ unconditionally refer to TM symbols. Please fix. - David

Re: [PATCH v2] libstdc++: Make certain exceptions transaction_safe.

On Sat, Jan 16, 2016 at 8:35 AM, Jakub Jelinek <ja...@redhat.com> wrote: > On Sat, Jan 16, 2016 at 07:47:33AM -0500, David Edelsohn wrote: >> stage1 libstdc++ builds just fine. the problem is stage2 configure >> fails due to missing ITM_xxx symbols when configure tries

Re: [PATCH v2] libstdc++: Make certain exceptions transaction_safe.

PM, Torvald Riegel <trie...@redhat.com> wrote: > On Sat, 2016-01-16 at 14:35 +0100, Jakub Jelinek wrote: >> On Sat, Jan 16, 2016 at 07:47:33AM -0500, David Edelsohn wrote: >> > stage1 libstdc++ builds just fine. the problem is stage2 configure >> > fails due to missi

PR68609

My initial implementation of software sqrt based on estimate was fragile for denormal inputs. This revised version converts both sqrt and rsqrt to use Goldschmidt's Algorithm and calculates sqrt through an iterative correction to a sqrt estimate. Because sqrt only is profitable for 1 iteration,

Re: [trans-mem, aa64, arm, ppc, s390] Fixing PR68964

On Tue, Jan 12, 2016 at 11:53 AM, Richard Henderson wrote: > The problem in this PR is that we never got around to flushing out the vector > support for transactions for anything but x86. My goal here is to make this > as > generic as possible, so that it should Just Work with

Re: [PATCH], PowerPC IEEE 128-bit fp, #11-rev3 (enable libgcc conversions)

On Tue, Jan 12, 2016 at 6:47 PM, Joseph Myers wrote: > On Tue, 12 Jan 2016, Michael Meissner wrote: > >> On Tue, Jan 12, 2016 at 12:18:55AM +, Joseph Myers wrote: >> > On Mon, 11 Jan 2016, Michael Meissner wrote: >> > >> > > I fixed the #ifdef to use __NO_FPRS__

Re: [PATCH, rs6000] Use lxvx and stxvx for 128-bit float, etc., with -mcpu=power9

On Wed, Jan 6, 2016 at 1:34 PM, Bill Schmidt wrote: > Hi, > > I previously added POWER9 support for lxvx and stxvx to replace the > load-swap and swap-store patterns for POWER8. However, I missed the > fact that we have different patterns for loads and stores of

Re: [PATCH, rs6000] Handle vector reductions in swap optimization

On Wed, Jan 6, 2016 at 5:37 PM, Bill Schmidt wrote: > Hi, > > Swap optimization is missing some opportunities when vector reductions > are present. This patch adds logic to recognize vector-reduction > patterns and mark them as swappable. Some of these are very easy

Re: adjust fallback_frame_state for 32bits AIX 7.1

On Tue, Jan 5, 2016 at 6:15 AM, Olivier Hainque wrote: > Hello, > > This is a tiny change we have been using successfully for at least a couple > of years now, improving exception propagation through signal handlers on > 32bits > AIX 7.1. > > While this isn't a complete

Re: [PATCH], PowerPC, add ISA 3.0 xxperm (power9 patch #12)

On Thu, Dec 31, 2015 at 1:30 PM, Michael Meissner wrote: > This patch adds support for the ISA 3.0 XXPERM instruction, which is like > VPERM, except it can operate on any VSX register. Since the instruction is a > 3 > operand instruction (RT and RA must be the

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