> >>>>> "Joel" == Joel Brobecker via Gdb-patches
> >>>>> writes:
>
> Joel> ChangeLog:
>
> Joel> * src-release.sh (GDB_SUPPORT_DIRS): Add libsframe.
>
> Joel> Ok to apply to master?
>
> Looks good to
Hello,
This script was recently changed as follow:
| commit e619dddb3a45780ae66d762756882a3b896b617d
| Date: Tue Nov 15 15:07:13 2022 -0800
| Subject: src-release.sh: Add libsframe
|
| Add libsframe to the list of top level directories that will be included
| in a releas
Signed-off-by: Joel Holdsworth
---
gcc/config/avr/avr-devices.cc | 2 --
1 file changed, 2 deletions(-)
diff --git a/gcc/config/avr/avr-devices.cc b/gcc/config/avr/avr-devices.cc
index aa284217f50..ff6a5441b77 100644
--- a/gcc/config/avr/avr-devices.cc
+++ b/gcc/config/avr/avr-devices.cc
> We can go with a private vect_gimple_build function until we sort out the API
> issue to unblock Tamar (I'll reply to Richards reply with further thoughts on
> this)
>
Done.
> > Similarly are you ok with the use of gimple_extract_op? I would lean
> towards using it as it is cleaner, but I don'
; Similarly are you ok with the use of gimple_extract_op? I would lean towards
> using it as it is cleaner, but I don't have strong feelings.
>
> Joel
Ping. Just looking for some confirmation before I rework this patch. It would
be good to get some agreement on this as Tamar is bl
are you ok with the use of gimple_extract_op? I would lean towards
using it as it is cleaner, but I don't have strong feelings.
Joel
> -Original Message-
> From: Richard Sandiford
> Sent: 07 June 2022 09:18
> To: Joel Hutton
> Cc: Richard Biener ; gcc-patches@gcc.gnu.or
> > Patches attached. They already incorporated the .cc rename, now
> > rebased to be after the change to tree.h
>
> @@ -1412,8 +1412,7 @@ vect_recog_widen_op_pattern (vec_info *vinfo,
>2, oprnd, half_type, unprom, vectype);
>
>tree var = vect_recog_temp_ssa_var (itype
> Can you post an updated patch (after the .cc renaming, and code_helper
> now already moved to tree.h).
>
> Thanks,
> Richard.
Patches attached. They already incorporated the .cc rename, now rebased to be
after the change to tree.h
Joel
0001-Refactor-to-allow-internal_fn-s.pa
Ping!
Just checking there is still interest in this. I'm assuming you've been busy
with release.
Joel
> -Original Message-
> From: Joel Hutton
> Sent: 13 April 2022 16:53
> To: Richard Sandiford
> Cc: Richard Biener ; gcc-patches@gcc.gnu.org
> Subje
> >> gcc/testsuite/ChangeLog:
> >>
> >> * gcc.misc-tests/outputs.exp: Make the -gsplit-dwarf test
> >> a compile-and-link test rather than a compile-only test.
>
> OK, thanks.
Thank you Richard. Pushed to master.
--
Joel
Hello,
Gentle ping on this patch.
Thank you!
On Mon, Apr 25, 2022 at 09:04:51AM -0700, Joel Brobecker wrote:
> Hello,
>
> We have noticed that, when running the GCC testsuite on AArch64
> RTEMS 6, we have about 150 tests failing due to a link failure.
> When investigating, we
netbsd Krister Walfridsson
sh-linux-gnu Kaz Kojima
-RTEMS PortsJoel Sherrill
+RTEMS PortsJoel Sherrill
RTEMS PortsRalf Corsepius
RTEMS PortsSebastian Huber
ort for the AVR-DA and AVR-DB
families here:
https://gcc.gnu.org/pipermail/gcc-patches/2022-April/592668.html
No response so far.
Best Regards
Joel Holdsworth
a compile-only test.
OK to push on master?
Thank you,
--
Joel
---
gcc/testsuite/gcc.misc-tests/outputs.exp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.misc-tests/outputs.exp
b/gcc/testsuite/gcc.misc-tests/outputs.exp
index bc1fbe4eb7f..afa
Ping patch.
Link: https://gcc.gnu.org/pipermail/gcc-patches/2022-April/592668.html
Thanks
Joel Holdsworth
Hi all,
These patches refactor the widening patterns in vect-patterns to use
internal_fn instead of tree_codes.
Sorry about the delay, some changes to master made it a bit messier.
Bootstrapped and regression tested on aarch64.
Joel
> > diff --git a/gcc/tree-vect-patterns.c b/gcc/tre
Signed-off-by: Joel Holdsworth
---
gcc/config/avr/avr-devices.cc | 2 --
1 file changed, 2 deletions(-)
diff --git a/gcc/config/avr/avr-devices.cc b/gcc/config/avr/avr-devices.cc
index aa284217f50..ff6a5441b77 100644
--- a/gcc/config/avr/avr-devices.cc
+++ b/gcc/config/avr/avr-devices.cc
leaking into cc1.
Signed-off-by: Joel Holdsworth
---
gcc/config/avr/avr-mcus.def | 22 ++
gcc/config/avr/gen-avr-mmcu-specs.cc | 2 +-
gcc/config/avr/gen-avr-mmcu-texi.cc | 2 +-
gcc/doc/avr-mmcu.texi| 6 +++---
4 files changed, 27 insertions(+), 5
avr-libc here: https://github.com/avrdudes/avr-libc/pull/881
In addition, this patch-set includes a patch to remove non-printable
characters from avr-devices.cc.
Joel Holdsworth (2):
avr: Added AVR-DA and DB MCU series
avr: Removed errant control characters
gcc/config/avr/avr-devices.cc
In recent versions of glibc fopen has __attribute__((malloc)).
Since we can not detect wether this attribute is present or not,
we avoid including stdio.h and instead forward declare what we
need in each test.
Signed-off-by: Joel Teichroeb
---
gcc/testsuite/gcc.dg/analyzer/analyzer-verbosity
On Sat, Dec 18, 2021 at 10:13 AM Joel Sherrill wrote:
>
>
>
> On Fri, Dec 17, 2021, 9:57 PM Jeff Law wrote:
>>
>>
>>
>> On 12/17/2021 9:10 AM, Joel Sherrill wrote:
>> > ---
>> > gcc/config.gcc | 1 +
>> > 1 file changed, 1 inse
On Fri, Dec 17, 2021, 9:57 PM Jeff Law wrote:
>
>
> On 12/17/2021 9:10 AM, Joel Sherrill wrote:
> > ---
> > gcc/config.gcc | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/gcc/config.gcc b/gcc/config.gcc
> > index c8824367b13
On Fri, Dec 17, 2021 at 12:53 PM Eric Gallager wrote:
>
> On Fri, Dec 17, 2021 at 11:11 AM Joel Sherrill wrote:
> >
> > ---
> > gcc/config.gcc | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/gcc/config.gcc b/gcc/config.gcc
> > ind
---
htdocs/gcc-12/changes.html | 4
1 file changed, 4 insertions(+)
diff --git a/htdocs/gcc-12/changes.html b/htdocs/gcc-12/changes.html
index b1c88670..c69b301e 100644
--- a/htdocs/gcc-12/changes.html
+++ b/htdocs/gcc-12/changes.html
@@ -66,6 +66,10 @@ a work-in-progress.
The hppa[12]*
---
gcc/config.gcc | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index c8824367b13..fe93a72a16c 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -252,6 +252,7 @@ case ${target} in
| cr16-*-*\
| hppa[12]*-*-hpux10*
> + if (ot_plus == unknown_optab
> + || ot_minus == unknown_optab
> + || optab_handler (ot_minus, TYPE_MODE (step_vectype)) ==
> CODE_FOR_nothing
> + || optab_handler (ot_plus, TYPE_MODE (step_vectype)) ==
> + CODE_FOR_nothing)
> return false;
>
> Won't optab_handler just retu
(vectorizable_induction): Rework to avoid
directly_supported_p
From: Joel Hutton
Sent: 13 December 2021 15:02
To: Richard Biener ; gcc-patches@gcc.gnu.org;
Tobias Burnus ; Richard Sandiford
Cc: Richard Biener
Subject: Re: GCC 11 backport does not build (no "directly_supported_p&qu
My mistake, reworked patch. Tests are still running.
From: Richard Biener
Sent: 13 December 2021 14:47
To: gcc-patches@gcc.gnu.org ; Tobias Burnus
; Joel Hutton ; Richard Sandiford
Cc: GCC Patches ; Richard Biener
Subject: Re: GCC 11 backport does not build
ok for backport to 11?
From: Richard Sandiford
Sent: 10 December 2021 10:22
To: Joel Hutton
Cc: GCC Patches ; Richard Biener
Subject: Re: pr103523: Check for PLUS/MINUS support
Joel Hutton writes:
> Hi all,
>
> This is to address pr103523.
>
> b
Hi all,
This is to address pr103523.
bootstrapped and regression tested on aarch64.
Check for PLUS_EXPR/MINUS_EXPR support in vectorizable_induction.
PR103523 is an ICE on valid code:
void d(float *a, float b, int c) {
float e;
for (; c; c--, e += b)
a[c] = e;
}
This is due to no
Just a quick ping to check this hasn't been forgotten.
> -Original Message-
> From: Joel Hutton
> Sent: 12 November 2021 11:42
> To: Richard Biener
> Cc: gcc-patches@gcc.gnu.org; Richard Sandiford
>
> Subject: RE: [vect-patterns] Refactor widen_plus/wid
Updated patch 2 with explanation included in commit message and changes
requested.
Bootstrapped and regression tested on aarch64
> -Original Message-
> From: Joel Hutton
> Sent: 12 November 2021 11:42
> To: Richard Biener
> Cc: gcc-patches@gcc.gnu.org; Richard Sandiford
&
IFN_VEC_WIDEN_PLUS_LO -> vec_widen_addl_lo_
-> (u/s)addl
This gives the same functionality as the previous WIDEN_PLUS/WIDEN_MINUS tree
codes which are expanded into VEC_WIDEN_PLUS_LO, VEC_WIDEN_PLUS_HI.
Let me know if I'm not expressing this clearly.
Thanks,
Joel
Hi all,
This refactor allows widening vect patterns (such as widen_plus/widen_minus) to
be represented as
either internal_fns or tree_codes and replaces the current
widen_plus/widen_minus with internal_fn versions. This refactor is split into 3
patches.
Boostrapped and regression tested on aar
On Thu, Sep 30, 2021, 3:37 PM Przemyslaw Wirkus
wrote:
> > Subject: Re: [PATCH][GCC] arm: Add Cortex-R52+ multilib
> >
> > I think the RTEMS multilibs are based on the products that RTEMS
> supports,
> > so this is really the RTEMS maintainers' call.
> >
>
Ping. Is there still interest in refactoring vect-patterns to internal_fn's?
> -Original Message-
> From: Joel Hutton
> Sent: 07 June 2021 14:30
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Biener ; Richard Sandiford
>
> Subject: [vect-patterns][RFC] Refactor
Hi all,
This refactor allows widening patterns (such as widen_plus/widen_minus) to be
represented as
either internal_fns or tree_codes. The widening patterns were originally added
as tree codes with the expectation that they would be refactored later.
[vect-patterns] Refactor as internal_fn's
This ignores a couple of plugins we use that I don't expect GCC to use.
It works great but the host dependencies are sometimes a pain. We've
ended up writing host OS specific advice/howto's to address this. Any
expectations on host pain versus the pretty painless texinfo?
Thanks.
s the epilogue for one vectorized
scalar stmt at a time. This modification makes one
invocation create the epilogue for both related stmts and marks the other as
'done'. Alternate suggestions are welcome.
Joel
[vect] Support min/max + index pattern
Add the capability to vect-loop to suppor
L
On Thu, Apr 1, 2021, 2:08 PM Bernhard Reutner-Fischer
wrote:
> On 1 April 2021 21:01:27 CEST, Bernhard Reutner-Fischer <
> rep.dot@gmail.com> wrote:
> >On 1 April 2021 20:32:34 CEST, Joel Sherrill wrote:
> >>Change the preprocessor logic so RTEMS us
Change the preprocessor logic so RTEMS uses utime().
gcc/ada/
* adaint.c (__gnat_copy_attribs): RTEMS should use utime().
---
gcc/ada/adaint.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/ada/adaint.c b/gcc/ada/adaint.c
index 0a90c92402c..d3b83f61076 100644
-
>> gcc/testsuite/ChangeLog:
>>
>> PR target/99102
>> * gcc.target/aarch64/sve/pr99102.c: New test.
>
>(The filename is out of date, but the git hook would catch that.)
Fixed and committed.
>
>>
>> diff --git a/gcc/testsuite/gcc.dg/vect/pr99102.c
>> b/gcc/testsuite/gcc.dg/vect/pr99102.c
>> new
Hi all,
This patch fixes PR99102. For masked gather loads/scatter stores the
'loop_masks' variable was checked to be non-null, but the 'final_mask' was the
actual mask used.
bootstrapped and regression tested on aarch64. Regression tested on aarch64_sve
under qemu.
[Vect] Fix mask check on Scat
Hi Richard,
I've revised the patch, sorry about sloppy formatting in the previous one.
Full bootstrap/regression tests are still running, but the changes are pretty
trivial.
Ok for trunk assuming tests finish clean?
>Joel Hutton writes:
>> @@ -277,6 +277,81 @@ optab_for_t
&code2, &multi_step_cvt,
>> +&interm_types))
>>{
>> /* Binary widening operation can only be supported directly by the
>> architecture. */
>> @@ -4981,10 +5065,20
Hi Richards,
This patch adds support for the V8QI->V8HI case from widening vect patterns as
discussed to target PR98772.
Bootstrapped and regression tested on aarch64.
[aarch64][vect] Support V8QI->V8HI WIDEN_ patterns
In the case where 8 out of every 16 elements are widened using a
widening
ater.
That's fair enough, fake/don't care elements is a bit of a hack. I'll try
something out with the conversions and regular subtract.
thanks for the help,
Joel
>> So emit a v4qi->v8qi gimple conversion
>> then a regular widen_lo/hi using the existing backend patterns/optabs?
>
>I was thinking of using a v8qi->v8hi convert on each operand followed
>by a normal v8hi subtraction. That's what we'd generate if the target
>didn't define the widening patterns.
>>> In practice this will only affect targets that choose to use mixed
>>> vector sizes, and I think it's reasonable to optimise only for the
>>> case in which such targets support widening conversions. So what
>>> do you think about the idea of emitting separate conversions and
>>> a normal subtr
ed with a V8QI, or how to
represent V16QI where we don't care about the top/bottom 8. I made some attempt
in optabs.c, which is in the patch commented out, but I'm not sure if I'm going
about this the right way.
Joel
diff --git a/gcc/config/aarch64/aarch64-simd.md b/
From: Richard Sandiford
Sent: 21 January 2021 13:40
To: Richard Biener
Cc: Joel Hutton via Gcc-patches ; Joel Hutton
Subject: Re: [AArch64] Remove backend support for widen-sub
Richard Biener writes:
> On Thu, 21 Jan 2021, Richard Sandiford wrote:
>
>> Joe
Hi all,
This patch removes support for the widening subtract operation in the aarch64
backend as it is causing a performance regression.
In the following example:
#include
extern void wdiff( int16_t d[16], uint8_t *restrict pix1, uint8_t *restrict
pix2)
{
for( int y = 0; y < 4; y++ )
{
> > I have no idea who that is (if it is a single user at all,
> > if it isn't any user with git write permissions).
>
> CCing Joel, he should help us how to set a git config
> that will be used by the server hooks.
I am not sure that requiring both the server and
* tree-vect-data-refs.c (vect_get_smallest_scalar_type): Add
WIDEN_PLUS/WIDEN_MINUS case.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/pr97929.c: New test.From 1d7855aab9ea099f244e50baede24c50897f6eb5 Mon Sep 17 00:00:00 2001
From: Joel Hutton
Date: Wed, 9 Dec 2020 16:51:17 +
Subject
EC_WIDEN_PLUS/MINUS_HI/LO<...>' for VEC_WIDEN_PLUS/MINUS_HI/LO
gcc/ChangeLog:
* tree-pretty-print.c (dump_generic_node): Add case for
VEC_WIDEN_(PLUS/MINUS)_(HI/LO)_EXPR and WIDEN_(PLUS/MINUS)_EXPR.
From 6ec022ddc86e97fd7779bdf075619d2e273c77d0 Mon Sep 17 00:00:00
rks, but IIRC it shows up as a tab
> character in the testsuite result summary too.
Fixed. Minor nits welcome. :)
> OK for the aarch64 bits with the testsuite changes above.
ok?
gcc/ChangeLog:
2020-11-13 Joel Hutton
* config/aarch64/aarch64-simd.md: Add vec_widen_lshift_hi/l
naming
> consistent with other tree codes: WIDEN_PLUS_EXPR instead of
> WIDEN_ADD_EXPR and WIDEN_MINUS_EXPR instead of WIDEN_SUB_EXPR.
> Same idea for the VEC_* codes.
Fixed.
> > gcc/ChangeLog:
> >
> > 2020-11-12 Joel Hutton
> >
> > * expr.c (expand
reme would
> be to have one define_expand and various iterators and attributes.
>
> I think the vec_widen_mult_*_ patterns strike a good balance:
> the use ANY_EXTEND to hide the sign difference while still having
> separate hi and lo patterns:
Done
gcc/ChangeLog:
2020-11-13 Joel H
Hi all,
This patch adds backend patterns for vec_widen_add, vec_widen_sub on aarch64.
All 3 patches together bootstrapped and regression tested on aarch64.
Ok for stage 1?
gcc/ChangeLog:
2020-11-12 Joel Hutton
* config/aarch64/aarch64-simd.md: New patterns
vec_widen_saddl_lo/hi_
Hi all,
This patch adds support in the aarch64 backend for the vec_widen_shift
vect-pattern and makes a minor mid-end fix to support it.
All 3 patches together bootstrapped and regression tested on aarch64.
Ok for stage 1?
gcc/ChangeLog:
2020-11-12 Joel Hutton
* config/aarch64
Hi all,
This patch adds widening add and widening subtract patterns to
tree-vect-patterns.
All 3 patches together bootstrapped and regression tested on aarch64.
gcc/ChangeLog:
2020-11-12 Joel Hutton
* expr.c (expand_expr_real_2): add widen_add,widen_subtract cases
* optabs
-09-29 Joel Hutton
PR target/96837
* tree-vect-slp.c (vect_analyze_slp): Do not call
vect_attempt_slp_rearrange_stmts for vector constructors.
gcc/testsuite/ChangeLog:
2020-09-29 Joel Hutton
PR target/96837
* gcc.dg/vect/bb-slp-49.c: New test.From
From: Joel Sherrill
* config/i386/t-rtems: Change from mtune to march when building
multilibs. The mtune argument tunes or optimizes for a specific
CPU model but does not ensure the generated code is appropriate
for the CPU model. Prior to this patch, i386
I approve of this patch. I'm responsible for GCC for TX2 at Marvell. Andrew
Pinski should certainly chime in if he wants.
Joel
On 7/6/20, 10:48 AM, "Gcc-patches on behalf of Richard Sandiford"
wrote:
aven't
gotten around to setting that up, but if this is causing any confusion
here, I'll make sure to include the ChangeLog diff in the patch as well.
Thanks again!
--
Joel
llowed onto branch master.
>
>
> On Fri, Apr 17, 2020 at 04:49:47PM -0700, Joel Brobecker wrote:
> > From: Douglas Rupp
> >
> > Hello,
> >
> > (submitting this on behalf of Doug Rupp, one of my colleagues)
> >
> > We're getting an er
Hello,
Just a friendly ping on the following patch, hopefully sufficiently
straightforward and tested to be allowed onto branch master.
Thank you!
On Fri, Apr 17, 2020 at 04:49:47PM -0700, Joel Brobecker wrote:
> From: Douglas Rupp
>
> Hello,
>
> (submitting this on behalf of
Yes, Bellsoft's contribution is to be covered under the Marvell copyright
assignment, as this is a work for hire.
Joel
>Yes, Bellsoft's contribution is to be covered under the Marvell copyright
>assignment, as this is a work for hire.
>
>Joel
>
>>>Hi Ant
place, as we've had employees in the past six months submit changes, for
example Steve Ellcey.
Joel Jones
>Hi Anton,
>
>> -Original Message-
>> From: Gcc-patches On Behalf Of Anton
>> Youdkevitch
>> Sent: 20 April 2020 19:29
>> To: gcc-patches@gcc.gnu.org
usual in that case.
gcc/testsuite/
* gcc.target/powerpc/pr71763.c: Require powerpc_vsx_ok.
OK for master?
Thanks!
--
Joel
---
gcc/testsuite/gcc.target/powerpc/pr71763.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr71763.c
b/gcc/testsuite/gcc.target/
> > gcc/testsuite/
> >
> > * gcc.target/arm/div64-unwinding.c: Skip on vxworks_kernel targets.
> OK.
Thank you, Richard. Pushed to master.
--
Joel
verify that this still runs on
non-VxWorks targets.
OK to push to master?
Thank you!
--
Joel
---
gcc/testsuite/gcc.target/arm/div64-unwinding.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.target/arm/div64-unwinding.c
b/gcc/testsuite/gcc.target/arm/div64-unwinding.c
index
Add myself to MAINTAINERS file.
2020-02-28 Joel Hutton
* MAINTAINERS (Write After Approval) : Add myself.
>From c0671c0d82c6858a90ab4abc62cdb302646f2d51 Mon Sep 17 00:00:00 2001
From: Joel Hutton
Date: Fri, 28 Feb 2020 11:06:05 +
Subject: [PATCH] Add myself to MAINTAINERS
2
armv8-a+sve' switch
gcc/ChangeLog:
2020-02-27 Joel Hutton
PR target/87612
* config/aarch64/aarch64.c (aarch64_override_options): Fix
misleading warning string.
>From 67e2be75db63238bb8d4418db70fb5876465f9f7 Mon Sep 17 00:00:00 2001
From: Joel Hutton
Date: Thu, 27 F
free to eventually revert it.
Great. Vladimir, Ok for trunk?
Changelog:
2020-01-21 Joel Hutton
PR target/93221
* ira.c (ira): Revert use of simplified LRA algorithm.
gcc/testsuite/ChangeLog:
2020-01-21 Joel Hutton
PR target/93221
* gcc.target/aarch64/p
ventually revert it.
Changelog:
2020-01-21 Joel Hutton
PR target/93221
* ira.c (ira): Revert use of simplified LRA algorithm.
gcc/testsuite/ChangeLog:
2020-01-21 Joel Hutton
PR target/93221
* gcc.target/aarch64/pr9322
Changelog was mangled by thunderbird, updated changelog:
Changelog:
2020-01-21 Joel Hutton
PR target/93221
* ira.c (ira): Revert use of simplified LRA algorithm.
gcc/testsuite/ChangeLog:
2020-01-21 Joel Hutton
PR target/93221
* gcc.target/aarch64
Updated changelog:
Changelog:
2020-01-21 Joel Hutton <mailto:joel.hut...@arm.com>
PR target/93221
* ira.c (ira): Revert use of simplified LRA algorithm.
gcc/testsuite/ChangeLog:
2020-01-21 Joel Hutton <mailto:joel.hut...@arm.com>
PR
t is compiled with -O0. Doesn't it ICE without the attribute
> too?
Done. It's not really necessary, belt and braces.
Updated patch attached
From 1a2980ef6eeb76dbf0556f806a85a4f49ad3ebdd Mon Sep 17 00:00:00 2001
From: Joel Hutton
Date: Tue, 21 Jan 2020 09:37:48 +
Subject: [
:
2020-01-21 Joel Hutton
* ira.c (ira): Revert use of simplified LRA algorithm.
gcc/testsuite/ChangeLog:
2020-01-21 Joel Hutton
PR bug/93221
* gcc.target/aarch64/pr93221.c: New test.
From 0d9980d2327c61eb99d041a217d6ea5c5b34c754 Mon Sep 17 00:00:00 2001
From: Joel
he limit would make sense.
What I would do is wait a bit and see. This may become moot soon,
depending on the direction that we want to take for vendor/user branches
with respect to emails. I'm still trying to think this over...
--
Joel
Hello,
> You should include Joel on such questions as the expert on the hooks.
>
> I don't know whether there's something to put in the commit message to say
> "allow this merge of more than 100 commits". I don't think a squashed
> merge is the right w
92391
Tested on x86 and sparc64.
2019-11-26 Joel Hutton
* lib/target-supports.exp: Update vect_char_add target selector
to use its own cache.
From 7ed08950f4440f8605b9df1114edcc8ee834 Mon Sep 17 00:00:00 2001
From: Joel Hutton
Date: Tue, 26 Nov 2019 17:09:12 +
Subject
Forgot to CC maintainer.
On 15/11/2019 18:03, Joel wrote:
> Hi all,
>
> Just looking for some feedback on the approach.
>
> Currently the loop vectorizer can't vectorize the following typical
> loop for getting max value and index from an array:
>
> void test_vec(int
testing is still in progress,
This patch does not work correctly with vect-epilogues-nomask, and the
reason for that is still being investigated.
gcc/ChangeLog:
2019-11-15 Joel Hutton
Tamar Christina
PR tree-optimization/88259
* tree-
tance))
> continue;
>
> before the loop over SLP_TREE_SCALAR_STMTS.
Done.
> + if (!subparts.is_constant () || !(subparts.to_constant ()
> + == CONSTRUCTOR_NELTS (rhs)))
> + continue;
>
> can be better written
> @@ -4061,15 +4201,42 @@ vect_schedule_slp (vec_info *vinfo)
> if (is_a (vinfo))
>
> the ChangeLog doesn't mention this. I guess this isn't necessary
> unless you fail vectorizing late which you shouldn't.
>
It's necessary to avoid:
On 30/10/2019 14:51, Richard Biener wrote:
> On Wed, 30 Oct 2019, Joel Hutton wrote:
>
>> On 30/10/2019 13:49, Richard Biener wrote:
>>> Why do you need this? The vectorizer already creates such CTORs. Any
>>> testcase that you can show?
>> typedef lon
412f996e70636b08d5b615813e..9f8419e4208b7d438ace41892022f93ebcadd019
> 100644
> --- a/gcc/tree-vectorizer.h
> +++ b/gcc/tree-vectorizer.h
> @@ -151,6 +151,10 @@ public:
> /* The root of SLP tree. */
> slp_tree root;
>
> + /* For vector constructors, the constructor stmt that the SLP tree is
> built
> + from, NULL otherwise. */
> + gimple *root_stmt;
>
> as said, make this a stmt_vec_info
>
> Thanks,
> Richard.
>
>
>> gcc/testsuite/ChangeLog:
>>
>> 2019-10-10 Joel Hutton
>>
>> * gcc.dg/vect/bb-slp-40.c: New test.
>> * gcc.dg/vect/bb-slp-41.c: New test.
>>
>>
t? no comments that clarify ;) The vector may be
> used as argument to a call or as source of a store. So I'd simply
> remove this check (and the function).
Done. The thinking was that if the vector was used as a source of a
store the SLP tree would be built from the group
v1.16b
.p2align 3,,7
.L2:
str q0, [x0], 16
cmp x0, x1
bne .L2
ret
.cfi_endproc
.LFE0:
2019-10-11 Joel Hutton joel.hut...@arm.com
* tree-vect-slp.c (vect_analyze_slp_instance): Add case for vector
constructors.
(vect_
Hi all,
I noticed when reading the documentation that BREAK_FROM_IMM_USE_SAFE
was removed at some point in 2006 and replaced with BREAK_FROM_IMM_USE_STMT.
2019-10-10 Joel Hutton joel.hut...@arm.com
* doc/tree-ssa.texi: Update renamed macro name.
From
On 01/10/2019 12:07, Joel wrote:
>
> SLP vectorization: vectorize vector constructors
>
>
> Currently SLP vectorization can build SLP trees staring from
> reductions or from group stores. This patch adds a third starting
> point: vector constructors.
>
>
> For the
Hi all,
Currently SLP vectorization can build SLP trees starting from reductions or
from group stores. This patch adds a third starting point: vector constructors.
For the following aarch64 test case (compiled with -O3 -fno-vect-cost-model):
char g_d[1024], g_s1[1024], g_s2[1024];
void test_
pe mismatches.
> * gfortran.dg/pr41011.f: Add -std=legacy.
> * gfortran.dg/whole_file_1.f90: Change warnings to errors.
> * gfortran.dg/whole_file_2.f90: Likewise.
>
> git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@274551
> 138bc75d-0d04-0410-961f-82ee72b054a4
Joel
);
}
The following warning is emitted:
warning: ignoring return value of 'cmse_check_address_range' declared
with attribute 'warn_unused_result' [-Wunused-result]
6 | cmse_check_address_range((int*)data, 0, 0);
| ^~
gcc/ChangeLo
t, and verifying that the name of the tarball is now
> >correct.
>
> Ok.
Thanks Richard. Pushed to the master branch in binutils-gdb. I looked at
the GCC repository, and couldn't find it there, so synchronization to do
between the two, after all!
--
Joel
dbsupport/create-version.sh
exists, use that to determine the version number.
Tested on x86_64-linux, by running the src-release script with "gdb"
as the argument, and verifying that the name of the tarball is now
correct.
OK to push?
Thanks!
--
Joel
---
src-release.sh | 4 +++
On 01/07/2019 18:03, James Greenhalgh wrote:
>> gcc/testsuite/ChangeLog:
>>
>> 2019-06-12 Joel Hutton
>>
>> * gcc.target/aarch64/fmul_scvtf_1.c: New test.
> This testcase will fail on ILP32 targets where unsigned long will still
> live in a '
Ping, plus minor rework (mostly non-functional changes)
gcc/ChangeLog:
2019-06-12 Joel Hutton
* config/aarch64/aarch64-protos.h (aarch64_fpconst_pow2_recip): New
prototype
* config/aarch64/aarch64.c (aarch64_fpconst_pow2_recip): New function
* config/aarch64
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