Re: [PATCH] Enable GCC support for AMX

Hello, On 12 сен 01:00, Hongyu Wang wrote: > Hi > > Thanks for your review, and sorry for the late reply. It took a while > to finish the runtime test. Thanks for your fixes! The patch is OK for trunk. -- Thanks, K

Re: [PATCH] Enable GCC support for AMX

Hello, On 03 сен 08:17, H.J. Lu wrote: > On Thu, Sep 3, 2020 at 8:08 AM Kirill Yukhin via Gcc-patches > wrote: > > > > Hello, > > > > On 06 июл 09:58, Hongyu Wang via Gcc-patches wrote: > > > Hi: > > > > > > This patch is about to s

Re: [PATCH] Enable GCC support for AMX

Hello, On 06 июл 09:58, Hongyu Wang via Gcc-patches wrote: > Hi: > > This patch is about to support Intel Advanced Matrix Extensions (AMX) > which will be enabled in GLC. > > AMX is a new 64-bit programming paradigm consisting of two > compo nents: a set of 2-dimensional registers (tiles)

Re: [PATCH] x86: Detect Rocket Lake and Alder Lake

Hello, On 16 авг 06:17, H.J. Lu via Gcc-patches wrote: > From arch/x86/include/asm/intel-family.h on Linux kernel master branch: > > #define INTEL_FAM6_ROCKETLAKE 0xA7 > #define INTEL_FAM6_ALDERLAKE0x97 > > * common/config/i386/cpuinfo.h (get_intel_cpu): Detect

Re: [PATCH][AVX512][PR96246] Merge two define_insn: _blendm, _load_mask.

Hello, On 22 июл 12:59, Hongtao Liu via Gcc-patches wrote: > Those two define_insns have same pattern, and > _load_mask would always be matched since it show up > earlier in the md file, and it may lose some opportunity in > pass_reload since _load_mask only have constraint "0C" > for operand2,

Re: [PATCH] [AVX512]For vector compare to mask register, UNSPEC is needed instead of comparison operator [PR96243]

Hello, On 05 авг 09:29, Hongtao Liu wrote: > On Tue, Aug 4, 2020 at 6:28 PM Kirill Yukhin wrote: > > > > On 04 авг 13:26, Kirill Yukhin wrote: > > > Could you please clarify, how your patch relared to [1]? > > > I see from the bug that it describes perf iss

Re: [PATCH] Enable GCC support for AMX

Hello, On 06 июл 09:58, Hongyu Wang via Gcc-patches wrote: > Hi: > > This patch is about to support Intel Advanced Matrix Extensions (AMX) > which will be enabled in GLC. > > AMX is a new 64-bit programming paradigm consisting of two > compo nents: a set of 2-dimensional registers (tiles)

Re: [PATCH] [AVX512]For vector compare to mask register, UNSPEC is needed instead of comparison operator [PR96243]

On 04 авг 13:26, Kirill Yukhin wrote: > Could you please clarify, how your patch relared to [1]? > I see from the bug that it describes perf issue w.r.t. scalar > operations. [1] - https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96226 > > -- > Regards, Kirill Yukhin

Re: [PATCH] [AVX512]For vector compare to mask register, UNSPEC is needed instead of comparison operator [PR96243]

> Bootstrap is ok, regression test is ok for i386 backend. > > 2020-07-20 Hongtao Liu > > gcc/ > PR target/96226 Could you please clarify, how your patch relared to [1]? I see from the bug that it describes perf issue w.r.t. scalar operations. -- Regards, Kirill Yukhin

Re: [PATCH v2 1/2] i386-tdep: Fix naming in zmm and ymm type descriptions.

Hello, On 24 июл 10:59, Felix Willgerodt via Gcc-patches wrote: > gdb/Changelog: > 2020-07-02 Felix Willgerodt > > * i386-tdep.c (i386_zmm_type): Fix field names. > (i386_ymm_type): Fix field names. I guess mailing list is wrong. -- Regards, Kirill Yukhin

Re: [PATCH] x86: Enable FMA in rsqrt2 expander

On 07 июл 09:06, H.J. Lu wrote: > On Tue, Jul 7, 2020 at 8:56 AM Kirill Yukhin wrote: > > > > Hello HJ, > > > > On 28 июн 07:19, H.J. Lu via Gcc-patches wrote: > > > Enable FMA in rsqrt2 expander and fold rsqrtv16sf2 expander into > > > rs

Re: [PATCH] x86: Enable FMA in rsqrt2 expander

Hello HJ, On 28 июн 07:19, H.J. Lu via Gcc-patches wrote: > Enable FMA in rsqrt2 expander and fold rsqrtv16sf2 expander into > rsqrt2 expander which expands to UNSPEC_RSQRT28 for TARGET_AVX512ER. > Although it doesn't show performance change in our workloads, FMA can > improve other workloads. >

Re: [PATCH] Fix up AVX512F 128/256-bit shifts from using EVEX counts (PR target/84786)

gt; for the DImode shift count in instructions that need AVX512VL when EVEX > encoded if AVX512VL is not enabled instead of v. Bootstrapped/regtested > on 7.x branch on x86_64-linux and i686-linux, ok for 7.x? > > Is the testcase alone ok also for trunk/8.2? Patch is ok for trunk and ports. -- Regards, Kirill Yukhin

Re: [patch] Remove redundant intrinsics

Hello Julia! On 04 июн 10:27, Koval, Julia wrote: > Hi, > > Since pre-Icelake ISA already had 128bit version vpclmul and vaes, we already > have intrinsics for them(_mm_aesdec_si128, _mm_aesdeclast_si128, > _mm_aesenc_si128, _mm_aesenclast_si128, _mm_clmulepi64_si128). Therefore > intrinsics

Re: [PATCH] Add constant folding for x86 shift builtins by vector

Hello Jakub, On 09 мая 22:54, Jakub Jelinek wrote: > Hi! > > The following patch on top of the earlier ix86_*fold_builtin patch adds > folding also for the *s{ll,rl,ra}v* builtins. > > Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? Your patch is OK for trunk. -- Thanks, K

Re: [PATCH] Constant fold even masked shift builtins

Hello Jakub, On 11 мая 10:10, Jakub Jelinek wrote: > Hi! > > On top of the earlier 3 pending patches, this patch adds constant folding > of the shifts even when the mask is not all ones (as long as the orig value > argument is VECTOR_CST too). Then we can just do the blend according to the >

Re: [PATCH] Constant folding of x86 vector shift by scalar builtins (PR target/85323)

Hello Jakub, On 08 мая 17:29, Jakub Jelinek wrote: > Hi! > > The following patch adds folding for vector shift by scalar builtins. > If they are masked, so far we only optimize them only if the mask is all > ones. ix86_fold_builtin handles the all constant argument cases, where the > effect of

Re: [PATCH] Add missing _mm512_set{_epi16,_epi8,zero} intrinsics

> compatibility we likely want to have it too. > > Surprisingly, the _mm512_setr_epi{8,16} intrinsics one would expect too > are missing in the ICC I have around. > > Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? Your patch is OK for trunk. -- Regards, Kirill Yukhin

Re: [PATCH, i386]: Implement usadv64qi

Hello Uroš, On 09 мая 13:07, Uros Bizjak wrote: > This patch adds usadv64qi expander, so the compiler is able to > vectorize with 512bit vpsadbw insn. > > 2017-05-09 Uros Bizjak > > PR target/85693 > * config/i386/sse.md (usadv64qi): New expander. > > Bootstrapped

Re: [PATCH] Optimize 128-bit vector insertion into zero 512-bit vector (PR target/85480)

Hello Jakub! On 23 апр 20:31, Jakub Jelinek wrote: > Hi! > > As mentioned in the PR, vmov{aps,apd,dqa{,32,64}} 128-bit instructions > zero the rest of 512-bit register, so we can optimize insertion into zero > vectors using those instructions. > > Bootstrapped/regtested on x86_64-linux and

Re: [PATCH] Add constant folding for _mm*movemask* intrinsics (PR target/85317)

tion > would do on that input and return the resulting INTEGER_CST. > > Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? Your patch is OK for trunk. -- Regards, Kirill Yukhin

Re: Patch ping (Re: [PATCH] Add _mm512_{,mask_}mullox_epi64 intrinsics (PR target/85530))

Hi Jakub, > On 3 May 2018, at 12:28, Jakub Jelinek wrote: > > On Thu, Apr 26, 2018 at 10:09:48PM +0200, Jakub Jelinek wrote: >> ICC apparently has these two intrinsics (why it doesn't have a maskz_ one >> is unclear to me) which are like _mm512_{,mask_}mullo_epi64, except they

Re: Patch ping

Hello Jakub On 16 апр 10:12, Jakub Jelinek wrote: > Hi! > > I'd like to ping the > > http://gcc.gnu.org/ml/gcc-patches/2018-04/msg00414.html > PR85281 - assorted -masm=intel fixes Sorry, for missing that. Patch is OK as far as tests beginning to pass. -- Thanks, K > > patch. Thanks. > >

Re: [PATCH] Fix non-AVX512VL handling of lo extraction from AVX512F xmm16+ (PR target/85328)

> On 12 Apr 2018, at 13:53, Jakub Jelinek <ja...@redhat.com> wrote: > > On Thu, Apr 12, 2018 at 01:46:40PM +0300, Kirill Yukhin wrote: >> >> Hello Jakub! >> >>> On 11 Apr 2018, at 16:27, Jakub Jelinek <ja...@redhat.com> wrote: >>> In

Re: [PATCH] Fix non-AVX512VL handling of lo extraction from AVX512F xmm16+ (PR target/85328)

Hello Jakub! > On 11 Apr 2018, at 16:27, Jakub Jelinek wrote: > > Hi! > > In lots of patterns we assume that we never see xmm16+ hard registers > with 128-bit and 256-bit vector modes when not -mavx512vl, because > HARD_REGNO_MODE_OK refuses those. > Unfortunately, as this

Re: [PATCH] Fix some broadcasts in -masm=intel mode (PR target/85281)

Hello Jakub! On 09 апр 20:29, Jakub Jelinek wrote: > Hi! > > As the following testcase shows, we emit an incorrect PTR prefix in a > vpbroadcastb instruction in -masm=intel mode; gas accepts and the manual > documents that the input operand is xmm2/m8 for vpbroadcastb and > xmm2/m16 for

Re: Patch ping

Hello Jakub, Sorry for missing that. Your patch is OK. — Thanks, K > On 10 Apr 2018, at 13:59, Jakub Jelinek wrote: > > Hi! > > I'd like to ping the > http://gcc.gnu.org/ml/gcc-patches/2018-04/msg00123.html > P1 PR85177 vinsert[if]{32x4,64x2} pattern fix > patch. > >

Re: [PATCH] Improve avx512{f,bw} vec_set (PR middle-end/85090)

> On 31 Mar 2018, at 01:50, Jakub Jelinek wrote: > Hi! > > The code we emit on the following testcases is really terrible, with both > -mavx512f -mno-avx512bw as well as -mavx512bw, rather than doing e.g. >vpinsrw $0, %edi, %xmm0, %xmm1 >vinserti32x4$0,

Re: [PATCH] Fix _blendm

Hello Jakub, On 28 мар 21:24, Jakub Jelinek wrote: > Hi! > > When looking at PR85090, I've looked into tmp-mddump.md and noticed there > some instructions that can't assemble - vblendmd etc., there is only > vpblendmd or vblendmps. I couldn't make a testcase that would reproduce > this though,

Re: [PATCH][i386,AVX] Fix PR84783 - backport missing permutexvar to GCC7

Hello Sebastian! On 22 мар 13:01, Peryt, Sebastian wrote: > Hi, > > This patch adds missing permutexvar intrinsics for backporting to GCC 7 to > resolve PR84783. > > 2018-03-22 Sebastian Peryt > > gcc: > PR84783 > * config/i386/avx512vlintrin.h

Re: [x86,avx] Fix __builtin_cpu_supports for icelake and cannonlake isa

Hello Julia! > On 14 Mar 2018, at 10:48, Koval, Julia <julia.ko...@intel.com> wrote: > > Gentle ping. Your patch is OK for main trunk. — Thanks, K >> -Original Message- >> From: Koval, Julia >> Sent: Monday, February 12, 2018 10:57 AM >> To:

Re: Patch ping

Hello Jakub, On Friday, March 2, 2018, Jakub Jelinek wrote: > Hi! > > I'd like to ping 2 patches: > > http://gcc.gnu.org/ml/gcc-patches/2018-02/msg01340.html > - PR target/84524 avx512* wrong-code bug Patch is OK. > >

Re: [PATCH][i386] Adjust vec_construct cost for AVX256/512, penaltize elementwise load vectorization

Hello Richard, On 14 фев 11:26, Richard Biener wrote: > > The following tries to account for the fact that when constructing > AVX256 or AVX512 vectors from elements we can only use insertps to > insert into the low 128bits of a vector but have to use > vinserti128 or vinserti64x4 to build larger

Re: [PATCH] Fix _vpermi2var3_mask (PR target/84336)

Hello Jakub! > On 13 Feb 2018, at 00:59, Jakub Jelinek wrote: > > Hi! > > The following testcase ICEs, because the expander is called with > a subreg as operands[2], and gen_lowpart on it creates another subreg > from the same pseudo; the instructions rely on match_dup

Re: [x86,avx] Fix __builtin_cpu_supports for icelake and cannonlake isa

Hello Julia. On 15 Jan 08:28, Koval, Julia wrote: > Hi, > This patch fixes subj. Ok for trunk? > > gcc/ > * config/i386/i386.c (F_AVX512VBMI2, F_GFNI, F_VPCLMULQDQ, F_AVX512VNNI, > F_AVX512BITALG): New. > > gcc/testsuite/ > * gcc.target/i386/builtin_target.c

Re: [patch][i386] Fix for PR83828

Hello Olga, On 06 Feb 08:13, Makhotina, Olga wrote: > Hi, > > This patch repairs vpopcnt tests. > > 06.02.2018 Olga Makhotina  > > gcc/testsuite/ > PR target/83828 > * gcc.target/i386/avx512bitalg-vpopcntb-1.c: Fix test. > *

Re: [patch][i386, AVX] Adding missing mask[z]_scalef_round_s[d,s] intrinsics

c.gnu.org > Cc: Uros Bizjak <ubiz...@gmail.com>; Kirill Yukhin <kirill.yuk...@gmail.com>; > Makhotina, Olga <olga.makhot...@intel.com>; Peryt, Sebastian > <sebastian.pe...@intel.com> > Subject: [patch][i386, AVX] Adding missing mask[z]_scalef_round_s[d,s] > in

Re: [patch][i386, AVX] Adding missing mask[z]_sqrt_round_s[d,s] intrinsics

Hello Olga, On 21 Nov 12:46, Makhotina, Olga wrote: > Hi, > > This patch adds missing intrinsics for _mm_mask[z]_sqrt_round_[sd,ss]. > > 21.11.2017 Olga Makhotina  > > gcc/ >   * config/i386/avx512fintrin.h (_mm_mask_sqrt_round_sd, >  

Re: [patch][i386, AVX] Adding missing mask[z]_range[_round]_s[d,s] intrinsics

Hello Olga, On 04 Dec 09:44, Makhotina, Olga wrote: > Hi, > > This patch adds missing intrinsics for _mm_mask[z]_range[_round]_[sd,ss]. > > 04.12.2017 Olga Makhotina  > > gcc/ > * config/i386/avx512dqintrin.h (_mm_mask_range_sd, _mm_maskz_range_sd, >

[PATCH, i386, AVX] PR target/83828: fix AVX-512BITALG test failures

Hello, If masked variant of vpopcnt[w,q] is being issued: there's no way for reload to put 32/64 bit mask into mask register, since kmov[d,q] are only available under -mavx512bw switch. We can insist user to issue -mavx512bw along w/ -mavx512bitalg if she is going to use masked variants of

Re: [PATCH] Fix various x86 avx512{bitalg, vpopcntdq, vbmi2} issues (PR target/83488)

12bitalg-vpshufbitqmb-1.c: Add -mavx512f > -mavx512bw. > * gcc.target/i386/avx512bitalgvl-vpshufbitqmb-1.c: Add -mavx512bw. > * gcc.target/i386/i386.exp: Fix types. Your patch is OK for trunk. I've checked it in. -- Thanks, K > > Thanks, > Julia > > > -Origin

Re: [PATCH] Fix various x86 avx512{bitalg,vpopcntdq,vbmi2} issues (PR target/83488)

Hello Julia, On 12 Jan 08:55, Koval, Julia wrote: > Changelog > > gcc/ > * config/i386/avx512bitalgintrin.h (_mm512_bitshuffle_epi64_mask, > _mm512_mask_bitshuffle_epi64_mask, _mm256_bitshuffle_epi64_mask, > _mm256_mask_bitshuffle_epi64_mask, _mm_bitshuffle_epi64_mask, >

Re: [PATCH] GFNI and misc other fixes (PR target/83604)

Hello Jakub! On 28 Dec 11:07, Jakub Jelinek wrote: > Hi! > > Martin reported sse-13.c ICEs without all the options it has in dg-options. > The problem is that the GFNI builtins used incorrect ISA masks and the > headers too. GFNI has one SSE encoded instruction (but that really needs > SSE2

Re: [PATCH] Fix a vbmi2 ICE (PR target/83604)

Hello Jakub! On 28 Dec 10:10, Jakub Jelinek wrote: > Hi! > > These insns don't really need AVX512BW in any way themselves, only their > masked variants might need it for reloading of the mask register, but that > should be covered in builtins.def, doesn't need duplication in sse.md. > For

Re: [PATCH] Fix avx512vnnivlintrin.h builtins (PR target/83488)

Hello Jakub, On 22 Dec 12:05, Jakub Jelinek wrote: > On Fri, Dec 22, 2017 at 11:41:27AM +0100, Uros Bizjak wrote: > > > Ok for trunk? > > > > OK. > > On top of this patch and the reason why we needed to move avx512vnni > from flags2 to flags instead of just: > case OPT_mavx512vnni: >

Re: [patch][x86,avx] Enable AVX512BITALG

Hello, Julia, On 12 Nov 12:51, Koval, Julia wrote: > Hi, this patch enables AVX512BITALG and AVX512VPOPCNTDQ instructions from > https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf. > Ok for trunk? OK for trunk. I've

Re: [PATCH][i386,AVX] Enable VPCLMULQDQ support

Hello Julia, On 09 Nov 09:47, Koval, Julia wrote: > Hi, this patch enables VPCLMULQDQ instruction from VPCLMULQDQ isaset, defined > here: > https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf > > Ok for trunk? Your patch

Re: [PATCH][i386,AVX] Enable VAES support [5/5]

Hello Julioa, On 08 Nov 12:44, Koval, Julia wrote: > Hi, this patch enables VAESENC instruction from VAES isaset, defined here: > https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf > > Ok for trunk? Your patch is OK.

Re: [PATCH][i386,AVX] Enable VAES support [4/5]

Hello Julia, On 08 Nov 12:42, Koval, Julia wrote: > Hi, this patch enables VAESENC instruction from VAES isaset, defined here: > https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf > > Ok for trunk? Your patch is OK. I've

Re: [PATCH][i386,AVX] Enable VAES support [3/5]

Hello Julia, On 08 Nov 12:38, Koval, Julia wrote: > Patch attached. > > > -Original Message- > > From: Koval, Julia > > Sent: Wednesday, November 08, 2017 1:38 PM > > To: 'GCC Patches' <gcc-patches@gcc.gnu.org> > > Cc: 'Kirill Yukhin' <kiril

Re: [PATCH][i386,AVX] Enable VAES support [2/5]

Hello Julia, On 08 Nov 12:32, Koval, Julia wrote: > Hi, this patch enables VAESDEC instruction from VAES isaset, defined here: > https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf > > Ok for trunk? Patch is OK. Checked

Re: [PATCH][i386,AVX] Enable VAES support [1/5]

Hello Julia, On 25 Oct 12:02, Koval, Julia wrote: > Hi, > This patch enables VAES isaset option. The doc for isaset and instruction: > https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf > > Ok for trunk? Your patch is

Re: [PATCH][i386,AVX] Enable VNNI support [5/5]

Hello Julia, On 24 Oct 11:20, Koval, Julia wrote: > Hi, > This patch enables VPDPWSSDS instruction. The doc for isaset and instruction: > https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf > > Ok for trunk? Your patch is

Re: [PATCH][i386,AVX] Enable VNNI support [4/5]

Hello Julia, On 24 Oct 11:06, Koval, Julia wrote: > Hi, > This patch enables VPDPWSSD instruction. The doc for isaset and instruction: > https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf > > Ok for trunk? Your patch is

Re: [PATCH][i386,AVX] Enable VNNI support [3/5]

On 24 Oct 10:57, Koval, Julia wrote: > Hi, > This patch enables VPDPBUSDS instruction. The doc for isaset and instruction: > https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf > > Ok for trunk? Patch is OK. I've checked

Re: [PATCH][i386,AVX] Enable VAES support [2/5]

Hello Julia, On 08 Nov 12:32, Koval, Julia wrote: > Hi, this patch enables VAESDEC instruction from VAES isaset, defined here: > https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf > > Ok for trunk? Patch is OK. I've

Re: [PATCH][i386,AVX] Enable VAES support [2/5]

Hello Julia, On 08 Nov 12:32, Koval, Julia wrote: > Hi, this patch enables VAESDEC instruction from VAES isaset, defined here: > https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf > > Ok for trunk? Your patch is OK. I've

Re: [PATCH][i386,AVX] Enable VNNI support [1/5]

Hello Julia, On 24 Oct 10:37, Koval, Julia wrote: > Hi, > This patch enables VNNI isaset option. The doc for isaset and instruction: > https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf > > Ok for trunk? Your patch is OK

Re: [PATCH] Re: loading of zeros into {x,y,z}mm registers (take 2)

On 02 Dec 01:13, Jakub Jelinek wrote: > On Fri, Dec 01, 2017 at 02:54:28PM +0100, Jakub Jelinek wrote: > > Will try this: > > That failed to bootstrap, but here is an updated version that passed > bootstrap/regtest on x86_64-linux and i686-linux, ok for trunk? Great. OK. -- Thanks, K

Re: [PATCH, i386] Fix movdi_internal to return MODE_TI with AVX512

Hello Sergey, On 29 Nov 11:05, Shalnov, Sergey wrote: > Hi, > I found wrong MODE_XI used in movdi_internal that cause zmm > Generation with "-march=skylake-avx512 -mprefer-vector-width=128" > options set. This patch fixes the mode and register type but keep using > AVX512 instruction set. > >

[PATCH, i386, AVX] Fix compress test.

Hello, For 32-bit mode there's no __popcnt64 instruction, so replace number of set bit calculation in 64b mask with two invocations of _popcnt32. Test started to pass for me under SDE. gcc/testsuite/ * gcc.target/i386/avx512f-vpcompressb-2.c: Fix popcnt for 32-bit mode. Checked into

Re: [PATCH, i386] Fix wrong instruction vpcmpeqd generation

Hello Sergey, On 24 Nov 15:44, Shalnov, Sergey wrote: > Hi, > I found wrong vpcmpeqd instruction form generated in case of > "-march=skylake-avx512 -mprefer-vector-width=128" options set > > The compiler emits following error at compile stage: > Error: invalid register operand for

Re: [PATCH, i386] Fix registers type for MODE_TI

Hello Sergey, On 24 Nov 14:52, Shalnov, Sergey wrote: > Hi, > I found wrong ymm registers are generated in case of > "-march=skylake-avx512 -mprefer-vector-width=128" options set > > The code looks like: > movq%r11, 64(%rbx) > vpxord %ymm0, %ymm0, %ymm0 > vmovdqa64

Re: [PATCH][i386,AVX] Enable VBMI2 support [7/7]

Hello Julia! On 24 Oct 10:28, Koval, Julia wrote: > Hi, > This patch enables VPSHRDV instruction. The doc for isaset and instruction: > https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf > > Ok for trunk? Your patch is

Re: [PATCH][i386,AVX] Enable VBMI2 support [6/7]

Hello Julia, On 24 Oct 10:16, Koval, Julia wrote: > Hi, > This patch enables VPSHRDV instruction. The doc for isaset and instruction: > https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf > > Ok for trunk? Your patch is

Re: [PATCH][i386,AVX] Enable VBMI2 support [5/7]

Hello Julia, On 24 Oct 10:05, Koval, Julia wrote: > Attached the patch > > > -Original Message- > > From: Koval, Julia > > Sent: Tuesday, October 24, 2017 12:01 PM > > To: GCC Patches <gcc-patches@gcc.gnu.org> > > Cc: Kirill Yukhin <kirill.yu

Re: [PATCH][i386,AVX] Enable VBMI2 support [4/7]

Hello Julia, On 24 Oct 09:08, Koval, Julia wrote: > Hi, > This patch enables VPSHLD instruction. The doc for isaset and instruction: > https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf > > Ok for trunk? You patch is OK

Re: [PATCH][i386,AVX] Enable VBMI2 support [2/7]

On 24 Nov 09:35, Jakub Jelinek wrote: > On Fri, Nov 24, 2017 at 09:34:07AM +0100, Eric Botcazou wrote: > > > This seems to break the build for me: > > > > > > In file included from > > > /home/glisse/repos/gcc/trunk/gcc/config/i386/i386.c:21:0: > > >

Re: [PATCH][i386,AVX] Enable VBMI2 support [3/7]

Hello, Julia! On 24 Oct 08:35, Koval, Julia wrote: > Hi, > This patch enables VPEXPANDB[W] instruction. The doc for isaset and > instruction: > https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf > > Ok for trunk? Your

Re: [PATCH][i386,AVX] Enable VBMI2 support [2/7]

Hello, Julia! On 24 Oct 08:25, Koval, Julia wrote: > Hi, > This patch enables VPCOMPRESSB[W] instruction. The doc for isaset and > instruction: > https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf > > Ok for trunk? Your

Re: [PATCH, i386] Enable option -mprefer-avx256 as default for Intel Skylake configuration

Hello Sergey, On 02 Nov 10:15, Shalnov, Sergey wrote: > Hi, > This patch makes "prefer-avx256" option as default tuning for > "skylake-avx512". > This is due to better performance of 256-bit code for some of the cases. In > case of > Skylake Server the Optimization Manual has following "Since

Re: [x86,avx][patch] Fix PR82983

Hello Julia! On 14 Nov 09:45, Koval, Julia wrote: > Didn't get in the list for some reason. > > > -Original Message- > > From: Koval, Julia > > Sent: Tuesday, November 14, 2017 10:29 AM > > To: GCC Patches <gcc-patches@gcc.gnu.org> > >

Re: [PATCH][i386,AVX] Enable VBMI2 support [1/7]

Hello Julia! On 25 Oct 11:18, Koval, Julia wrote: > Thanks, fix it. > > gcc/ > * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VBMI2_SET, > OPTION_MASK_ISA_AVX512VBMI2_UNSET): New. > (ix86_handle_option): Handle -mavx512vbmi2. > * config/i386/cpuid.h: Add

Re: [patch][i386, AVX] GFNI enabling [4/4]

Hello Julia, On 17 Oct 13:28, Koval, Julia wrote: > Fixed changelog. > > gcc/ > * config/i386/gfniintrin.h (_mm_gf2p8mul_epi8, _mm256_gf2p8mul_epi8, > _mm_mask_gf2p8mul_epi8, _mm_maskz_gf2p8mul_epi8, > _mm256_mask_gf2p8mul_epi8, _mm256_maskz_gf2p8mul_epi8, >

Re: [patch][i386, AVX] GFNI enabling [3/4]

--- > > From: Koval, Julia > > Sent: Tuesday, October 17, 2017 3:26 PM > > To: Jakub Jelinek <ja...@redhat.com> > > Cc: GCC Patches <gcc-patches@gcc.gnu.org>; Kirill Yukhin > > <kirill.yuk...@gmail.com> > > Subject: RE: [patch

Re: [patch][x86] GFNI enabling [2/4]

Hello Julia! On 03 Nov 17:42, Koval, Julia wrote: > Here is the solution I propose: > > gcc/ > * common/config/i386/i386-common.c > (OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET): Remove MPX from flag. > (ix86_handle_option): Move MPX to isa_flags2 and GFNI to isa_flags. > *

Re: [patch][x86] GFNI enabling [2/4]

Hello Julia! On 30 Oct 19:02, Koval, Julia wrote: > Hi, > Fixed that. Your patch is OK for trunk. I've comitted it w/ minor re-indentation in gcc/ChangeLog entry. -- Thanks, K > > > > > > Ok for trunk? > > Few comments: > > 1. Why copyright in config/i386/gfniintrin.h starts from 2014? > > > >

Re: [patch][x86] GFNI enabling [2/4]

On 17 Oct 12:58, Koval, Julia wrote: > Hi, this is the second patch of enabling GFNI ISASET. It adds GF2P8AFFINEINV > instruction. > The instruction is described here: > https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

Re: [patch][i386, AVX] Adding missing CMP* intrinsics

Hello Olga, Sebastian, On 20 Oct 08:36, Peryt, Sebastian wrote: > Hi, > > This patch written by Olga Makhotina adds listed below missing intrinsics: > _mm512_[mask_]cmpeq_[pd|ps]_mask > _mm512_[mask_]cmple_[pd|ps]_mask > _mm512_[mask_]cmplt_[pd|ps]_mask > _mm512_[mask_]cmpneq_[pd|ps]_mask >

Re: [PATCH] Improve V?TImode shifts (PR target/82370)

On 24 Oct 19:14, Uros Bizjak wrote: > On Tue, Oct 24, 2017 at 4:46 PM, Jakub Jelinek wrote: > > On Tue, Oct 24, 2017 at 05:44:44AM -0700, H.J. Lu wrote: > >> > What I can see from config/atom.md: > >> > ;; if palignr or psrldq > >> > (define_insn_reservation "atom_sseishft_2" 1

Re: Patch ping

Hello Jakub, On 24 Oct 13:01, Jakub Jelinek wrote: > http://gcc.gnu.org/ml/gcc-patches/2017-10/msg00525.html > PR target/82460 - improve AVX512* vperm[ti]2* > Kyrill, can you please review this one? Your patch is OK for trunk. -- Thanks, K > > Thanks > > Jakub

Re: [PATCH, i386] Avoid 512-bit mode MOV for prefer-avx256 option in Intel AVX512 configuration

-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On > Behalf Of Kirill Yukhin > Sent: Wednesday, October 18, 2017 8:10 PM > To: Shalnov, Sergey <sergey.shal...@intel.com> > Cc: Jakub Jelinek <ja...@redhat.com>; 'gcc-patches@gcc.gnu.org' > <gcc-patches@gcc.

Re: [PATCH] Improve V?TImode shifts (PR target/82370)

Hello Jakub, Uroš, Jakub On 04 Oct 21:35, Jakub Jelinek wrote: > Hi! > > The following patch tweaks the TImode vector shifts similarly > to the earlier vector shift patch, so that for shifts by immediate > we can accept a memory input. Additionally, it removes the vec_shl_* > expander, because

Re: [x86] GFNI enabling[1/4]

ek [mailto:ja...@redhat.com] > > Sent: Friday, October 13, 2017 9:08 AM > > To: Koval, Julia <julia.ko...@intel.com> > > Cc: GCC Patches <gcc-patches@gcc.gnu.org>; Uros Bizjak > > <ubiz...@gmail.com>; Kirill Yukhin <kirill.yuk...@gmail.com> > > Subjec

Re: [PATCH] Improve AVX512 vector shift patterns (PR target/82370)

Hello Jakub, On 04 Oct 21:29, Jakub Jelinek wrote: > Hi! > > EVEX encoded vector shifts by immediate allow memory operand as input. > We handle this right for the sra patterns by having 3 distinct > define_insns, one TARGET_AVX512VL with masking, where the non-masked > insn names start with *,

Re: [PATCH] Prefer shorter VEX encoding of VP{AND,OR,XOR,ANDN} over EVEX when possible (PR target/82370)

Hello Jakub, Uroš, On 04 Oct 13:41, Uros Bizjak wrote: > On Wed, Oct 4, 2017 at 10:33 AM, Jakub Jelinek wrote: > > Hi! > > > > Most AVX* instructions have the same insn name between VEX and EVEX > > encoded insns and whether it is EVEX or VEX encoded is determined by > > the

Re: [PATCH, i386] Avoid 512-bit mode MOV for prefer-avx256 option in Intel AVX512 configuration

Hello Sergey, On 06 Oct 14:20, Shalnov, Sergey wrote: > Jakub, > I completely agree with you. I fixed the patch. > Currently, TARGET_PREFER256 will work on architectures with 512VL. It will > not work otherwise. > > I will try to find better solution for this. I think I need to look into >

Re: Missing REDUCE[SD,SS] intrinsics

Hello Olga, Sebastian, On 16 Oct 11:20, Peryt, Sebastian wrote: > Hi, > > This patch written by Olga Makhotina adds missing intrinsics for > REDUCE[SD,SS]. > > 16.10.2017 Olga Makhotina > > gcc/ > * config/i386/avx512dqintrin.h (_mm_mask_reduce_sd, >

Re: [PATCH][x86] Add missing intrinsics for VGETMANT[SD,SS] and VGETEXP[SD,SS]

On 06 Jul 09:35, Peryt, Sebastian wrote: > Hi, > > This patch adds missing intrinsics for VGETEXPSD, VGETEXPSS, VGETMANTSD, > VGETMANTSS. > > 2017-07-06 Sebastian Peryt > > gcc/ > * config/i386/avx512fintrin.h (_mm_mask_getexp_round_ss, >

Re: [patch][x86] Remove old rounding code

Hello Julia, On 21 Jun 08:41, Koval, Julia wrote: > Hi, > This patch removes old parallel code for avx512er. Parallel in this case > can't be generated anymore, because all existing patterns were reworked to > unspec in r249423 and r249009. Ok for trunk? Your patch is OK for trunk. I've comitted

Re: [PATHC][x86] Scalar mask and round RTL templates

an > > -Original Message- > From: Kirill Yukhin [mailto:kirill.yuk...@gmail.com] > Sent: Wednesday, July 5, 2017 12:36 PM > To: Peryt, Sebastian <sebastian.pe...@intel.com> > Cc: gcc-patches@gcc.gnu.org > Subject: Re: [PATHC][x86] Scalar mask and round RTL templa

Re: [PATHC][x86] Scalar mask and round RTL templates

2, %1, > %0| > %0, %1, %2}): Changed to ... > v\t{%2, > %1, %0| > %0, %1, %2} ... this. > (v\t{%2, %1, > %0| > %0, %1, %2}): Changed to > ... > > v\t{%2, %1, > %0| > %0, %1, %2} > ... this. Max line length is

Re: [PATHC][x86] Scalar mask and round RTL templates

Hello Sebastian, On 23 Jun 09:00, Peryt, Sebastian wrote: > Hi, > > This patch adds three extra RTL meta-templates for scalar round and mask. > Additionally fixes errors caused by previous mask and round usage in some of > the intrinsics that I found. Could you pls point which intrinsics did

Re: [PATCH] Fix vec_extract_lo_* patterns (PR target/81225)

Hello Jakub, On 29 Jun 18:51, Jakub Jelinek wrote: > Hi! > > This patch fixes various issues with the vec_extract_lo_* patterns. > There are splitters for these, but only for some cases (no mask, and > in one case also not xmm32+ reg) that change those into just a copy or load > of the low part

Re: [PATCH][X86] Fix rounding pattern similar to PR73350

Hello Julia, Uroš, On 16 Jun 09:05, Uros Bizjak wrote: > On Fri, Jun 16, 2017 at 8:46 AM, Koval, Julia wrote: > > Hi, > > > > This test hangs on avx512er, maybe that's why: > >> According to POSIX, the behavior of a process is undefined after it > >> ignores a SIGFPE,

Re: [PATCH] Add mov[us]wb store intrinsics

Hello Julia, On 08 Jun 07:16, Koval, Julia wrote: > Hi, > These patch adds these 9 new intrinsics. Ok for trunk? Your patch is OK for trunk. I've checked it in for you. -- Thanks, K PS: Could you pls add [i386] or [x86] mark to the mail title?

Re: [PATCH][x86][PR73350][PR80862]

Hello Julia, On 05 Jun 10:13, Koval, Julia wrote: > Hi, > > 1 is replace 8 spaces with tab suggested by ./check_GNU_style.sh, should I > still fix it back? > 2,3,4 Done Thanks a lot! Your patch is OK for trunk. I've checked it in for you (r249009.). > CSE is working, spec 2k6 on skylake-avx512

Re: [PATCH] Rename __builtin_ia32_kmov16 to __builtin_ia32_kmovw in gcc-{5,6}-branch

On 31 May 17:28, Uros Bizjak wrote: > On Wed, May 31, 2017 at 12:33 PM, Senkevich, Andrew > wrote: > > Hi, > > > > attached patches are for renaming __builtin_ia32_kmov16 to > > __builtin_ia32_kmovw in GCC 5.* and 6.* branches since it was renamed in > > master. > >

Re: [PATCH][x86][PR73350][PR80862]

On 31 May 11:38, Kirill Yukhin wrote: > Hello Julia, > On 26 May 09:13, Koval, Julia wrote: > > Hi, > > This patch fixes these PR's. Ok for trunk? > > > > gcc/ > > * config/i386/subst.md (round): Fix round pattern. > > * config/i386/i386.c (

Re: [PATCH][x86][PR73350][PR80862]

Hello Julia, On 26 May 09:13, Koval, Julia wrote: > Hi, > This patch fixes these PR's. Ok for trunk? > > gcc/ > * config/i386/subst.md (round): Fix round pattern. > * config/i386/i386.c (ix86_erase_embedded_rounding): > Fix erasing rounding for the fixed pattern. > > Thanks, >

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