Re: [PATCH v2 1/9] RISC-V: minimal support for xtheadvector

On Sat, Nov 18, 2023 at 12:27 PM Jun Sha (Joshua) wrote: > > This patch is to introduce basic XTheadVector support > (march string parsing and a test for __riscv_xtheadvector) > according to https://github.com/T-head-Semi/thead-extension-spec/ > > Contributors: > Jun Sha (Joshua) >

Re: [PATCH V2] RISC-V: Fix bug of tuple move splitter

LGTM, and could you add one more comment before that condition: /* Non-fractional LMUL has whole register moves that don't require a vsetvl for VLMAX. */ On Fri, Nov 17, 2023 at 9:48 PM Juzhe-Zhong wrote: > > Fix segment fault on tuple move: > > bbl loader > z ra

Re: [PATCH] RISC-V: Fix bug of tuple move splitter[PR112561]

> On 11/17/23 07:18, Kito Cheng wrote: > > I didn’t take a closer look yet on the ira/lra dump yet, but my feeling > > is that may cause by the earlyclober modifier isn’t work as expect? > > > > Let me take closer look tomorrow. > Remember that constraints aren't che

Re: [PATCH] RISC-V: Refactor RVV iterators[NFC]

LGTM, that's a really great clean up :) On Sat, Nov 18, 2023 at 11:12 AM Juzhe-Zhong wrote: > > This patch refactors RVV iteratros for easier maintain. > > E.g. > > (define_mode_iterator V [ > RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI > "TARGET_MIN_VLEN > 32") > > RVVM8HI

Re: Re: [PATCH] RISC-V: Fix bug of tuple move splitter[PR112561]

31]) > (reg:DI 6 t1 [247])) "/app/example.c":8:14 206 {*movdi_64bit} > (nil)) > > The latter pass consider "a6" can be replaced by "a7". > Then, the memory address is changed into "a7" which is wrong. > > So. we should emit

Re: [PATCH] RISC-V: Fix bug of tuple move splitter[PR112561]

> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc > index 6a2009ffb05..08bbb657a06 100644 > --- a/gcc/config/riscv/riscv-v.cc > +++ b/gcc/config/riscv/riscv-v.cc > @@ -374,10 +374,24 @@ void > emit_vlmax_insn_lra (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl) > {

Re: Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

Oh, ok I got why it happened and it is definitely caused by my patch (but not that one, it is caused by another patch[1]), let me describe the reason why I try to emit errors. RISC-V has a crazy number of possible extension combinations, so it's easy to make some mistakes by using some unsupported

Re: [PATCH v2] RISC-V: Implement target attribute

Committed with changelog update :P Thanks for the review. On Thu, Nov 16, 2023 at 7:59 AM Christoph Müllner wrote: > > On Tue, Nov 14, 2023 at 3:15 PM Kito Cheng wrote: > > > > The target attribute which proposed in [1], target attribute allow user > > to specify a lo

Re: [PATCH] RISC-V: Save/restore ra register correctly [PR112478]

Committed, thanks for the review and test :) On Thu, Nov 16, 2023 at 7:19 AM Christoph Müllner wrote: > > On Tue, Nov 14, 2023 at 3:15 PM Kito Cheng wrote: > > > > We set ra to fixed register now, but we still need to save/restore that at > > prologue/epilogue if that

Re: [PATCH] RISC-V: Fix ICE in non-canonical march parsing

ntions/pull/14 > Patrick > > On 11/14/23 17:52, Kito Cheng wrote: > > LGTM, and BTW...I am thinking we could relax the canonical order > during parsing, did you have interesting and time working on that > item? > > On Wed, Nov 15, 2023 at 9:35 AM Patrick O'Neill wrote

Re: [PATCH] RISC-V: Change unaligned fast/slow/avoid macros to misaligned [PR111557]

ohhh, thanks for fixing that, LGTM! On Thu, Nov 16, 2023 at 7:31 AM Edwin Lu wrote: > > Fix __riscv_unaligned_fast/slow/avoid macro name to > __riscv_misaligned_fast/slow/avoid to be consistent with the RISC-V API Spec > > gcc/ChangeLog: > > * config/riscv/riscv-c.cc

Re: Re: [PATCH] RISC-V: Disallow RVV mode address for any load/store[PR112535]

0(a5) > lbu a5,%lo(b)(a4) > vse64.v v1,0(a3) > beq a5,zero,.L6 > vmv.x.s a5,v1 > sw zero,0(a5) > > I think the codegen is not good. It should be using scalar load/store. > I think it should be COST MODEL issue. > > ____ > juzhe.zh...

Re: [PATCH] RISC-V: Disallow RVV mode address for any load/store[PR112535]

Curious about the code gen impact, does it make IRA/LRA insert one more move like (set (reg:DI) (subreg:DI (reg:V1DI 155) 0)) and then (set (mem:SI (reg:DI)) (const_int 0))? On Wed, Nov 15, 2023 at 3:15 PM Juzhe-Zhong wrote: > This patch is quite obvious patch which disallow for load/store

Re: [PATCH] RISC-V: Fix ICE in non-canonical march parsing

LGTM, and BTW...I am thinking we could relax the canonical order during parsing, did you have interesting and time working on that item? On Wed, Nov 15, 2023 at 9:35 AM Patrick O'Neill wrote: > > Passing in a base extension in non-canonical order (i, e, g) causes GCC > to ICE: > xgcc: error:

Re: [PATCH v2] RISC-V: Implement target attribute

Oh damm, I found it should be v3, but anyway it's the latest version for the target attribute support...

[PATCH v2] RISC-V: Implement target attribute

The target attribute which proposed in [1], target attribute allow user to specify a local setting per-function basis. The syntax of target attribute is `__attribute__((target("")))`. and the syntax of `` describes below: ``` ATTR-STRING := ATTR-STRING ';' ATTR | ATTR ATTR

[PATCH] RISC-V: Save/restore ra register correctly [PR112478]

We set ra to fixed register now, but we still need to save/restore that at prologue/epilogue if that has used. gcc/ChangeLog: PR target/112478 * config/riscv/riscv.cc (riscv_save_return_addr_reg_p): Check ra is ever lived. gcc/testsuite/gcc/ChangeLog: PR

Re: [PATCH v2 3/3] RISC-V: Add support for XCVbi extension in CV32E40P

I would prefer you suppress those patterns in riscv.cc rather than adjust the including order, T-Head extension goes that way too, so I would prefer to keep it using a consistent way. you can search !TARGET_XTHEAD in riscv.md On Mon, Nov 13, 2023 at 9:36 PM Mary Bennett wrote: > > Spec: >

Re: [PATCH v2] RISC-V: Fixbug for that XTheadMemPair causes interrupt to fail.

I thought Christoph was already committed? Do you mind describing the difference between v1 and v2? On Fri, Nov 10, 2023 at 9:55 PM Jin Ma wrote: > The t0 register is used as a temporary register for interrupts, so it needs > special treatment. It is necessary to avoid using "th.ldd" in the

Re: [PATCH] RISC-V: Fix bug that XTheadMemPair extension caused fcsr not to be saved and restored before and after interrupt.

LGTM Christoph Müllner 於 2023年11月10日 週五，20:55寫道： > On Fri, Nov 10, 2023 at 8:14 AM Jin Ma wrote: > > > > The t0 register is used as a temporary register for interrupts, so it > needs > > special treatment. It is necessary to avoid using "th.ldd" in the > interrupt > > program to stop the

Re: [PATCH] minimal support for xtheadv

Give a few more thought behind my first LGTM: I am OK *IF* binutils bits accepted since it's just kind of bypassing the -march to bintuils to enable those instructions for assembly code. However the situation seems is little more complicated than my expect at beginning...:P Anyway, I still think

Re: [PATCH] RISC-V: Removed unnecessary sign-extend for vsetvl

Should we need a zero-ext version as well? On Wed, Nov 8, 2023 at 9:39 PM Lehua Ding wrote: > > Committed, thanks Juzhe. > > On 2023/11/8 21:29, juzhe.zhong wrote: > > lgtm > > Replied Message > > From Lehua Ding > > Date 11/08/2023 21:27 > > To

Re: [PATCH] RISC-V: Fix the illegal operands for the XTheadMemidx extension.

Thanks, pushed :) On Thu, Nov 9, 2023 at 3:40 PM Jin Ma wrote: > > The pattern "*extend2_bitmanip" and > "*zero_extendhi2_bitmanip" in bitmanip.md are similar > to the pattern "*th_memidx_bb_extendqi2" and > "*th_memidx_bb_zero_extendhi2" in thead.md, which will > cause the wrong instruction to

Re: [PATCH] minimal support for xtheadv

Hi Yi Xuan: This patch is trivial, and generally LGTM, but I would require putting the spec into https://github.com/riscv-non-isa/riscv-toolchain-conventions before merging this, also don't forget include "RISC-V:" in the title, it would be easier to track during the RISC-V GCC sync meeting :)

Re: [PATCH] RISC-V: Fix dynamic LMUL cost model ICE

LGTM, thanks :) On Thu, Nov 9, 2023 at 10:39 AM Juzhe-Zhong wrote: > > When trying to use dynamic LMUL to compile benchmark. > Notice there is a bunch ICEs. > > This patch fixes those ICEs and append tests. > > gcc/ChangeLog: > > * config/riscv/riscv-vector-costs.cc

Re: Re: [PATCH] RISC-V: Normalize user vsetvl intrinsics[PR112092]

On Wed, Nov 8, 2023 at 2:37 PM juzhe.zh...@rivai.ai wrote: > > Another question raise to me. > > Is it necessary we have such many variant of vsetvls? > > I am thinking about redesign: > > __riscv_vsetvl_e8mf8 > __riscv_vsetvl_e16mf4 > __riscv_vsetvl_e32mf2 > __riscv_vsetvl_e64m1 > > They are

Re: [PATCH] RISC-V: Nan-box the result of movhf on soft-fp16

Thanks for the patch!! We also found the same issue on internal testing works and trying to figure out how to resolve that issue yet, this patch is little bit magic, let me take a closer look.. :P On Wed, Nov 8, 2023 at 11:08 AM KuanLin Chen wrote: > > According to spec, fmv.h checks if the

Re: Re: [PATCH] RISC-V: Normalize user vsetvl intrinsics[PR112092]

3 to bb2. > We are not able to remove block bb 1 and bb 2 and create new bb 4 to hold the > vsetvl if bb 1 and bb 2 has the same vsetvl: > > bb 4 (new block) > | > bb 3 > > I don't think we should do this on VSETVL PASS. > ____ > juzhe.zh...

Re: [PATCH] RISC-V: Normalize user vsetvl intrinsics[PR112092]

I thought vsetvli insertion will try to merge them into one for those cases? Could you explain few more reasons why they are not fused now? Not an objection since I could imageing that would be easier to process, just wondering why. On Wed, Nov 8, 2023 at 2:11 PM Juzhe-Zhong wrote: > > Since our

Re: [PATCH] RISC-V: Use stdint-gcc.h in rvv testsuite

LGTM, but title is little bit misleading, it's not really related to rvv, change to either RISC-V or T-head is fine, anyway, you can commit without send v2 :) Christoph Muellner 於 2023年11月7日 週二 17:45 寫道： > From: Christoph Müllner > > stdint.h can be replaced with stdint-gcc.h to resolve some

Re: [PATCH] RISC-V regression test: Fix FAIL of bb-slp-39.c

LGTM On Tue, Nov 7, 2023 at 10:32 AM Juzhe-Zhong wrote: > > Like s390, add riscv to fix the fail. > > gcc/testsuite/ChangeLog: > > * gcc.dg/vect/bb-slp-39.c: Add RISCV. > > --- > gcc/testsuite/gcc.dg/vect/bb-slp-39.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff

Re: [PATCH] RISC-V: Add ABI requirement for XTheadFMemIdx tests

LGTM, and maybe change stdint.h to stdint-gcc.h in xtheadmemidx-helpers.h? that could make it more portable on multi-lib testing. On Tue, Nov 7, 2023 at 3:44 AM Christoph Muellner wrote: > > From: Christoph Müllner > > The XTheadFMemIdx tests set the required ABI for RV32, but not > for RV64,

Re: [PATCH] RISC-V: VECT: Remember to assert any_known_not_updated_vssa

> Oh, you're right! I should have checked the master branch first... and > I was even wondering why it wasn't marked as such. Should perhaps > cherry pick this for gcc-13-with-riscv-opts? gcc-13-with-riscv-opts mostly maintained by Ventana folks, so maybe ask Jeff if you want to cherry pick into

Re: Re: [PATCH] RISC-V: Early expand DImode vec_duplicate in RV32 system

__ > juzhe.zh...@rivai.ai > > > From: Kito Cheng > Date: 2023-11-06 20:38 > To: Juzhe-Zhong > CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc > Subject: Re: [PATCH] RISC-V: Early expand DImode vec_duplicate in RV32 system > Could you add a testca

Re: [PATCH] RISC-V: Early expand DImode vec_duplicate in RV32 system

Could you add a testcase? other than that LGTM. On Mon, Nov 6, 2023 at 8:27 PM Juzhe-Zhong wrote: > > An ICE was discovered in recent rounding autovec support: > > config/riscv/riscv-v.cc:4314 >65 | } > | ^ > 0x1fa5223 riscv_vector::validate_change_or_fail(rtx_def*, rtx_def**, >

Re: [RFC] RISC-V: Support -mcmodel=large.

> Overall it looks pretty good. Does Andestech have a copyright > assignment in place? Or are you contributing under the DCO rule? Kuan-Lin Chen is Andestech folk, and Andestech have signed copyright assignment for most GNU toolchain components I believe :) > https://gcc.gnu.org/dco.html > >

Re: [PATCH 1/4] RISC-V: Recategorize "prefetch" availabilities

> Unless Kito feels otherwise I would suggest keeping a distinct API > interface for each case. Yeah, I think they should have a distinct API.

Re: Re: [PATCH] RISC-V: Add rawmemchr expander.

Could you put it into riscv-string.cc rather than riscv-v.cc? I would like to put those builtin function expander together if possible, riscv-string.cc might little bit confuse, but it's all included in string.h On Fri, Oct 27, 2023 at 3:40 PM juzhe.zh...@rivai.ai wrote: > > LGTM. Thanks. > >

Re: [PATCH V2] RISC-V: Add AVL propagation PASS for RVV auto-vectorization

LGTM, Thanks, it's really awesome - the implementation is simpler than I expected, it's another great improvement for RISC-V GCC! Just make sure Patrick gives a green light on the testing before committing the patch :) On Wed, Oct 25, 2023 at 8:05 PM Juzhe-Zhong wrote: > > This patch

Re: [PATCH] RISC-V: Export some functions from riscv-vsetvl to riscv-v

LGTM, but plz mention it's NFC in the title, no v2 needed :) On Wed, Oct 25, 2023 at 5:03 PM Juzhe-Zhong wrote: > > Address kito's comments of AVL propagation patch. > > Export the functions that are not only used by VSETVL PASS but also AVL > propagation PASS. > > No functionality change. >

Re: [PATCH] RISC-V: Add AVL propagation PASS for RVV auto-vectorization

> +using namespace rtl_ssa; > +using namespace riscv_vector; > + > +/* The AVL propagation instructions and corresponding preferred AVL. > + It will be updated during the analysis. */ > +static hash_map *avlprops; Maybe put into member data of pass_avlprop? > + > +const pass_data

Re: Re: [PATCH v2] RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]

Ok for gcc 13 but just wait one more week to make sure everything is fine as gcc convention :) Li Xu 於 2023年10月24日 週二，15:49寫道： > Committed to trunk. Thanks juzhe. > > > -- > > > > Li Xu > > > > >Ok for trunk (You can commit it to the trunk now). > > > > > > > > > >For GCC-13, I'd

Re: [PATCH V2] RISC-V: Fix ICE for the fusion case from vsetvl to scalar move[PR111927]

LGTM Juzhe-Zhong 於 2023年10月23日 週一 17:41 寫道： > ICE: > > during RTL pass: vsetvl > : In function 'riscv_lms_f32': > :240:1: internal compiler error: in merge, at > config/riscv/riscv-vsetvl.cc:1997 > 240 | } > > In general compatible_p (avl_equal_p) has: > > if (next.has_vl () &&

Re: [PATCH] RISC-V: Fix ICE for the fusion case from vsetvl to scalar move[PR111927]

Few minor comments: On Mon, Oct 23, 2023 at 5:04 PM Juzhe-Zhong wrote: > > ICE: > > during RTL pass: vsetvl > : In function 'riscv_lms_f32': > :240:1: internal compiler error: in merge, at > config/riscv/riscv-vsetvl.cc:1997 > 240 | } > > In general compatible_p (avl_equal_p) has: > > if

Re: [PATCH] RISC-V: Rename some variables of vector_block_info[NFC]

> 1. Remove "m_" prefix as they are not private members. Actually it's not only for private members[1], but I think it's not mandatory, anyway it's not objection, and I am OK with that, just share the doc [1] "When structs and/or classes have member functions, prefer to name data members with a

Re: Continued (Non)mutlib and stub header issue (was Re: [PATCH v2] RISC-V: Use stdint-gcc.h in rvv testsuite)

> When looking around, I stumbled upon commit > d0bbecb1c41 "RISC-V: Add riscv_vector.h wrapper in testsuite to > prevent pull in stdint.h from C library" >work > Which seems like a step in a right direction, but how does one ensure > that the wrapper riscv_vector.h (containing stdint-gcc.h)

Re: [PATCH] RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV

LGTM Juzhe-Zhong 於 2023年10月12日 週四 22:45 寫道： > Like ARM SVE and GCN, add RVV. > > gcc/testsuite/ChangeLog: > > * gcc.dg/vect/bb-slp-pr69907.c: Add RVV. > > --- > gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git

Re: [PATCH v2] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512.

Committed with few changelog tweak :P On Thu, Oct 12, 2023 at 3:37 PM 钟居哲 wrote: > > LGTM > > > juzhe.zh...@rivai.ai > > > From: Kito Cheng > Date: 2023-10-13 02:40 > To: gcc-patches; kito.cheng; palmer; jeffreyalaw; rdapp; juzhe.zh

[PATCH v2] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512.

riscv_legitimize_poly_move was expected to ensure the poly value is at most 32 times smaller than the minimal VLEN (32 being derived from '4096 / 128'). This assumption held when our mode modeling was not so precisely defined. However, now that we have modeled the mode size according to the

Re: [PATCH v2] RISC-V: Make xtheadcondmov-indirect tests robust against instruction reordering

but anyway, I don't have a strong opinion for either way, just go ahead no matter which one you choose. On Thu, Oct 12, 2023 at 11:28 AM Kito Cheng wrote: > > Sorry for the late comment after Jeff say ok, but I guess we may > consider add "-fno-schedule-insns -fno-schedule-in

Re: [PATCH v2] RISC-V: Make xtheadcondmov-indirect tests robust against instruction reordering

Sorry for the late comment after Jeff say ok, but I guess we may consider add "-fno-schedule-insns -fno-schedule-insns2" to avoid disturbing from schedule like some of our test case in gcc/testsuite/gcc.target/riscv/rvv? On Thu, Oct 12, 2023 at 9:12 AM Jeff Law wrote: > > > > On 10/12/23 07:06,

Re: [PATCH] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512.

Yeah, will send v2 today Jeff Law 於 2023年10月12日 週四 09:15 寫道： > > > On 10/11/23 17:17, Kito Cheng wrote: > > Yeah, I'll take you suggestion and go ahead, Robin's suggestion is > > great but it's just a little too magic :P > So there'll be a V2 of this patch, right? Just

Re: [PATCH v1] RISC-V: Support FP llrint auto vectorization

ion from the situation like search from the git logs, > I choose option 2 here and add some description in > as well. > > Finally, is there any best practices for this case? Thank again for > comments. > > Pan > > -Original Message- > From: Kito Cheng >

Re: [PATCH v1] RISC-V: Support FP llrint auto vectorization

Did I miss something? the title says support but it seems only testcase?? On Wed, Oct 11, 2023 at 8:38 PM Li, Pan2 wrote: > > Committed, thanks Juzhe. > > > > Pan > > > > From: juzhe.zh...@rivai.ai > Sent: Thursday, October 12, 2023 11:34 AM > To: Li, Pan2 ; gcc-patches > Cc: Li, Pan2 ; Wang,

Re: RISC-V: Support CORE-V XCVMAC and XCVALU extensions

Take a quick look and maybe fix it like that, but I am not sure the layout is what they want. diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index eb665188caf..1692e43de10 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -21714,7 +21714,7 @@ vector intrinsic specification,

Re: Re: [PATCH v2 1/4] options: Define TARGET__P and TARGET__OPTS_P macro for Mask and InverseMask

Fixed, sorry for disturbing trunk On Wed, Oct 11, 2023 at 3:50 PM Kito Cheng wrote: > > Oh, my bad seem like that was in later patch, let me fix now > > 钟居哲 於 2023年10月11日 週三 15:49 寫道： >> >> ../../../../gcc/gcc/config/riscv/riscv.cc:8142:18: error: >> ‘TARGET_M

[committed] RISC-V: Add TARGET_MIN_VLEN_OPTS to fix the build

gcc/ChangeLog: * config/riscv/riscv-opts.h (TARGET_MIN_VLEN_OPTS): New. --- gcc/config/riscv/riscv-opts.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index e7c6b75c5ea..31ee42dea6b 100644 ---

Re: Re: [PATCH] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512.

c-lmul=m8 > -march=rv64gcv_zvl4096b --param=riscv-autovec-lmul=dynamic > > I will do that in stage 3. I hope this patch can be landed before I do that. > > juzhe.zh...@rivai.ai > > > From: Kito Cheng > Date: 2023-10-05 22:00 > To: Ro

Re: Re: [PATCH v2 1/4] options: Define TARGET__P and TARGET__OPTS_P macro for Mask and InverseMask

PTS (opts); > > > > -- > juzhe.zh...@rivai.ai > > > *From:* Kito Cheng > *Date:* 2023-10-12 05:20 > *To:* Jeff Law > *CC:* Kito Cheng ; gcc-patches > ; palmer ; rdapp > ; juzhe.zhong > *Subject:* Re: [PATCH v2 1/4] options: Define TARGET__P and > TARGET__OPT

Re: [PATCH v2 4/4] RISC-V: Implement target attribute

> Assuming you're agreeable to adjusting the code to avoid alloca, we'll > do a quick turnaround on the v3 -- I'll just audit the return paths to > make sure we don't leak and we'll be good to go. Thanks for point out that, let me figure out which is the best way to fix that, using xstrdup + free

Re: [PATCH v2 2/4] RISC-V: Refactor riscv_option_override and riscv_convert_vector_bits. [NFC]

Thanks, committed :) On Tue, Oct 10, 2023 at 6:51 AM Jeff Law wrote: > > > > On 10/9/23 22:13, Kito Cheng wrote: > > Allow those funciton apply from a local gcc_options rather than the > > global options. > > > > Preparatory for target attribute, sperate thi

Re: [PATCH v2 1/4] options: Define TARGET__P and TARGET__OPTS_P macro for Mask and InverseMask

Thanks, committed, and just did one more check with x86 again, it works as well, hope no more awk portable issue this time :P On Tue, Oct 10, 2023 at 6:51 AM Jeff Law wrote: > > > > On 10/9/23 22:13, Kito Cheng wrote: > > We TARGET__P marcro to test a Mask and InverseMask with

Re: [PATCH v2 3/4] RISC-V: Extend riscv_subset_list, preparatory for target attribute support

Thanks, committed with fixup for those two comments :) On Tue, Oct 10, 2023 at 7:01 AM Jeff Law wrote: > > > > On 10/9/23 22:13, Kito Cheng wrote: > > riscv_subset_list only accept a full arch string before, but we need to > > parse single extension when supporting targe

Re: [PATCH v3 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions

Just repeat what I said on the mailing list again :P it's LGTM, just need to rebase to deal with riscv.opt related changes :) On Sat, Sep 30, 2023 at 8:02 PM Mary Bennett wrote: > > Thank you for reviewing this patch. > > v1->v2: > * Add XCValu RTL. > * Change assembly mnemonics from mixed

[PATCH v2 3/4] RISC-V: Extend riscv_subset_list, preparatory for target attribute support

riscv_subset_list only accept a full arch string before, but we need to parse single extension when supporting target attribute, also we may set a riscv_subset_list directly rather than re-parsing the ISA string again. gcc/ChangeLog: * config/riscv/riscv-subset.h

[PATCH v2 4/4] RISC-V: Implement target attribute

The target attribute which proposed in [1], target attribute allow user to specify a local setting per-function basis. The syntax of target attribute is `__attribute__((target("")))`. and the syntax of `` describes below: ``` ATTR-STRING := ATTR-STRING ';' ATTR | ATTR ATTR

[PATCH v2 2/4] RISC-V: Refactor riscv_option_override and riscv_convert_vector_bits. [NFC]

Allow those funciton apply from a local gcc_options rather than the global options. Preparatory for target attribute, sperate this change for eaiser reivew since it's a NFC. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_convert_vector_bits): Get setting from argument rather than

[PATCH v2 1/4] options: Define TARGET__P and TARGET__OPTS_P macro for Mask and InverseMask

We TARGET__P marcro to test a Mask and InverseMask with user specified target_variable, however we may want to test with specific gcc_options variable rather than target_variable. Like RISC-V has defined lots of Mask with TargetVariable, which is not easy to use, because that means we need to

[PATCH v2 0/4] RISC-V target attribute

This patch set implement target attribute for RISC-V target, which is similar to other target like x86 or ARM, let user able to set some local setting per function without changing global settings. We support arch, tune and cpu first, and we will support other target attribute later, this

Re: [PATCH] RISC-V: Add available vector size for RVV

LGTM On Mon, Oct 9, 2023 at 4:23 PM Juzhe-Zhong wrote: > > For RVV, we have VLS modes enable according to TARGET_MIN_VLEN > from M1 to M8. > > For example, when TARGET_MIN_VLEN = 128 bits, we enable > 128/256/512/1024 bits VLS modes. > > This patch fixes following FAIL: > FAIL:

Re: [PATCH] RISC-V: Make xtheadcondmov-indirect tests robust against instruction reordering

I guess you may also want to clean up those bodies for "check-function-bodies"? On Mon, Oct 9, 2023 at 3:47 PM Christoph Muellner wrote: > > From: Christoph Müllner > > Fixes: c1bc7513b1d7 ("RISC-V: const: hide mvconst splitter from IRA") > > A recent change broke the xtheadcondmov-indirect

Re: [PATCH v1 1/4] options: Define TARGET__P and TARGET__OPTS_P macro for Mask and InverseMask

> Doesn't this need to be updated to avoid multi-dimensional arrays in awk > and rebased? Oh, yeah, I should update that, it's post before that issue reported, let me send v2 sn :P

Re: [PATCH v1] RISC-V: Update comments for FP rounding related autovec

LGTM 於 2023年10月6日 週五 10:39 寫道： > From: Pan Li > > Some comment is out of date, this patch would like to fix it. > > gcc/ChangeLog: > > * config/riscv/autovec.md: Update comments. > > Signed-off-by: Pan Li > --- > gcc/config/riscv/autovec.md | 6 +- > 1 file changed, 5

Re: [PATCH v2] RISC-V: Use stdint-gcc.h in rvv testsuite

LGTM Patrick O'Neill 於 2023年10月6日 週五 07:46 寫道： > stdint.h can be replaced with stdint-gcc.h to resolve some missing > system headers in non-multilib installations. > > Tested using glibc rv32gcv and rv64gcv on r14-4381-g7eb5ce7f58e. > > gcc/testsuite/ChangeLog: > > *

Re: [PATCH] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512.

Hi Robin: Your suggested code seems work fine, let me run more test and send v2, I guess I just don’t know how to explain why it work in comment :p Robin Dapp 於 2023年10月5日 週四，03:57寫道： > >> I think the "max poly value" is the LMUL 1 mode coeffs[1] > >> > >> See int vlenb =

Re: [PATCH] RISC-V: THead: Fix missing CFI directives for th.sdd in prologue.

LGTM, will commit if nobody commit that tomorrow :p Christoph Müllner 於 2023年10月4日 週三，23:04寫道： > On Wed, Oct 4, 2023 at 9:49 AM Xianmiao Qu > wrote: > > > > From: quxm > > > > When generating CFI directives for the store-pair instruction, > > if we add two parallel REG_FRAME_RELATED_EXPR

Re: [PATCH] options: Prevent multidimensional arrays

committed to trunk, got approval from Jeff in another mail thread: https://gcc.gnu.org/pipermail/gcc-patches/2023-October/631873.html :) On Mon, Oct 2, 2023 at 4:03 PM Kito Cheng wrote: > > Multidimensional arrary is gawk extension, and we accidentally > introduced that in recent

Re: [PATCH] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512.

钟居哲 於 2023年10月4日 週三，20:20寫道： > > I think the "max poly value" is the LMUL 1 mode coeffs[1] > > See int vlenb = BYTES_PER_RISCV_VECTOR.coeffs[1]; > > So I think bump max_power to exact_log2 (64); is not enough. > since we adjust the LMUL 1 mode size according to TARGET_MIN_VLEN. > > I suspect the

Re:

Ooop, I screwed up when writing my cover letter of the target attribute patch set... On Tue, Oct 3, 2023 at 5:10 PM Kito Cheng wrote: > > From: Kito Cheng > > Reply-To: > > Subject: [PATCH v1 0/4] RISC-V target attribute > > In-Reply-To: > > This patch set impleme

[PATCH v1 3/4] RISC-V: Extend riscv_subset_list, preparatory for target attribute support

riscv_subset_list only accept a full arch string before, but we need to parse single extension when supporting target attribute, also we may set a riscv_subset_list directly rather than re-parsing the ISA string again. gcc/ChangeLog: * config/riscv/riscv-subset.h

[PATCH v1 4/4] RISC-V: Implement target attribute

The target attribute which proposed in [1], target attribute allow user to specify a local setting per-function basis. The syntax of target attribute is `__attribute__((target("")))`. and the syntax of `` describes below: ``` ATTR-STRING := ATTR-STRING ';' ATTR | ATTR ATTR

[PATCH v1 2/4] RISC-V: Refactor riscv_option_override and riscv_convert_vector_bits. [NFC]

Allow those funciton apply from a local gcc_options rather than the global options. Preparatory for target attribute, sperate this change for eaiser reivew since it's a NFC. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_convert_vector_bits): Get setting from argument rather than

[no subject]

From: Kito Cheng Reply-To: Subject: [PATCH v1 0/4] RISC-V target attribute In-Reply-To: This patch set implement target attribute for RISC-V target, which is similar to other target like x86 or ARM, let user able to set some local setting per function without changing global settings. We

[PATCH v1 1/4] options: Define TARGET__P and TARGET__OPTS_P macro for Mask and InverseMask

We TARGET__P marcro to test a Mask and InverseMask with user specified target_variable, however we may want to test with specific gcc_options variable rather than target_variable. Like RISC-V has defined lots of Mask with TargetVariable, which is not easy to use, because that means we need to

Re: [PATCH v3] RISC-V:Optimize the MASK opt generation

Proposed fix, and verified with "mawk" and "gawk -P" (gawk with posix mode) on my linux also some other report it work on freebsd, just wait review :) https://gcc.gnu.org/pipermail/gcc-patches/2023-October/631785.html On Tue, Oct 3, 2023 at 2:07 AM Jeff Law wrote: > > > > On 10/2/23 12:03,

[PATCH] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512.

riscv_legitimize_poly_move was expected to ensure the poly value is at most 32 times smaller than the minimal VLEN (32 being derived from '4096 / 128'). This assumption held when our mode modeling was not so precisely defined. However, now that we have modeled the mode size according to the

Re: [PATCH v2] RISC-V: Implement TLS Descriptors.

Just one nit and one more comment for doc: Could you add some doc something like that? mostly I grab from other target, so you can just included in the patch. diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index 31f2234640f..39396668da2 100644 --- a/gcc/doc/install.texi +++

Re: [PATCH] RISC-V: Use stdint-gcc.h in rvv testsuite

> > On Tue, Sep 26, 2023 at 10:59 AM Patrick O'Neill > > wrote: > >> stdint.h can be replaced with stdint-gcc.h to resolve some missing > >> system headers in non-multilib installations. > >> > >> Tested using glibc rv32gcv and rv64gcv on r14-4258-gc9837443075. > >> > >> gcc/ChangeLog: > >> > >>

[PATCH] options: Prevent multidimensional arrays

Multidimensional arrary is gawk extension, and we accidentally introduced that in recent commit[1]. [1] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=e4a4b8e983bac865eb435b11798e38d633b98942 gcc/ChangeLog: * opt-read.awk: Drop multidimensional arrays. * opth-gen.awk: Ditto. ---

Re: [PATCH v6] RISC-V:Optimize the MASK opt generation

Hi Gerald: Thanks for reporting this issue, I just realized multidimensional arrays are gawk extensions, could you try the attached patch to see if it can resolve the issue? On Mon, Oct 2, 2023 at 4:56 AM Gerald Pfeifer wrote: > > On Sun, 1 Oct 2023, Kito Cheng wrote: > > Commit

Re: [PATCH v6] RISC-V:Optimize the MASK opt generation

Committed to trunk, thanks Feng :) On Sat, Sep 30, 2023 at 3:34 AM Jeff Law wrote: > > > > On 9/12/23 03:18, Feng Wang wrote: > > New patch add some comments and update docs for this new usage. > > --- > > Accoring to Kito's advice, using "MASK(name) Var(other_flag_name)" > > to generate MASK

Re: [PATCH v6] RISC-V:Optimize the MASK opt generation

Hi Jeff: Could you take a look for this? RISC-V part is ok to me. Thanks :) Feng Wang 於 2023年9月12日 週二 17:18 寫道： > New patch add some comments and update docs for this new usage. > --- > Accoring to Kito's advice, using "MASK(name) Var(other_flag_name)" > to generate MASK and TARGET MACRO

Re: Re: [PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566]

that pattern between reload and split2? > > I have no ideal. Some fortran tests just need recognization of mem-to-mem > pattern before RA. > I don't know the reason. > > ____ > juzhe.zh...@rivai.ai > > > From: Kito Cheng > Date: 2023-09-27

Re: [PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566]

> (define_insn_and_split "*mov" >[(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr") > (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))] >"TARGET_VECTOR > - && (register_operand (operands[0], mode) > + && (can_create_pseudo_p () Why add

Re: [PATCH 2/2] RISC-V: Add support for XCValu extension in CV32E40P

Hi Mary: Several inline comments, mostly are related to the RTX pattern. I guess we don't really need those unspec except clip*. > diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md > index 59aeafe485f..30c8bcbe476 100644 > --- a/gcc/config/riscv/corev.md > +++

Re: [PATCH v1] RISC-V: Remove FP run test for ceil.

I guess it just needs more checks than `target { riscv_vector }`, maybe something like `target { riscv_vector_zvfh }`, but anyway I am fine to drop this for now. On Sat, Sep 23, 2023 at 2:11 AM Li, Pan2 wrote: > > Committed, thanks Juzhe. > > > > Pan > > > > From: 钟居哲 > Sent: Saturday,

Re: [Committed] RISC-V: Support VLS unary floating-point patterns

GCC has built in function[1] for those math function stuff, e.g. __builtin_ceilf, so we don't really need math.h :) [1] https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html On Thu, Sep 21, 2023 at 11:20 AM Palmer Dabbelt wrote: > > On Wed, 20 Sep 2023 10:47:23 PDT (-0700), Patrick O'Neill

Re: [PATCH] RISC-V: Enable undefined support for RVV auto-vectorization[PR110751]

Cool, LGTM as well! On Thu, Sep 21, 2023 at 10:11 AM Robin Dapp wrote: > > Hi Juzhe, > > with the middle-end changes that's a nice improvement. LGTM. > > Regards > Robin

Re: [PATCH] RISC-V: Remove math.h import to resolve missing stubs failures

LGTM Patrick O'Neill 於 2023年9月20日 週三 18:07 寫道： > Resolves some of the missing stubs failures: > fatal error: gnu/stubs-lp64d.h: No such file or directory > compilation terminated. > > 2023-09-20 Juzhe Zhong > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/vls/def.h:

Re: [Committed] RISC-V: Fix Demand comparison bug[VSETVL PASS]

Does it also happened on gcc 13 branch? If so plz backport :) Juzhe-Zhong 於 2023年9月20日 週三 11:09 寫道： > This bug is exposed when we support VLS integer conversion patterns. > > FAIL: c-c++-common/torture/pr53505.c execution. > > This is because incorrect vsetvl elimination by Phase 4: > >

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