On 7 April 2014 14:46, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
2014-04-04 Kyrylo Tkachov kyrylo.tkac...@arm.com
* config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Check
TARGET_SIMD rather than TARGET_GENERAL_REGS_ONLY.
(TARGET_SIMD): Take AARCH64_ISA_SIMD
On 10 April 2014 12:05, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This is the 4.8 version of the patch posted at:
http://gcc.gnu.org/ml/gcc-patches/2014-04/msg00315.html
TARGET_CRYPTO was not defined in 4.8 therefore that hunk is removed.
Ok for the 4.8 branch?
Thanks,
Kyrill
On 23 April 2014 20:17, Alan Lawrence alan.lawre...@arm.com wrote:
This adds DejaGNU tests of the existing AArch64 vrev_* intrinsics, both
checking the assembler output and the runtime results. Test bodies are in
separate files ready to reuse for ARM in the third patch.
All tests passing on
On 23 April 2014 20:44, Alan Lawrence alan.lawre...@arm.com wrote:
This patch (borrowing heavily from the ARM backend) makes
aarch64_expand_vec_perm_const output REV instructions when appropriate,
and then implements the vrev_XXX intrinsics in terms of __builtin_shuffle
(which
now produces
On 23 April 2014 21:01, Alan Lawrence alan.lawre...@arm.com wrote:
This adds DejaGNU tests of the existing AArch64 vext* intrinsics, both
checking the assembler output and the runtime results. Test bodies are in
separate files ready to reuse for ARM in the third patch.
All passing on
gcc/ChangeLog:
2014-04-11 Alan Lawrence alan.lawre...@arm.com
* config/aarch64/aarch64.c (aarch64_evpc_tbl): enable for bigendian.
gcc/testsuite/ChangeLog:
2014-04-11 Alan Lawrence alan.lawre...@arm.com
* lib/target-supports.exp (check_effective_target_vect_perm):
On 23 April 2014 10:22, Richard Earnshaw rearn...@arm.com wrote:
libgfortran/
2014-04-17 Kyrylo Tkachov kyrylo.tkac...@arm.com
* configure.ac: Quote usage of ac_cv_func_clock_gettime in if test.
* configure: Regenerate.
This looks fairly safe to me. My only question might be
On 27 March 2014 10:52, Alan Lawrence alan.lawre...@arm.com wrote:
This adds DejaGNU tests of the existing AArch64 vzip_* intrinsics, both
checking the assembler output and the runtime results. Test bodies are in
separate files ready to reuse for ARM in the third patch. Putting these in a
new
On 27 March 2014 10:52, Alan Lawrence alan.lawre...@arm.com wrote:
This patch replaces the temporary inline assembler for vzip_* in arm_neon.h
with equivalent calls to __builtin_shuffle. These are matched by
aarch64_expand_vec_perm_const{,_1} to output the same assembler
instructions.
Tests
On 27 March 2014 17:17, Alan Lawrence alan.lawre...@arm.com wrote:
This adds DejaGNU tests of the existing AArch64 vuzp_* intrinsics, both
checking the assembler output and the runtime results. Test bodies are in
separate files ready to reuse for ARM in the third patch.
Putting these in a new
On 27 March 2014 17:25, Alan Lawrence alan.lawre...@arm.com wrote:
This patch replaces the temporary inline assembler for vuzp_* in arm_neon.h
with equivalent calls to __builtin_shuffle. These are matched by
aarch64_expand_vec_perm_const{,_1} to output (generally) the same assembler
On 8 January 2014 18:13, Richard Henderson r...@redhat.com wrote:
* config/aarch64/aarch64 (addti3, subti3): New expanders.
(addGPI3_compare0): Remove leading * from name.
(addGPI3_carryin): Likewise.
(subGPI3_compare0): Likewise.
(subGPI3_carryin):
On 8 January 2014 18:13, Richard Henderson r...@redhat.com wrote:
* config/aarch64/aarch64.md (multi3): New expander.
(maddGPI): Remove leading * from name.
I think this should go in now we are in stage-1 /Marcus
On 8 January 2014 18:13, Richard Henderson r...@redhat.com wrote:
* config/aarch64/aarch64.md (su_optabmulditi3): New expander.
---
gcc/config/aarch64/aarch64.md | 17 +
1 file changed, 17 insertions(+)
diff --git a/gcc/config/aarch64/aarch64.md
On 18 February 2014 12:40, James Greenhalgh james.greenha...@arm.com wrote:
2014-02-18 James Greenhalgh james.greenha...@arm.com
* config/aarch64/aarch64-protos.h (aarch64_modes_tieable_p): New.
* config/aarch64/aarch64.c
(aarch64_cannot_change_mode_class): Weaken
Hi, I just committed the attached to fix up some indentation in aarch64.c
/Marcuscommit 9484cf884a28c18e310b31fcc283f75ade42e93d
Author: Marcus Shawcroft marcus.shawcr...@arm.com
Date: Tue Apr 22 13:27:39 2014 +0100
[AArch64] Fix indentation.
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
On 22 April 2014 14:23, Jiong Wang jiong.w...@arm.com wrote:
2014-04-22 Renlin renlin...@arm.com
2014-04-22 Jiong Wang jiong.w...@arm.com
gcc/
* config/aarch64/aarch64.h (aarch64_frame): Delete fp_lr_offset.
* config/aarch64/aarch64.c (aarch64_layout_frame): Likewise.
*
On 22 April 2014 14:40, Tejas Belagod tbela...@arm.com wrote:
Alan Lawrence wrote:
Sorry to be pedantic again, but 'wierd' should be spelt 'weird'.
Otherwise,
looks good to me and much neater than before. (Seems you'd rather keep the
re-enabling, here and in the testsuite, for another
On 22 April 2014 17:09, Yufeng Zhang yufeng.zh...@arm.com wrote:
Ping~
OK for stage-1?
The original patch was posted here:
http://gcc.gnu.org/ml/gcc-patches/2014-01/msg00286.html
and the glibc patch was approved here:
http://sourceware.org/ml/libc-alpha/2014-01/msg00120.html
The glibc
On 19 March 2014 09:55, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
[gcc/]
2014-03-19 Kyrylo Tkachov kyrylo.tkac...@arm.com
* config/aarch64/aarch64.md (rev16mode2): New pattern.
(rev16mode2_alt): Likewise.
* config/aarch64/aarch64.c (aarch64_rtx_costs): Handle rev16 case.
On 19 March 2014 09:56, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This patch depends on the series started at
http://gcc.gnu.org/ml/gcc-patches/2014-03/msg00933.html but is not really a
part of it. It just adds costing of the bswap operation using the new rev
field in the rtx cost
On 28 March 2014 14:52, Ramana Radhakrishnan ramana@googlemail.com wrote:
To my mind on ARM / AArch64 this actually helps anyone using the
crypto intrinsics on A53 hardware today and it would be good to get
this into 4.9. Again I perceive this as low risk on ARM (AArch32) as
this is not a
and to give the
RM's the chance to object before committing.
Cheers
/Marcus
2014-03-25 Marcus Shawcroft marcus.shawcr...@arm.com
PR target/60580
* config/aarch64/aarch64.c (faked_omit_frame_pointer): Remove.
(aarch64_frame_pointer_required): Adjust logic
On 25 March 2014 04:55, Kugan kugan.vivekanandara...@linaro.org wrote:
gcc/
2014-03-25 Kugan Vivekanandarajah kug...@linaro.org
PR target/60034
* aarch64/aarch64.c (aarch64_classify_address): Fix alignment for
section anchor.
gcc/testsuite/
2014-03-25 Kugan
On 24 March 2014 11:26, Jiong Wang jiong.w...@arm.com wrote:
gcc/
* config/arm/predicates.md (call_insn_operand): Add long_call check.
* config/arm/arm.md (sibcall, sibcall_value): Force the address to reg for
long_call.
* config/aarch64/aarch64.c (arm_function_ok_for_sibcall): Remove
On 24/03/14 10:00, James Greenhalgh wrote:
*ping*
Jakub pointed out to me recently that obvious patches are OK even in
Stage 4, so if I don't hear any objections in 24 hours, I'll push
this.
Thanks,
James
OK /Marcus
On 21 March 2014 14:55, Alan Lawrence alan.lawre...@arm.com wrote:
This patch fixes a bug whereby a vector like V8QImode {1,0,1,0,1,0,1,0} can
result in an instruction like
movi v1.4h, 0x1
whereas on bigendian this should be
movi v1.4h, 0x1, lsl 8
Regression tested on
On 14 March 2014 16:22, Alex Velenko alex.vele...@arm.com wrote:
Hi,
This patch adds vdup intrinsic testcases for AArch64. those testcases
are nice to have, as it allows to reason about vdup consistency for
both LE and BE compiler flavors.
gcc/testsuite/
2014-03-14 Alex Velenko
On 25 February 2014 11:58, Alex Velenko alex.vele...@arm.com wrote:
Hi,
This patch fixes a bug in vshr_n_u64 and vshrd_n_u64 intrinsic
behavior in case of shift by 64. Shift by 64 is strictly defined in ACLE to
use ushr instruction intended by those intrinsics.
The testcase provided also
On 28 February 2014 10:30, Alex Velenko alex.vele...@arm.com wrote:
Hi Richard,
Thank you for your suggestion. Attached is a patch that includes
implementation of your proposition. A testsuite was run on LE and BE
compilers with no regressions.
Here is the description of the patch:
This
On 28 February 2014 09:32, Ramana Radhakrishnan ramra...@arm.com wrote:
Hi,
This defines TARGET_FLAGS_REGNUM for AArch64 to be CC_REGNUM.
Noticed this turns on the cmpelim pass after reload and in a few examples
and a couple of benchmarks I noticed a number of comparisons getting
On 19 March 2014 17:11, Venkataramanan Kumar
venkataramanan.ku...@linaro.org wrote:
I have incorporated your review comments and split the patch into two.
The first patch attached here contains Aarch64 machine descriptions
for the stack protect patterns.
ChangeLog.
2014-03-19
On 19 March 2014 17:18, Venkataramanan Kumar
venkataramanan.ku...@linaro.org wrote:
I used the existing dg-require-effective-target check,
stack_protector and added it in a separate line.
ChangeLog.
2014-03-19 Venkataramanan Kumar venkataramanan.ku...@linaro.org
*
On 18/03/14 09:43, Ramana Radhakrishnan wrote:
Hi,
While looking at something else I realized that we had MEMORY_MOVE_COST
defined in the backend. However we also have the more recent target hook
defined for this through TARGET_MEMORY_MOVE_COST making it obvious to
remove this
2014-02-13 9:46 GMT+00:00 Alex Velenko alex.vele...@arm.com:
Hi,
This patch re-implements vreinterpret intrinsics to directly call a cast.
The aim is to forward as much information to front-end as possible.
This patch had a full LE and BE regression run with no regressions.
Is patch good to
On 12 February 2014 10:54, Alex Velenko alex.vele...@arm.com wrote:
Hi,
This patch implements vqneg_s64, vqnegd_s64, vqabs_s64 and
vqabsd_s64 AArch64 intrinsics. Regression tests added.
Run full regression with no regressions.
Is patch OK?
Thanks,
Alex
gcc/
2014-02-12 Alex Velenko
Hi Venkat
On 5 February 2014 10:29, Venkataramanan Kumar
venkataramanan.ku...@linaro.org wrote:
Hi Marcus,
+ ldr\\t%x2, %1\;str\\t%x2, %0\;mov\t%x2,0
+ [(set_attr length 12)])
This pattern emits an opaque sequence of instructions that cannot be
scheduled, is that necessary? Can we not
Hi Kugan
On 3 March 2014 21:56, Kugan kugan.vivekanandara...@linaro.org wrote:
gcc/
2014-03-03 Kugan Vivekanandarajah kug...@linaro.org
PR target/60034
* aarch64/aarch64.c (aarch64_classify_address): Fix alignment for
section anchor.
gcc/testsuite/
On 11 March 2014 11:48, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
- if test x$target_cpu_cname = x
+ if test x$target_cpu_cname != x
I think the addition of quoting here is orthogonal to the issue you
are fixing. There are several other references to target_cpu_cname in
config.gcc none
+ else if (SYMBOL_REF_HAS_BLOCK_INFO_P (sym)
This test makes sense.
+SYMBOL_REF_ANCHOR_P (sym)
Do we need this test or is the patch being conservative? I would
have thought that it is sufficient to drop this test and just take the
block alignment...
Thanks for the
On 28/02/14 17:44, Yufeng Zhang wrote:
Hi,
The attached patch fixes a bug in ./src/aarch64/sysv.S:ffi_closure_SYSV
where stack unwinding information was not generated correctly. The
change has been reviewed, approved and merged into the stand-alone
libffi release tree**.
OK for the trunk?
On 24/02/14 14:05, Yufeng Zhang wrote:
Hi Marcus,
On 01/14/14 12:30, Marcus Shawcroft wrote:
On 6 January 2014 12:30, Yufeng Zhangyufeng.zh...@arm.com wrote:
This patch fixes the implementation of vcvtmd_s64_f64 and vcvtpd_s64_f64 in
arm_neon.h to use llfloor and llceil instead, which
this to go in now during stage-4 in order to have slightly less
noisy 4.9 regression tests for the next n years.
OK?
Cheers
/Marcus
testsuite/ChangeLog
2014-03-12 Marcus Shawcroft marcus.shawcr...@arm.com
* lib/profopt.exp (profopt-execute): Use $testcase in
unsupported.diff --git
On 25 February 2014 10:08, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
The problem solved in this patch is that when gcc is configured with
--with-arch=armv8-a gcc will go into aarch64-arches.def, pick the
representative CPU (Cortex-A53 for ARMv8-A) and use that CPUs ISA flags. Now
On 7 March 2014 09:35, Thomas Preud'homme thomas.preudho...@arm.com wrote:
+++ b/gcc/testsuite/gcc.dg/optimize-bswapsi-2.c
@@ -0,0 +1,26 @@
+/* { dg-do compile { target arm*-*-* alpha*-*-* i?86-*-* powerpc*-*-*
rs6000-*-* x86_64-*-* s390*-*-* } } */
I'm fairly sure the target list here
On 13 February 2014 16:03, James Greenhalgh james.greenha...@arm.com wrote:
Hi,
This patch rewrites the vst4_lane intrinsics in terms of RTL builtins.
Tested on aarch64-none-elf with no issues.
OK to queue for Stage 1?
OK for stage 1
/Marcus
On 21 February 2014 04:24, Kugan kugan.vivekanandara...@linaro.org wrote:
Compiling inline asm results in ICE (PR60034). Alignment calculation in
aarch64_classify_address for (symbol_ref:DI (*.LANCHOR4) [flags
0x182])) seems wrong here.
Hi Kugan,
+ else if (SYMBOL_REF_FLAGS (sym))
+
On 24 February 2014 10:01, Ian Bolton ian.bol...@arm.com wrote:
Hi,
This is needed for when people are porting their aarch32 code to aarch64.
They will have #ifdef __ARM_NEON (as specified in ACLE) and their intrinsics
currently won't get used on aarch64 because it's not defined there by
On 24 February 2014 09:49, Renlin Li renlin...@arm.com wrote:
gcc/testsuite/ChangeLog:
2014-02-03 Renlin Li renlin...@arm.com
* gcc.target/aarch64/aapcs64/validate_memory.h: Move f32in64 and
i32in128 cases
outside special big-endian processing block.
This is is a fix for a
On 12 February 2014 16:10, Renlin Li renlin...@arm.com wrote:
gcc/ChangeLog:
2014-02-12 Renlin Li renlin...@arm.com
* config/aarch64/aarch64.c (aarch64_print_operand_address): Adjust the
output asm format
by adding a space between base register and offset.
OK for stage-1.
On 24 February 2014 18:17, James Greenhalgh james.greenha...@arm.com wrote:
gcc/
2014-02-24 James Greenhalgh james.greenha...@arm.com
* config/aarch64/aarch64-simd.md
(aarch64_cmoptabdi): Always split.
(*aarch64_cmoptabdi): New.
(aarch64_cmtstdi): Always
On 26 February 2014 02:25, Andrew Pinski apin...@cavium.com wrote:
Hi,
With ILP32, some simple usage of TLS variables causes an unrecognizable
instruction due to needing to use SImode for loading pointers from memory.
This fixes the three (tlsie_small, tlsle_small, tlsdesc_small) patterns to
On 21 February 2014 12:44, Alex Velenko alex.vele...@arm.com wrote:
This patch adds vrnd*_f64 aarch64 intrinsics. A testcase for those
intrinsics is added. Run a complete LE and BE regression run with no
regressions.
Is patch OK for stage-1?
gcc/
2014-02-21 Alex Velenko
On 3 February 2014 10:02, Renlin Li renlin...@arm.com wrote:
2014-02-03 Renlin Li renlin...@arm.com
* gcc.target/aarch64/aapcs64/validate_memory.h: move f32in64 and
i32in128 cases
outside special big-endian processing block.
This is a test case fix. This is ok with me but needs a
On 6 February 2014 22:51, Michael Hudson-Doyle
michael.hud...@canonical.com wrote:
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 16c51a8..958c667 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1187,14 +1187,10 @@
On 10 February 2014 09:55, Marcus Shawcroft marcus.shawcr...@gmail.com wrote:
On 30 January 2014 13:48, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This patch wires up the aarch64 backend to use the Cortex-A57 rtx costs
table that is proposed at
http://gcc.gnu.org/ml/gcc-patches
On 30 January 2014 13:48, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This patch wires up the aarch64 backend to use the Cortex-A57 rtx costs
table that is proposed at
http://gcc.gnu.org/ml/gcc-patches/2014-01/msg01954.html
OK if release manager agrees.
/Marcus
On 16 January 2014 18:10, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
The Cortex-A53 and Cortex-A57 cores support the CRC32 and Crypto extensions
to the ARMv8-A architecture. This patch adds that information to their
definitions in aarch64-cores.def.
Both cortex-a53 and cortex-a57
Hi Venkat,
On 22 January 2014 16:57, Venkataramanan Kumar
venkataramanan.ku...@linaro.org wrote:
Hi Marcus,
After we changed the frame growing direction (downwards) in Aarch64,
the back-end now generates stack smashing set and test based on
generic code available in GCC.
But most of the
Symbol classification logic intended to force symbols to memory in large
memory model is triggering in appropriately for all memory models, this
results in an unnecessary level of indirection in generated code.
Regressed aarch64-none-elf, committed.
/Marcus
2014-01-30 Marcus Shawcroft
On 30 January 2014 15:28, Alex Velenko alex.vele...@arm.com wrote:
Hi,
This patch fixes shift right pattern, as it failed on -O0 after shift
right patch. The reason was unnecessary movement of immediate value to
a register due to type mismatch.
Patch is tested not to cause any additional
The definition of _FP_I_TYPE in AArch64 libgcc sfp-machine.h is wrong,
this patch ensures the definition matches that provided by glibc's
AArch64 sfp-machine.h
Committed
/Marcus
2014-01-29 Marcus Shawcroft marcus.shawcr...@arm.com
* config/aarch64/sfp-machine.h (_FP_I_TYPE): Define
Fix a couple of white space nits, committed.
/Marcus
2014-01-29 Marcus Shawcroft marcus.shawcr...@arm.com
* config/aarch64/aarch64.c (aarch64_expand_mov_immediate)
(aarch64_legitimate_address_p, aarch64_class_max_nregs): Adjust
whitespace.diff --git a/gcc/config
On 16 January 2014 12:12, Alex Velenko alex.vele...@arm.com wrote:
This patch implements test cases for following NEON intrinsics:
vdup_lane_f32
vdup_lane_s[8,16]
vdup_lane_s[32,64]
vdup_n_[p,s,u][8,16]
vdup_n_[s,u][32,64]
vdupb_lane_[s,u]8
vduph_lane_[s,u]16
vdupd_lane_[f,s,u]64
On 21 January 2014 10:48, James Greenhalgh james.greenha...@arm.com wrote:
2014-01-21 James Greenhalgh james.greenha...@arm.com
* common/config/aarch64/aarch64-common.c
(aarch64_rewrite_mcpu): Handle multiple names.
* config/aarch64/aarch64.h
On 6 January 2014 11:52, Alex Velenko alex.vele...@arm.com wrote:
Hi,
This patch fixes vector shift by 64 behavior to meet reference
manual expectations. Testcase included to check that expectations
are now met. No regressions found.
Is patch OK?
OK
/Marcus
On 16 January 2014 11:49, Alex Velenko alex.vele...@arm.com wrote:
Hi,
This patch is the first patch in a series of patches fixing Big-Endian
lane numbering. The goal of this series of patches is to make proper
bridge between pure GCC big-endian view on lane numbering and internal
architected
On 16 January 2014 11:49, Alex Velenko alex.vele...@arm.com wrote:
Hi,
This patch changes get_lane intrinsics to provide a correct big-endian
indexing. This fixes numerous BE load and store issues based on getting
correct lane.
Is this good for trunk?
OK
/Marcus
On 16 January 2014 11:50, Alex Velenko alex.vele...@arm.com wrote:
Hi,
This patch by James Greenhalgh fixes by-lane patterns broken by
previous patches.
Regression tested on aarch64-none-elf and aarch64_be-none-elf
with no unexpected issues.
OK?
OK /Marcus
2014/1/16 Alex Velenko alex.vele...@arm.com:
Hi,
In previous BE patches the way lane indexing in lanes is calculated has
been changed. To accommodate the change, arm neon intrinsics had to be
updated.
Is it okay?
OK /Marcus
On 13 January 2014 19:27, Vidya Praveen vidyaprav...@arm.com wrote:
Hello,
This patch adds support to the SISD variants of SCVTF/UCVTF instructions.
This also refactors the existing support for floating point instruction
variants of SCVTF/UCVTF in order to direct the instruction selection
On 6 January 2014 15:36, Marcus Shawcroft marcus.shawcr...@arm.com wrote:
Hi,
This patch defines the AArch64 BE loader name. Corresponding patches for
glibc and binutils have been posted on the relevant lists.
/Marcus
* config/aarch64/aarch64-linux.h (GLIBC_DYNAMIC_LINKER): Expand
On 20 January 2014 17:21, Alex Velenko alex.vele...@arm.com wrote:
Could someone, please, commit it, as I do not have commit rights
Alex
I've committed this for you.
/Marcus
On 20 January 2014 17:33, Alex Velenko alex.vele...@arm.com wrote:
Can someone, please, commit this patch, as I do not have permissions?
Kind regards,
Alex
Committed.
/Marcus
On 15 January 2014 00:09, Andrew Pinski
andrew.pin...@caviumnetworks.com wrote:
ChangeLog:
* config/aarch64/aarch64.c (aarch64_register_move_cost): Correct cost
of moving from/to the STACK_REG register class.
+ /* Moving between GPR and stack cost is the same as GP2GP. */
Don't forget the
On 6 January 2014 12:30, Yufeng Zhang yufeng.zh...@arm.com wrote:
This patch fixes the implementation of vcvtmd_s64_f64 and vcvtpd_s64_f64 in
arm_neon.h to use llfloor and llceil instead, which are ILP32-friendly.
This patch will fix the following test failure in the ILP32 mode:
FAIL:
On 07/01/14 17:02, James Greenhalgh wrote:
Ugh.
Now we have two ASM_SPECs which try to handle -mcpu as input.
One of them just returns the input, the other does the cpu rewriting
we actually want, so we can end up with:
gcc -mcpu=cortex-a57.cortex-a53
Getting passed through to the
Hi,
This patch defines the AArch64 BE loader name. Corresponding patches
for glibc and binutils have been posted on the relevant lists.
/Marcus
* config/aarch64/aarch64-linux.h (GLIBC_DYNAMIC_LINKER): Expand
loader
name using mbig-endian.
(LINUX_TARGET_LINK_SPEC):
On 18 December 2013 12:23, James Greenhalgh james.greenha...@arm.com wrote:
2013-12-18 James Greenhalgh james.greenha...@arm.com
* config/aarch64/aarch64-cores.def: Add new column for
SCHEDULER_IDENT.
* config/aarch64/aarch64-opts.h (AARCH64_CORE): Handle
On 18 December 2013 12:23, James Greenhalgh james.greenha...@arm.com wrote:
2013-12-18 James Greenhalgh james.greenha...@arm.com
* common/config/aarch64/aarch64-common.c
(aarch64_rewrite_selected_cpu): New.
(aarch64_rewrite_mcpu): New.
*
On 18 December 2013 12:23, James Greenhalgh james.greenha...@arm.com wrote:
2013-12-18 James Greenhalgh james.greenha...@arm.com
* config/aarch64/aarch64-cores.def: Add support for
-mcpu=cortex-a57.cortex-a53.
* config/aarch64/aarch64-tune.md: Regenerate.
*
On 18 December 2013 15:28, Tejas Belagod tbela...@arm.com wrote:
2013-12-18 Tejas Belagod tejas.bela...@arm.com
gcc/
* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
* config/aarch64/aarch64-builtins.c
(aarch64_types_binopu_qualifiers,
On 18 December 2013 15:28, Tejas Belagod tbela...@arm.com wrote:
2013-12-18 Tejas Belagod tejas.bela...@arm.com
gcc/
* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
* config/aarch64/aarch64-builtins.c
(aarch64_types_ternopu_qualifiers,
On 18 December 2013 15:28, Tejas Belagod tbela...@arm.com wrote:
2013-12-18 Tejas Belagod tejas.bela...@arm.com
gcc/
* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
* config/aarch64/aarch64-simd.md
(aarch64_crypto_sha256hsha256_opv4si,
On 18 December 2013 15:28, Tejas Belagod tbela...@arm.com wrote:
2013-12-06 Tejas Belagod tejas.bela...@arm.com
gcc/
* config/aarch64/aarch64-builtins.c: Define builtin types for
poly64_t
poly128_t.
* aarch64/aarch64-simd-builtins.def: Update builtins table.
On 10/12/13 20:23, Kugan wrote:
gcc/
+2013-12-11 Kugan Vivekanandarajah kug...@linaro.org
+ * configure.ac: Add check for aarch64 assembler -mabi support.
+ * configure: Regenerate.
+ * config.in: Regenerate.
+ * config/aarch64/aarch64-elf.h (ASM_MABI_SPEC): New
On 6 December 2013 17:35, Tejas Belagod tbela...@arm.com wrote:
2013-12-06 Tejas Belagod tejas.bela...@arm.com
* config/aarch64/aarch64.h (TARGET_CRYPTO): New.
(__ARM_FEATURE_CRYPTO): Define if TARGET_CRYPTO is true.
OK, but don;t apply until the rest of this patch series
On 6 December 2013 17:35, Tejas Belagod tbela...@arm.com wrote:
* config/arm/types.md (neon_mul_d_long, crypto_aes, crypto_sha1_xor,
crypto_sha1_fast, crypto_sha1_slow, crypto_sha256_fast,
crypto_sha256_slow): New.
Looks ok to me, but get an ack from Ramana.
Note that
Same comments as previous patch:
On 6 December 2013 17:36, Tejas Belagod tbela...@arm.com wrote:
testsuite/
* gcc.target/aarch64/sha1.c: New.
Add _1 on the test case file name (see http://gcc.gnu.org/wiki/TestCaseWriting)
+static __inline uint32x4_t
+vsha1cq_u32 (uint32x4_t
On 6 December 2013 17:36, Tejas Belagod tbela...@arm.com wrote:
Hi,
The attached patch implements support for crypto sha256.
Same comments as previous crypto patch.
/Marcus
On 3 December 2013 21:24, Andrew Pinski pins...@gmail.com wrote:
While compiling some programs, GCC and glibc (and newlib)'s definitions of
size_t
were not agreeing and causing format warnings to happen. The simple testcase
for this is:
#include stdio.h
#include stdint.h
int main(void)
Hi,
On 10 December 2013 01:52, Andrew Pinski pins...@gmail.com wrote:
On Mon, Dec 9, 2013 at 12:12 PM, Yufeng Zhang yufeng.zh...@arm.com wrote:
To be more explicit and consistent, the name of the ILP32 loader shall have
'ilp32' instead of '32'. The extension field shall be appended to
Hi
On 3 December 2013 21:24, Andrew Pinski pins...@gmail.com wrote:
+(define_insn trap
+ [(trap_if (const_int 1) (const_int 8))]
+
+ brk #1000)
Please add a type attribute to the pattern. The type attributes are
now shared between arm and aarch64 backends.You should use the
type
On 3 December 2013 21:24, Andrew Pinski pins...@gmail.com wrote:
* config/aarch64/t-aarch64 (MULTILIB_OPTIONS): Fix definition so
that options are conflicting ones.
Looks fine to me, commit it.
/Marcus
On 2 December 2013 23:44, Vladimir Makarov vmaka...@redhat.com wrote:
If somebody with the rights approves, I can commit it tomorrow.
2013-12-02 Vladimir Makarov vmaka...@redhat.com
* config/aarch64/aarch64.c (aarch64_frame_pointer_required): Check
LR_REGNUM.
On 1 December 2013 19:55, Michael Hudson-Doyle
michael.hud...@linaro.org wrote:
Ian Lance Taylor i...@google.com writes:
I've gotten a patch from Michael Hudson-Doyle to set GOARCH to arm64
on an Aarch64 system (https://codereview.appspot.com/34830045/).
Haha, go us.
I've gotten a patch
On 22 November 2013 15:11, James Greenhalgh james.greenha...@arm.com wrote:
gcc/
2013-11-22 James Greenhalgh james.greenha...@arm.com
* config/aarch64/aarch64-builtins.c
(VAR1): Use new naming scheme for aarch64_builtins.
(aarch64_builtin_vectorized_function):
On 22 November 2013 15:11, James Greenhalgh james.greenha...@arm.com wrote:
2013-11-22 James Greenhalgh james.greenha...@arm.com
* config/aarch64/aarch64-builtins.c
(aarch64_type_qualifiers): Add qualifier_poly.
(aarch64_build_scalar_type): Also build Poly types.
On 22 November 2013 15:11, James Greenhalgh james.greenha...@arm.com wrote:
gcc/
2013-11-22 James Greenhalgh james.greenha...@arm.com
* config/aarch64/aarch64-builtins.c
(aarch64_types_bsl_p_qualifiers): New.
(aarch64_types_bsl_s_qualifiers): Likewise.
On 22 November 2013 15:11, James Greenhalgh james.greenha...@arm.com wrote:
2013-11-22 James Greenhalgh james.greenha...@arm.com
* config/aarch64/arm_neon.h (vtbx1_psu8): Emulate behaviour
using other intrinsics.
(vtbx3_psu8): Likewise.
OK /Marcus
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