Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/sync.md: Change LR.aq/SC.rl pairs into
sequentially consistent LR.aqrl/SC.rl pairs.
Signed-off-by: Patrick
Remove references to MEMMODEL_SYNC_* models by converting via
memmodel_base().
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/riscv.cc: Remove MEMMODEL_SYNC_* cases and
sanitize memmodel input with memmodel_base.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv
error: control reaches end of non-void function
Patrick O'Neill (11):
RISC-V: Eliminate SYNC memory models
RISC-V: Enforce Libatomic LR/SC SEQ_CST
RISC-V: Enforce subword atomic LR/SC SEQ_CST
RISC-V: Enforce atomic compare_exchange SEQ_CST
RISC-V: Add AMO release bits
RISC-V
ngs.rst
[2] https://inbox.sourceware.org/gcc-patches/ZFV8pNAstwrF2qBb@andrea/T/#t
[3] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/391
gcc/ChangeLog:
2023-07-17 Patrick O'Neill
* common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as
dependent on 'a'
On 5/16/23 19:47, Palmer Dabbelt wrote:
On Tue, 16 May 2023 19:46:28 PDT (-0700), Vineet Gupta wrote:
On 5/16/23 19:21, Kito Cheng wrote:
Palmer:
For short-term, this should help your internal test:
https://github.com/riscv-collab/riscv-gnu-toolchain/pull/1233
That only helps if using
On 5/15/23 21:32, Jeff Law wrote:
On 5/9/23 10:01, Patrick O'Neill wrote:
Ping.
OK for backporting. Sorry for the delay.
jeff
Committed.
Thanks,
Patrick
Ping.
On 5/3/23 10:19, Patrick O'Neill wrote:
RISC-V has no support for subword atomic operations; code currently
generates libatomic library calls.
This patch changes the default behavior to inline subword atomic calls
(using the same logic as the existing library call).
Behavior can
).
https://github.com/preames/public-notes/blob/master/riscv-tso-mappings.rst
LLVM has implemented this same mapping (Ztso is still behind a
experimental flag in LLVM, so there is *not* a defined ABI for this yet).
https://reviews.llvm.org/D143076
2023-05-04 Patrick O'Neill
gcc/ChangeLog:
-atomics command line flags.
gcc/libgcc/config/riscv/atomic.c has the same logic implemented in asm.
This will need to stay for backwards compatibility and the
-mno-inline-atomics flag.
2023-05-03 Patrick O'Neill
gcc/ChangeLog:
PR target/104338
* config/riscv/riscv-protos.h: Add
:
On 5/2/23 14:34, Patrick O'Neill wrote:
> Is this OK for a backport to GCC-13 as well?
Let me sync with Richi & Jakub. They're the release managers and
this
doesn't fall under the usual rules for things that can be backported.
I would guess that most distros have these patches bac
Is this OK for a backport to GCC-13 as well?
(with the whitespace fixes/changelog revision squashed into it)
Patrick
On 4/26/23 10:01, Patrick O'Neill wrote:
Committed - I had to reformat the changelog so it would push and resolve a
trivial merge conflict in riscv.opt.
---
RISC-V has
heck-function-bodies was pre-approved by Jeff Law.
Committed.
Patrick
---
These tests cover basic cases to ensure the atomic mappings follow the
strengthened Table A.6 mappings that are compatible with Table A.7.
2023-04-27 Patrick O'Neill
gcc/testsuite/ChangeLog:
* gcc.target/riscv
On 4/28/23 11:04, Jeff Law wrote:
On 4/27/23 10:23, Patrick O'Neill wrote:
This change brings atomic loads in line with table A.6 of the ISA
manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/sync.md (atomic_load): Implement atomic
load mapping.
OK.
jeff
On 4/28/23 10:40, Jeff Law wrote:
On 4/27/23 10:22, Patrick O'Neill wrote:
This change makes atomic stores strictly stronger than table A.6 of the
ISA manual. This mapping makes the overall patchset compatible with
table A.7 as well.
2023-04-27 Patrick O'Neill
PR 89835
Should be &qu
On 4/28/23 11:00, Jeff Law wrote:
On 4/27/23 10:22, Patrick O'Neill wrote:
This change brings atomic fences in line with table A.6 of the ISA
manual.
Relax mem_thread_fence according to the memmodel given.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/sync.md
On 4/28/23 10:56, Jeff Law wrote:
On 4/27/23 10:22, Patrick O'Neill wrote:
Introduce the %I and %J flags for setting the .aqrl bits on LR/SC pairs
as needed.
Atomic compare and exchange ops provide success and failure memory
models. C++17 and later place no restrictions on the relative
On 4/28/23 10:34, Jeff Law wrote:
On 4/27/23 10:22, Patrick O'Neill wrote:
This patch sets the relevant .rl bits on amo operations.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_print_operand): change behavior
of %A to include release bits.
Capitalize
On 4/28/23 10:43, Jeff Law wrote:
On 4/27/23 10:22, Patrick O'Neill wrote:
Atomic operations with the appropriate bits set already enfore release
semantics. Remove unnecessary release fences from atomic ops.
This change brings AMO ops in line with table A.6 of the ISA manual.
2023-04-27
On 4/28/23 10:23, Jeff Law wrote:
On 4/27/23 10:22, Patrick O'Neill wrote:
This patch enforces SEQ_CST for atomic compare_exchange ops.
Replace Fence/LR.aq/SC.aq pairs with SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog
On 4/27/23 09:22, Patrick O'Neill wrote:
Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/sync.md: Change LR.aq/SC.rl pairs into
sequentially consistent
On 4/28/23 09:50, Jeff Law wrote:
On 4/27/23 10:22, Patrick O'Neill wrote:
Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
libgcc/ChangeLog:
* config/riscv/atomic.c: Change LR.aq/SC.rl pairs
On 4/28/23 09:23, Jeff Law wrote:
On 4/27/23 10:22, Patrick O'Neill wrote:
Remove references to MEMMODEL_SYNC_* models by converting via
memmodel_base().
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/riscv.cc: Remove MEMMODEL_SYNC_* cases and
sanitize memmodel input
On 5/2/23 08:50, Jeff Law wrote:
On 5/1/23 10:10, Patrick O'Neill wrote:
This patch fixes the changelog to explicitly name the added command line
flags introduced in this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616807.html
2023-05-01 Patrick O'Neill
gcc/ChangeLog
that bridge when/if we get to it.
Patrick
On 4/27/23 09:22, Patrick O'Neill wrote:
This change makes atomic stores strictly stronger than table A.6 of the
ISA manual. This mapping makes the overall patchset compatible with
table A.7 as well.
2023-04-27 Patrick O'Neill
PR 89835
gcc
This patch fixes the changelog to explicitly name the added command line
flags introduced in this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616807.html
2023-05-01 Patrick O'Neill
gcc/ChangeLog:
* ChangeLog: Name the flags added by the patch in the changelog.
Signed
On 4/28/23 10:44, Patrick O'Neill wrote:
On 4/28/23 09:29, Palmer Dabbelt wrote:
On Fri, 28 Apr 2023 09:14:00 PDT (-0700), jeffreya...@gmail.com wrote:
On 4/27/23 10:22, Patrick O'Neill wrote:
...
LLVM mapping notes
LLVM emits corresponding fences for atomic_signal_fence
On 4/28/23 09:29, Palmer Dabbelt wrote:
On Fri, 28 Apr 2023 09:14:00 PDT (-0700), jeffreya...@gmail.com wrote:
On 4/27/23 10:22, Patrick O'Neill wrote:
This patchset aims to make the RISCV atomics implementation stronger
than the recommended mapping present in table A.6 of the ISA manual
This patch sets the relevant .rl bits on amo operations.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_print_operand): change behavior
of %A to include release bits.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/riscv.cc | 7 ++-
1 file
This change brings atomic fences in line with table A.6 of the ISA
manual.
Relax mem_thread_fence according to the memmodel given.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/sync.md (mem_thread_fence_1): Change fence
depending on the given memory model.
Signed
Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/sync.md: Change LR.aq/SC.rl pairs into
sequentially consistent LR.aqrl/SC.rl pairs.
Signed-off-by: Patrick
These tests cover basic cases to ensure the atomic mappings follow the
strengthened Table A.6 mappings that are compatible with Table A.7.
2023-04-27 Patrick O'Neill
gcc/testsuite/ChangeLog:
* gcc.target/riscv/amo-table-a-6-amo-add-1.c: New test.
* gcc.target/riscv/amo-table
the ordering of both given models.
This change brings LR/SC ops in line with table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/riscv-protos.h (riscv_union_memmodels): Expose
riscv_union_memmodels function to sync.md.
* config/riscv/riscv.cc
Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
libgcc/ChangeLog:
* config/riscv/atomic.c: Change LR.aq/SC.rl pairs into
sequentially consistent LR.aqrl/SC.rl pairs.
Signed-off-by: Patrick
Atomic operations with the appropriate bits set already enfore release
semantics. Remove unnecessary release fences from atomic ops.
This change brings AMO ops in line with table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/riscv.cc
This change brings atomic loads in line with table A.6 of the ISA
manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/sync.md (atomic_load): Implement atomic
load mapping.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/sync.md | 28
ally slightly slower.
if (i != 0) {
total_time[j] += getnanos() - start_time;
}
if (sum == 0 || last_sum != 0 && sum != last_sum) {
std::cerr << "result check failed";
exit(1);
}
last_sum = sum;
}
}
for (int i
This change makes atomic stores strictly stronger than table A.6 of the
ISA manual. This mapping makes the overall patchset compatible with
table A.7 as well.
2023-04-27 Patrick O'Neill
PR 89835
gcc/ChangeLog:
* config/riscv/sync.md:
gcc/testsuite/ChangeLog
This patch enforces SEQ_CST for atomic compare_exchange ops.
Replace Fence/LR.aq/SC.aq pairs with SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/sync.md: Change FENCE/LR.aq/SC.aq
Remove references to MEMMODEL_SYNC_* models by converting via
memmodel_base().
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/riscv.cc: Remove MEMMODEL_SYNC_* cases and
sanitize memmodel input with memmodel_base.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv
On 4/26/23 14:21, Patrick O'Neill wrote:
This patch fixes whitespace errors introduced with
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616807.html
2023-04-26 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/riscv.cc: Fix whitespace.
* config/riscv/sync.md: Fix
On 4/26/23 14:45, Bernhard Reutner-Fischer wrote:
On 26 April 2023 23:21:06 CEST, Patrick O'Neill wrote:
This patch fixes whitespace errors introduced with
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616807.html
2023-04-26 Patrick O'Neill
gcc/ChangeLog:
* config/riscv
This patch fixes whitespace errors introduced with
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616807.html
2023-04-26 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/riscv.cc: Fix whitespace.
* config/riscv/sync.md: Fix whitespace.
Signed-off-by: Patrick O'Neill
This patch fixes whitespace errors introduced with
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616807.html
2023-04-26 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/riscv.cc: Fix whitespace.
* config/riscv/sync.md: Fix whitespace.
Signed-off-by: Patrick O'Neill
flag.
2023-04-18 Patrick O'Neill
gcc/ChangeLog:
PR target/104338
* config/riscv/riscv-protos.h: Add helper function stubs.
* config/riscv/riscv.cc: Add helper functions for subword masking.
* config/riscv/riscv.opt: Add command-line flag.
* config/riscv
On 4/26/23 09:08, Palmer Dabbelt wrote:
On Wed, 26 Apr 2023 09:07:05 PDT (-0700), Patrick O'Neill wrote:
2023-04-26 Patrick O'Neill
* MAINTAINERS: Add myself.
Signed-off-by: Patrick O'Neill
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
2023-04-26 Patrick O'Neill
* MAINTAINERS: Add myself.
Signed-off-by: Patrick O'Neill
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d2188c3275a..169418d44f7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -578,6 +578,7 @@ Dorit Nuzman
On 4/24/23 22:52, Jeff Law wrote:
On 4/18/23 15:41, Patrick O'Neill wrote:
RISC-V has no support for subword atomic operations; code currently
generates libatomic library calls.
This patch changes the default behavior to inline subword atomic calls
(using the same logic as the existing
Ping
Also here's the corrected link for Jeff's comments:
https://inbox.sourceware.org/gcc-patches/f965671f-5997-0220-8831-a94e8c68d...@gmail.com/T/#m53e5d46a94868e68693e0d79455ca5343cf275a9
Patrick
On 4/18/23 14:41, Patrick O'Neill wrote:
RISC-V has no support for subword atomic operations
-atomics command line flags.
gcc/libgcc/config/riscv/atomic.c has the same logic implemented in asm.
This will need to stay for backwards compatibility and the
-mno-inline-atomics flag.
2023-04-18 Patrick O'Neill
PR target/104338
* riscv-protos.h: Add helper function stubs
On 4/18/23 09:59, Jeff Law wrote:
On 4/18/23 08:28, Patrick O'Neill wrote:
...
+ rtx addr = force_reg (Pmode, XEXP (mem, 0));
+
+ rtx aligned_addr = gen_reg_rtx (Pmode);
+ emit_move_insn (aligned_addr, gen_rtx_AND (Pmode, addr,
+ gen_int_mode (-4, Pmode)));
So
-atomics command line flags.
gcc/libgcc/config/riscv/atomic.c has the same logic implemented in asm.
This will need to stay for backwards compatibility and the
-mno-inline-atomics flag.
2023-04-18 Patrick O'Neill
PR target/104338
* riscv-protos.h: Add helper function stubs
-atomics command line flags.
gcc/libgcc/config/riscv/atomic.c has the same logic implemented in asm.
This will need to stay for backwards compatibility and the
-mno-inline-atomics flag.
2023-04-18 Patrick O'Neill
PR target/104338
* riscv-protos.h: Add helper function stubs
This change brings atomic fences in line with table A.6 of the ISA
manual.
Relax mem_thread_fence according to the memmodel given.
2023-04-14 Patrick O'Neill
* sync.md (mem_thread_fence_1): Change fence depending on the
given memory model.
Signed-off-by: Patrick O'Neill
the ordering of both given models.
This change brings compare_exchange LR/SC ops in line with table A.6 of the ISA
manual.
2023-04-14 Patrick O'Neill
* riscv.cc: Add function to get the union of two
memmodels in sync.md.
* riscv-protos.h: Likewise.
* sync.md
Atomic operations with the appropriate bits set already enfore release
semantics. Remove unnecessary release fences from atomic ops.
This change brings AMO ops in line with table A.6 of the ISA manual.
2023-04-14 Patrick O'Neill
* riscv.cc (riscv_memmodel_needs_amo_acquire): Change
This change makes atomic stores strictly stronger than table A.6 of the
ISA manual. This mapping makes the overall patchset compatible with
table A.7 as well.
2023-04-14 Patrick O'Neill
PR target/89835
* sync.md (atomic_store): Use simple store instruction in
combination
These tests cover basic cases to ensure the atomic mappings follow the
strengthened Table A.6 mappings that are compatible with Table A.7.
2023-04-14 Patrick O'Neill
* amo-table-a-6-amo-add-1.c: New test.
* amo-table-a-6-amo-add-2.c: Likewise.
* amo-table-a-6-amo-add-3.c
This change brings atomic loads in line with table A.6 of the ISA
manual.
2023-04-14 Patrick O'Neill
* sync.md (atomic_load): Implement atomic load mapping.
Signed-off-by: Patrick O'Neill
---
v3 Changelog:
* Add this patch
---
gcc/config/riscv/sync.md | 27
This patch sets the relevant .rl bits on amo operations.
2023-04-14 Patrick O'Neill
* riscv.cc (riscv_print_operand): change behavior of %A to
include release bits.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/riscv.cc | 7 ++-
1 file changed, 6 insertions(+), 1
This patch enforces SEQ_CST for atomic compare_exchange ops.
Replace Fence/LR.aq/SC.aq pairs with SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-14 Patrick O'Neill
* sync.md: Change FENCE/LR.aq/SC.aq into sequentially
consistent LR.aqrl/SC.rl
Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-14 Patrick O'Neill
* atomic.c: Change LR.aq/SC.rl pairs into sequentially
consistent LR.aqrl/SC.rl pair.
Signed-off-by: Patrick O'Neill
---
libgcc/config/riscv
Remove references to MEMMODEL_SYNC_* models by converting via
memmodel_base().
2023-04-14 Patrick O'Neill
* riscv.cc: Remove MEMMODEL_SYNC_* cases and sanitize memmodel
input with memmodel_base
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/riscv.cc | 11 +++
1
conformance testcases patch assertions and add new
compare-exchange testcases
Patrick O'Neill (10):
RISCV: Eliminate SYNC memory models
RISCV: Enforce Libatomic LR/SC SEQ_CST
RISCV: Enforce atomic compare_exchange SEQ_CST
RISCV: Add AMO release bits
RISCV: Strengthen atomic stores
This change brings atomic fences in line with table A.6 of the ISA
manual.
Relax mem_thread_fence according to the memmodel given.
2023-04-10 Patrick O'Neill
* sync.md (mem_thread_fence_1): Change fence depending on the
given memory model.
Signed-off-by: Patrick O'Neill
These tests cover basic cases to ensure the atomic mappings follow the
strengthened Table A.6 mappings that are compatible with Table A.7.
2023-04-10 Patrick O'Neill
* amo-table-a-6-amo-add-1.c: New test.
* amo-table-a-6-amo-add-2.c: Likewise.
* amo-table-a-6-amo-add-3.c
This change brings atomic loads in line with table A.6 of the ISA
manual.
2023-04-10 Patrick O'Neill
* sync.md (atomic_load): Implement atomic load mapping.
Signed-off-by: Patrick O'Neill
---
v3 Changelog:
* Add this patch
---
gcc/config/riscv/sync.md | 27
This change makes atomic stores strictly stronger than table A.6 of the
ISA manual. This mapping makes the overall patchset compatible with
table A.7 as well.
2023-04-10 Patrick O'Neill
PR target/89835
* sync.md (atomic_store): Use simple store instruction in
combination
This patch enforces SEQ_CST for atomic compare_exchange ops.
Replace Fence/LR.aq/SC.aq pairs with SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-10 Patrick O'Neill
* sync.md: Change FENCE/LR.aq/SC.aq into sequentially
consistent LR.aqrl/SC.rl
the ordering of both given models.
This change brings compare_exchange LR/SC ops in line with table A.6 of the ISA
manual.
2023-04-10 Patrick O'Neill
* riscv.cc: Add function to get the union of two
memmodels in sync.md.
* riscv-protos.h: Likewise.
* sync.md
Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-10 Patrick O'Neill
* atomic.c: Change LR.aq/SC.rl pairs into sequentially
consistent LR.aqrl/SC.rl pair.
Signed-off-by: Patrick O'Neill
---
libgcc/config/riscv
This patch sets the relevant .rl bits on amo operations.
2023-04-10 Patrick O'Neill
* riscv.cc (riscv_print_operand): change behavior of %A to
include release bits.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/riscv.cc | 7 ++-
1 file changed, 6 insertions(+), 1
Atomic operations with the appropriate bits set already enfore release
semantics. Remove unnecessary release fences from atomic ops.
This change brings AMO ops in line with table A.6 of the ISA manual.
2023-04-10 Patrick O'Neill
* riscv.cc (riscv_memmodel_needs_amo_acquire): Change
Remove references to MEMMODEL_SYNC_* models by converting via
memmodel_base().
2023-04-10 Patrick O'Neill
* riscv.cc: Remove MEMMODEL_SYNC_* cases and sanitize memmodel
input with memmodel_base
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/riscv.cc | 11 +++
1
for atomic store introduced in v1 in favor of
if/else
* Rebase/test
Changes for v3:
* Use a trailing fence for atomic stores to be compatible with Table A.7
* Emit an optimized fence r,rw following a SEQ_CST load
* Consolidate tests in [PATCH v3 10/10]
* Add tests for basic A.6 conformance
Patrick
This change brings atomic fences in line with table A.6 of the ISA
manual.
Relax mem_thread_fence according to the memmodel given.
2023-04-05 Patrick O'Neill
* riscv.cc: Expose helper functions to sync.md.
* riscv-protos.h: Likewise.
* sync.md (mem_thread_fence_1
This change brings atomic stores in line with table A.6 of the ISA
manual.
2023-04-05 Patrick O'Neill
PR target/89835
* sync.md (atomic_store): Use simple store instruction in
combination with a fence.
* pr89835.c: New test.
Signed-off-by: Patrick
This patch enforces SEQ_CST for atomic compare_exchange ops.
Replace Fence/LR.aq/SC.aq pairs with strong SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-05 Patrick O'Neill
* sync.md: Change FENCE/LR.aq/SC.aq into sequentially
consistent LR.aqrl
Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-05 Patrick O'Neill
* atomic.c: Change LR.aq/SC.rl pairs into sequentially
consistent LR.aqrl/SC.rl pair.
Signed-off-by: Patrick O'Neill
---
libgcc/config/riscv
the ordering of both given models.
This change brings compare_exchange LR/SC ops in line with table A.6 of the ISA
manual.
2023-04-05 Patrick O'Neill
* riscv.cc: Add function to get the union of two
memmodels in sync.md.
* riscv-protos.h: Likewise.
* sync.md
Atomic operations with the appropriate bits set already enfore release
semantics. Remove unnecessary release fences from atomic ops.
This change brings AMO ops in line with table A.6 of the ISA manual.
2023-04-05 Patrick O'Neill
* riscv.cc (riscv_memmodel_needs_amo_acquire): Change
This patch sets the relevant .rl bits on amo operations.
2023-04-05 Patrick O'Neill
* riscv.cc (riscv_print_operand): change behavior of %A to
include release bits.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/riscv.cc | 7 ++-
1 file changed, 6 insertions(+), 1
Remove references to MEMMODEL_SYNC_* models by converting via
memmodel_base().
2023-04-05 Patrick O'Neill
* atomic.c: Remove MEMMODEL_SYNC_* cases and sanitize memmodel
input with memmodel_base
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/riscv.cc | 11 +++
1
of
if/else
* Rebase/test
* PR target/89835: The RISC-V target uses amoswap.w for relaxed stores
Patrick O'Neill (8):
RISCV: Eliminate SYNC memory models
RISCV: Enforce Libatomic LR/SC SEQ_CST
RISCV: Enforce atomic compare_exchange SEQ_CST
RISCV: Add AMO release bits
RISCV: Eliminate AMO op
The litmus test in this RFC is flawed since it does not assert that the
LR/SC pair succeeds. The condition in the RFC is permitted iff the LR/SC
pair fails. After correcting this flaw [1][2], the litmus test condition
is correctly forbidden.
This correction does not mean that the A.6 mapping is
-atomics command line flags.
gcc/libgcc/config/riscv/atomic.c has the same logic implemented in asm.
This will need to stay for backwards compatibility and the
-mno-inline-atomics flag.
2022-04-19 Patrick O'Neill
PR target/104338
* riscv-protos.h: Add helper function stubs
Hi Pan RZ,
I appreciate the help - that's a good starting point for the macros.
It looks like the file:
gcc/config/nds32/linux.h
interacts with the macro:
#define HAVE_sync_compare_and_swaphi 1
I'm not sure if that's the correct way to do it/if this is defined in a
different way for targets
Hi RZ Pan,
I'll start working on the atomic store/exchange stuff. It shouldn't be
too difficult to add since it will have similar masking logic to
atomic fetch.
Also - I briefly looked and couldn't find the place where those macro's
values for RISC-V are defined in GCC. If anyone can point me
This change brings atomic fences in line with table A.6 of the ISA
manual.
Relax mem_thread_fence according to the memmodel given.
2022-03-31 Patrick O'Neill
* riscv.cc: Expose helper functions to sync.md.
* riscv-protos.h: Likewise.
* sync.md (mem_thread_fence_1
This change brings atomic stores in line with table A.6 of the ISA
manual.
2022-03-31 Patrick O'Neill
PR target/89835
* riscv.cc (atomic_cas_value_strong): Add %I flag for
atomic store fences.
* sync.md (atomic_store): Use simple store instruction
of
both given models.
This change brings LR/SC ops in line with table A.6 of the ISA manual.
2022-03-31 Patrick O'Neill
* riscv.cc: Add functions to get the parent of two
memmodels in sync.md.
* riscv-protos.h: Likewise.
* sync.md (atomic_cas_value_strong
Atomic operations with the appropriate bits set already enfore release
semantics. Remove unnecessary release fences from atomic ops.
This change brings amo ops in line with table A.6 of the ISA manual.
2022-03-31 Patrick O'Neill
* riscv.cc (riscv_memmodel_needs_amo_acquire): Change
This patch sets the relevant .rl bits on amo operations.
2022-03-31 Patrick O'Neill
* riscv.cc (riscv_print_operand): change behavior of %A to
include release bits.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/riscv.cc | 7 ++-
1 file changed, 6 insertions(+), 1
This patch enforces SEQ_CST for atomic compare_exchange ops.
Replace Fence/LR.aq/SC.aq pairs with strong SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2022-03-31 Patrick O'Neill
* sync.md: Change LR.aq/SC.rl pairs into sequentially
consistent LR.aqrl
Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2022-03-31 Patrick O'Neill
* atomic.c: Change LR.aq/SC.rl pairs into sequentially
consistent LR.aqrl/SC.rl pair.
Signed-off-by: Patrick O'Neill
---
libgcc/config/riscv
: LLVM implements fence rw,w + sw
https://godbolt.org/z/n68P7ne1W
That means that LLVM isn't compatible with libatomic's LR.aq/SC.rl.
* PR target/89835: The RISC-V target uses amoswap.w for relaxed stores
Patrick O'Neill (7):
RISCV: Enforce Libatomic LR/SC SEQ_CST
RISCV: Enforce Atomic Compare
-atomics command line flags.
gcc/libgcc/config/riscv/atomic.c has the same logic implemented in asm.
This will need to stay for backwards compatibility and the
-mno-inline-atomics flag.
2022-02-15 Patrick O'Neill
PR target/104338
* riscv.opt: Add command-line flag
may
restrict subsequent RTL pass optimizations.
2. Are there other concerns with implementing source-dest constraints
within the combine pass?
3. Any other thoughts/input you have is welcome!
2022-03-10 Patrick O'Neill
* combine.cc: Add register equality replacement.
* riscv.cc (
may
restrict subsequent RTL pass optimizations.
2. Are there other concerns with implementing source-dest constraints
within the combine pass?
3. Any other thoughts/input you have is welcome!
2022-03-10 Patrick O'Neill
* combine.cc: Add register equality replacement.
* riscv.cc (
:x7=1 /\ 1:x5=0 /\ b=1)
This patch enforces SEQ_CST by setting the .aqrl bits on the LR and .rl
bits on SC ops.
2022-03-07 Patrick O'Neill
PR target/104831
* atomic.c: Change LR.aq/SC.rl pairs into sequentially
consistent LR.aqrl/SC.rl pair.
Signed-off-by: Patrick O'Neill
enforces SEQ_CST by setting the .aqrl bits on the LR and SC
ops.
2022-03-07 Patrick O'Neill
PR target/104831
* atomic.c: Change LR.aq/SC.rl pairs into sequentially
consistent LR.aqrl/SC.aqrl pair.
Signed-off-by: Patrick O'Neill
---
RISCV LRSC-BUGFIX
{
0:x6=a; 0:x8=b; 0
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