Thanks a lot ! I will send V2 for Richi to review.
juzhe.zh...@rivai.ai
From: Andrew Stubbs
Date: 2023-11-07 20:05
To: juzhe.zh...@rivai.ai; gcc-patches
CC: jeffreyalaw; rguenther
Subject: Re: [PATCH] test: Fix FAIL of pr97428.c for RVV
On 07/11/2023 12:03, juzhe.zh...@rivai.ai wrote
It need command line to enable SIMD auto-vectorization (VLS mode in RVV).
It will enable VLS modes auto-vectorization by default if we didn't add RISCV
into vect_cmdline.
So adding it to disable VLS mode vectorization which will fix the FAILs like
other targets.
juzhe.zh...@rivai.ai
SLP" 4 "vect" {
target { vect512 } } } } */
Tested on RVV is OK.
juzhe.zh...@rivai.ai
From: Andrew Stubbs
Date: 2023-11-07 19:44
To: juzhe.zh...@rivai.ai; gcc-patches
CC: jeffreyalaw; rguenther
Subject: Re: [PATCH] test: Fix FAIL of pr97428.c for RVV
On 07/11/2023 11:24, juzhe.zh...@rivai.a
{
target { ! vect512 } } } } */
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-11-07 19:23
To: ams; gcc-patches
CC: jeffreyalaw; rguenther
Subject: Re: Re: [PATCH] test: Fix FAIL of pr97428.c for RVV
Do you mean this ?
/* { dg-final { scan-tree-dump-times &qu
} } } } */
Could you try again ? If it works for you, I am gonna send V2 patch to Richi.
Thank you so much for help.
juzhe.zh...@rivai.ai
From: Andrew Stubbs
Date: 2023-11-07 19:21
To: juzhe.zh...@rivai.ai; gcc-patches
CC: jeffreyalaw; rguenther
Subject: Re: [PATCH] test: Fix FAIL of pr97428
Could you try this ?
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" {
xfail { { ! vect_hw_misalign } || { vect512 } } } } } */
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 4 "vect" {
xfail { ! vect512 }
So, this patch not only fixes RVV FAIL, but also fixes GCN ?
juzhe.zh...@rivai.ai
From: Andrew Stubbs
Date: 2023-11-07 18:09
To: Juzhe-Zhong; gcc-patches@gcc.gnu.org
CC: jeffreya...@gmail.com; rguent...@suse.de
Subject: Re: [PATCH] test: Fix FAIL of pr97428.c for RVV
On 07/11/2023 07:44
able
vect_pack_trunc test.
But I think we don't need it any more. Your fix looks more reasonable.
juzhe.zh...@rivai.ai
LGTM. Thanks for fixing it.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-11-07 15:49
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH] RISC-V: Fixed failed rvv combine testcases
Hi,
This patch fixed the fellowing failed testcases on
Thanks Jeff. Just finish bootstrap +regression passed.
Committed.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-07 11:53
To: Juzhe-Zhong; gcc-patches
CC: rguenther
Subject: Re: [PATCH] test: Fix FAIL of vect-sdiv-pow2-1.c for RVV test: Fix
FAIL of vect-sdiv-pow2-1.c for RVV#
On 11/6
Thanks Jeff. Just finish bootstrap +regression passed.
Committed.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-07 11:49
To: juzhe.zh...@rivai.ai; gcc-patches
CC: rguenther
Subject: Re: [PATCH] test: Fix XPASS of bb-slp-43.c for RVV
On 11/6/23 20:30, juzhe.zh...@rivai.ai wrote
Thanks Jeff. Just finish bootstrap +regression passed.
Committed.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-07 11:52
To: Juzhe-Zhong; gcc-patches
CC: rguenther
Subject: Re: [PATCH] test: Fix FAIL of SAD tests for RVV
On 11/6/23 20:36, Juzhe-Zhong wrote:
> RVV didn't ex
OK
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-11-07 14:41
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP ceil to i/l/ll diff size autovec
From: Pan Li
This patch would like to support the FP below API auto vectorization
with
e the fallbacks to VLS still
>> available when we prefer scalable vectors?
Yes. since it is -fno-vect-cost-model.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-07 11:23
To: Juzhe-Zhong; gcc-patches
CC: rguenther
Subject: Re: [PATCH] test: Fix XPASS of bb-slp-43.c for RVV
On 11/6/23
Ping this simple optimization.
Ok for trunk ?
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-11-06 11:34
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V: Enhance AVL propagation for complicate reduction
auto-vectorization
I notice we
Testcase already existed on the trunk, which is added by Li Pan added recently
when supporting rounding mode autovec.
https://gcc.gnu.org/pipermail/gcc-patches/2023-November/635280.html
math-llrintf-run-0.c passed on RV64 but cause ICE on RV32.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-11-06 16:33
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Adjust FP rint round tests for RV32
From: Pan Li
The FP rint test cases for RV32 need some additional adjust
for types and data
Sorry.
This is middle-end patch, sending to wrong CC lists.
Forget about this patch.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-11-06 14:52
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH V2] VECT: Support mask_len_strided_load
. Operand 0 is the vector to modify,
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-11-03 15:40
To: juzhe.zh...@rivai.ai
CC: gcc-patches; jeffreyalaw; richard.sandiford; Robin Dapp
Subject: Re: Re: [PATCH V2] OPTABS/IFN: Add
mask_len_strided_load/mask_len_strided_store OPTABS/I
ve(tail or unmasked) elements, I
am wondering whether it will cause issues.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-11-03 15:40
To: juzhe.zh...@rivai.ai
CC: gcc-patches; jeffreyalaw; richard.sandiford; Robin Dapp
Subject: Re: Re: [PATCH V2] OPTABS/IFN: Add
mask_len_strided_load/m
Does it look reasonable ? Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-11-02 22:34
To: 钟居哲
CC: gcc-patches; Jeff Law; richard.sandiford; rdapp.gcc
Subject: Re: Re: [PATCH V2] OPTABS/IFN: Add
mask_len_strided_load/mask_len_strided_store OPTABS/IFN
On Thu, 2 Nov 2023, ??? wrote:
&
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-11-03 11:26
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Refactor prefix [I/L/LL] rounding API autovec
iterator
From: Pan Li
Update in v2:
* Add mode size equal check to disable
_vectype))
return false;
+ /* MASK_LEN_GATHER_LOAD dummy mask -1 should always match the
+MASK_VECTYPE. */
+ if (mask_index >= 0 && slp_node && mask_dt == vect_constant_def
+ && !vect_maybe_update_slp_op_vectype (slp_op, mask_vectype))
+
update with more dump information in V2:
https://gcc.gnu.org/pipermail/gcc-patches/2023-November/634950.html
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-11-02 11:06
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V: Fix redundant
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-11-02 08:54
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH] RISC-V: Support vcreate intrinsics for non-tuple types
From: xuli
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/288
gcc/ChangeLog
LGTM.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-11-01 14:35
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH] RISC-V: Support vundefine intrinsics for tuple types
From: xuli
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/288
gcc/ChangeLog
It is new vectorization optimization which needs middle-end patches.
I believe you didn't apply these following 2 patches:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/634812.html
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/634813.html
juzhe.zh...@rivai.ai
Thanks Robin. Address comments on V2.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-31 16:45
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; richard.sandiford; rguenther; jeffreyalaw
Subject: Re: [PATCH] OPTABS/IFN: Add
mask_len_strided_load/mask_len_strided_store OPTABS/IFN
Hi Juzhe
LGTM from my side.
Give kito one more day to review it.
Thanks for support this feature !
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-10-31 17:03
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH v6] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV
intrinsic
From
LGTM.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-31 11:39
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH] RISC-V: Add the missed combine of [u]int64 -> _Float16 and
vcond
Hi,
This patch let the INT64 to FP16 convert split
LGTM as long as you add HONOR_SNANS
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-31 03:26
To: Joseph Myers
CC: rdapp.gcc; gcc-patches; palmer; Kito Cheng; jeffreyalaw;
juzhe.zh...@rivai.ai
Subject: Re: [PATCH] RISC-V: Add vector fmin/fmax expanders.
> Aren't they actually
I notice we have expand_block_move
in riscv-v.cc
Maybe we should move it into riscv-string.cc ?
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-27 15:51
To: Kito Cheng; juzhe.zh...@rivai.ai
CC: rdapp.gcc; gcc-patches; palmer; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Add rawmemchr
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-27 15:38
To: 钟居哲; gcc-patches; palmer; kito.cheng; Jeff Law
CC: rdapp.gcc
Subject: Re: [PATCH] RISC-V: Add rawmemchr expander.
> Suggested adapt codes as follows:
>
> unsigned int element_size = GET_MODE_S
LGTM from my side.
The original integer division COST seems too low.
Hi, Jeff and Kito. Could take a look at this patch ?
Thanks.
juzhe.zh...@rivai.ai
scv-autovec-lmul=dynamic
--param=riscv-autovec-preference=fixed-vlmax
We will need your help of CI. Currently, it's still stage 1 and we are working
on pushing as many optimizations as possible.
Thanks.
juzhe.zh...@rivai.ai
From: Patrick O'Neill
Date: 2023-10-27 02:43
To: Robin
Thanks Richard. Committed.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-10-26 17:56
To: Juzhe-Zhong
CC: gcc-patches; rguenther
Subject: Re: [PATCH V2] DOC: Update COND_LEN document
Juzhe-Zhong writes:
> gcc/ChangeLog:
>
> * doc/md.texi: Adapt COND_LEN pseudo code.
O
Oh. I made a mistake here.
Forget about my last email.
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/634376.html
Here is the V2 address comments as you suggested.
Could you take a look ?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-10-26 17:25
To: Juzhe-Zhong
Hi, Richard.
I tried your pseudo code, but report a warning:
../../../../gcc/gcc/doc/invoke.texi:20243: warning: `.' or `,' must follow
@xref, not )
I have tried several changes, still failed to eliminate this warning.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-10-2
gi?id=111970
I guess they are related to make RVV GCC unstable, so testing various in
different machines.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-26 16:34
To: juzhe.zh...@rivai.ai; Kito.cheng
CC: rdapp.gcc; gcc-patches; kito.cheng; jeffreyalaw; Patrick O'Neill
Subject: Re: [PATCH
Thanks Kito.
I have sent V3 with adapting testcases (2 additional dump FAILs detected by
both Pan Li and Patrick).
No need to review.
I will wait for patrick is ok to ignore popcount FAILs for now then commit it.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-10-26 15:51
To: Juzhe-Zhong
Ls).
I am not familiar with popcount, Robin. Any suggestions?
juzhe.zh...@rivai.ai
From: Li, Pan2
Date: 2023-10-26 15:33
To: juzhe.zh...@rivai.ai; Patrick O'Neill; gcc-patches
CC: kito.cheng; Kito.cheng; jeffreyalaw; Robin Dapp
Subject: RE: Re: [PATCH] RISC-V: Add AVL propagation PAS
er_load_run-11.c
execution test
I use SPIKE works fine. This is my SPIKE configuration
spike \
--isa=rv64gcv_zvfh_zfh \
--misaligned \
${PK_PATH}/pk${xlen} "$@"
juzhe.zh...@rivai.ai
From: Patrick O'Neill
Date: 2023-10-26 09:22
To: juzhe.zh...@rivai.ai; gcc-patches
C
n-1.c execution test
These 2 already exist on the trunk for RV32.
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-11.c
execution test
This FAIL for RV64 is odd. I don't have it. Could you share me the debug log ?
juzhe.zh...@rivai.ai
From: Patrick O'Neill
Date
I'm on other things.
No worry, I won't commit this patch. I will use this patch in my local.
You can fix it when you have time.
I don't know how to fix it since I am really noob about testing.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-25 17:15
To: juzhe
Thanks. Committed with NFC mentioned.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-10-25 17:06
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Export some functions from riscv-vsetvl to riscv-v
LGTM, but plz mention it's NFC in the
Committed.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-10-25 16:35
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V: Change MD attribute avl_type into avl_type_idx[NFC]
Address kito's comments of AVL propagation patch.
C
Hmmm. I am not familiar with Binutils...
I just adapted tests like others in the testsuite make them consistent.
And turns out it can fix the issues...
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-25 16:44
To: juzhe.zh...@rivai.ai; gcc-patches
CC: rdapp.gcc; kito.cheng; Kito.cheng
all of these FAILs
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-25 16:35
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Fix multiple EXCESS test FAILs in RVV testsuite
Hi Juzhe,
I guess that's OK but what's the pr
hese tests like others.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-25 16:35
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Fix multiple EXCESS test FAILs in RVV testsuite
Hi Juzhe,
I guess that's OK but what's the pr
vectype (slp_op, mask_vectype))
+ gcc_unreachable ();
}
As you can see, except MASK_LEN_GATHER_LOAD, other LOADs, I pass 'NULL' same as
before.
Only MASK_LEN_GATHER_LOAD passes '&slp_op'. It works fine for RVV. But I don't
think it's a correct code, we may need
Ok for trunk (You can commit it to the trunk now).
For GCC-13, I'd like to wait for kito's comment.
Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-10-24 15:29
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong
Subject: [PATCH v2] RISC-V: Fix ICE of RVV vget/vset intrinsi
, 3, r0);
tmp = __riscv_vrgather_vv_f32m4(tmp, transpose_indexes(), 16);
r0 = __riscv_vget_v_f32m4_f32m1(tmp, 0);
}
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-10-24 14:22
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong
Subject: RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]
Calling vget
CCing Patrick...
Hi, @Patrick.
Could you apply this patch and trigger your regression CI?
I don't have an environment to test fortran for now (I only test it on C/C++).
Thanks.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-10-24 11:32
To: gcc-patches
CC: kito.cheng; kito.
Fixed on trunk. Pl;z verify it.
juzhe.zh...@rivai.ai
From: Patrick O'Neill
Date: 2023-10-24 09:01
To: juzhe.zh...@rivai.ai; 丁乐华
CC: kito.cheng; Robin Dapp; palmer; jeffreyalaw; gcc-patches
Subject: Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass
IIRC --enable-checking=yes does not
XFLAGS='-O0 -g3'
'CFLAGS_FOR_TARGET=-Os-mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-Os
-mcmodel=medany'
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20231023 (experimental) (g70b66ac9bcb-dirty)
juzhe.zh...@rivai.ai
From: P
LGTM。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-23 17:54
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Remove unnecessary asm check for vec cvt
From: Pan Li
The vsetvl asm check is unnecessary for the vector convert. We
should be
LGTM。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-23 15:53
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Bugfix for merging undef tmp register for trunc
From: Pan Li
For trunc function autovec, there will be one step like below take MU
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-23 10:39
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Remove unnecessary asm check for rounding autovec
From: Pan Li
The vsetvl asm check is unnecessary for the rounding
e" "vmov,vlde,vste")
(set_attr "mode" "")
(set (attr "avl_type") (const_int INVALID_ATTRIBUTE))])
We classify this pattern as vlde/vste/vmov, this pattern doesn't have AVL TYPE
operands.
I realize that when I am adding new pre-RA optimizatio
OK。 LGTM。
juzhe.zh...@rivai.ai
From: Li, Pan2
Date: 2023-10-23 09:42
To: juzhe.zh...@rivai.ai; gcc-patches
CC: Wang, Yanzhang; kito.cheng
Subject: RE: [PATCH v1] RISC-V: Bugfix for merging undefined tmp register in
math
Yes, it is required by the second cvt. The unmasked elements keep the
UNARY_OP_TAMU_FRM_DYN = UNARY_OP_TAMU | FRM_DYN_P,
UNARY_OP_TAMU_FRM_RUP = UNARY_OP_TAMU | FRM_RUP_P,
UNARY_OP_TAMU_FRM_RDN = UNARY_OP_TAMU | FRM_RDN_P,
Are they still necessary ?
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-23 09:26
To: gcc-patches
CC: juzhe.zhong; pan2.li
when preference fixed-vlmax[PR111857]
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vls-mode-6.c
Change all tests name into pr111857-1.c...etc.
juzhe.zh...@rivai.ai
From: Li, Pan2
Date: 2023-10-20 16:43
To: Richard Biener
CC: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang,
ocation,
+"incompatible vector types for invariants\n");
+ return false;
+ }
Bootstrap and Regression on x86 passed.
Thanks.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-10-18 20:36
To: gcc-patches
CC: richard.sandiford; rg
LGTM popcount patch.
juzhe.zh...@rivai.ai
10e20: 02d606d7vadd.vv v13,v13,v12
10e24: fdc5bneza1,10ddc
The vncvt.x.x.w consume e16m1 VTYPE vsetvl but it shouldn't, it should be e8mf2.
This issue is fixed by recent refactor patch.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date:
Forget about this patch.
Commit log code example is wrong, fixed it in V2：
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633420.html
Thanks.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-10-18 18:21
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe
OK
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-17 19:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH V2 14/14] RISC-V: P14: Adjust and add testcases
This sub-patch adjust some testcases and add some bugfix
testcases.
PR
OK
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-17 19:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH V2 13/14] RISC-V: P13: Reorganize functions used to modify RTL
This sub-patch reoriganize the functions that used to modify
OK
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-17 19:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH V2 12/14] RISC-V: P12: Delete riscv-vsetvl.h
This sub-patch delete the unused header file riscv-vsetvl.h
since we no need
LGTM.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-17 19:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH V2 09/14] RISC-V: P9: Cleanup post optimize phase
This sub-patch deletes partial post optimize code(which implement
in the
LGTM.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-17 19:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH V2 08/14] RISC-V: P8: Unified insert and delete of vsetvl insn
into Phase 4
This sub-patch move the modification of rtl
LGTM.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-17 19:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH V2 07/14] RISC-V: P7: Move earliest fuse and lcm code to
pre_vsetvl class
This patch adjust move the code phase 2 and 3
and the output is not used between the start of
- the block and the occurrence. */
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-17 19:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH V2 06/14] RISC-V: P6: Add computing
compute_vsetvl_lcm_data -> compute_lcm_local_properties
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-17 19:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH V2 06/14] RISC-V: P6: Add computing reaching definition data
f
LGTM on algorithm of local analysis.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-17 19:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH V2 05/14] RISC-V: P5: combine phase 1 and 2
This sub-patch combine phase 1 and 2 to use the
() const
+ {
+gcc_assert (!empty_p ());
+return infos.is_empty () ? m_info : infos[infos.length () - 1];
+ }
Change it into get_exit_info (be consistent with mode-switching naming which
also uses LCM).
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-17 19:34
To: gcc-patches
CC: juzhe.zhong; ki
LGMT this patch.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-17 19:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH V2 04/14] RISC-V: P4: move method from pass_vsetvl to pre_vsetvl
This sub-patch remove the method about
delete_list;
All of them add "m_" prefix.
earliest_fusion_worthwhile_p -> successors_probability_equal_p
calculate_dominance_info (CDI_POST_DOMINATORS); > remove
free_dominance_info (CDI_POST_DOMINATORS); ---> remove
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-
Committed.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-10-17 15:30
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V: Enable more tests for dynamic LMUL and bug
fix[PR111832]
Last time, Robin has mentioned that dynamic LMUL will
OK
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-17 17:57
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH] RISC-V: Fix failed testcase when use -cmodel=medany
This little path fix a failed testcase when use -cmodel=medany.
gcc
);
+ gcc_assert (match_p);
+ }
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633209.html
Assert we always match mask_vectype.
Tested on RISC-V and bootstrap && regtest on X86 passed.
Could you confirm it ?
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-10-
ich simplify
COND_LEN_ADD (mask, a, 0, b, len, bias) into LEN_VCOND_MASK (mask, a, b, len,
bias)
I think upstream GCC could consider this approach.
Thanks.
juzhe.zh...@rivai.ai
V2: https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633120.html
with some bug fix.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-10-16 11:57
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V: Fix unexpected big LMUL choosing in
Thanks Robin.
Committed.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-16 17:12
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Use VLS modes if the NITERS is known and smaller
than VLS mode elements.
Hi Juzhe,
this LGTM
OK
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-13 17:49
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Add test for FP llfloor auto vectorization
From: Pan Li
The below FP API are supported already by sharing the same standard
name, as
OK
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-13 16:23
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Add test for FP ifloor auto vectorization
From: Pan Li
The below FP API are supported already by sharing the same standard
name, as
Ok
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-13 16:06
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Add test for FP iceil auto vectorization
From: Pan Li
The below FP API are supported already by sharing the same standard
name, as
OK
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-13 15:20
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Add test for FP llceil auto vectorization
From: Pan Li
The below FP API are supported already by sharing the same standard
name, as
OK
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-13 14:15
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Add test for FP llround auto vectorization
From: Pan Li
The below FP API are supported already by sharing the same standard
name, as
Thanks. Committed.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-10-13 14:01
To: Juzhe-Zhong
CC: GCC Patches; Jeff Law; Richard Biener
Subject: Re: [PATCH] RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV
LGTM
Juzhe-Zhong 於 2023年10月12日 週四 22:45 寫道：
Like ARM SVE and GCN, add RVV
Hi, Richi.
As you suggest, I keep MAK_LEN_GATHER_LOAD (...,-1) format and support SLP for
that in V3:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/632846.html
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-10-12 19:14
To: juzhe.zh...@rivai.ai
CC: gcc-patches
LGTM。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-13 10:22
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Leverage stdint-gcc.h for RVV test cases
From: Pan Li
Leverage stdint-gcc.h for the int64_t types instead of typedef.
Or we may
OK.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-13 09:38
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP lfloor/lfloorf auto vectorization
From: Pan Li
This patch would like to support the FP lfloor/lfloorf auto vectorization
The mask node is NULL since the caller :
if (mask_index >= 0
&& !vect_check_scalar_mask (vinfo, stmt_info, slp_node, mask_index,
&mask, NULL, &mask_dt, &mask_vectype))
return false;
pass NULL to mask_node.
t; ?
But I don't know how to adjust that.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-10-12 17:55
To: juzhe.zh...@rivai.ai
CC: gcc-patches; richard.sandiford
Subject: Re: Re: [PATCH] VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721]
On Thu, 12 Oct 2023, juzhe.zh.
o->ops);
SLP_TREE_DEF_TYPE (invnode) = oprnd_info->first_dt;
oprnd_info->ops = vNULL;
children.safe_push (invnode);
continue;
}
It seems that we handle vect_constant_def same as vect_external_def.
So failed to SLP ?
juzhe.zh...@rivai.ai
ly. */
gcc_assert ((STMT_VINFO_TYPE (SLP_TREE_REPRESENTATIVE (node))
> assert FAILed.
== shift_vec_info_type)
&& j == 1);
continue;
}
Could you help me with that?
juzhe.zh...@rivai.ai
From: Richa
n SLP failed:
Build SLP failed: invalid type of def
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-10-12 17:44
To: 钟居哲
CC: gcc-patches; richard.sandiford
Subject: Re: Re: [PATCH] VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721]
On Thu, 12 Oct 2023, ??? wrote:
> Thanks Richi point
OK
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-12 16:59
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP lround/lroundf auto vectorization
From: Pan Li
This patch would like to support the FP lround/lroundf auto vectorization
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-12 11:28
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP llrint auto vectorization
From: Pan Li
This patch would like to support the FP llrint auto vectorization.
* long long
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