omprehensive than I wrote.
I will send V3 patch with appending your comments.
Thanks you so much!
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-06-05 18:09
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther
Subject: Re: [PATCH V2] VECT: Add SELECT_VL support
"juzhe.zh...@rivai.
LGTM,
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-05 16:20
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subject: [PATCH v2] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic API
From: Pan Li
This patch support the intrinsic API of FP16 ZVFH floating-point
Thanks for catching this.
LGTM.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-06-05 16:18
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; Li Xu
Subject: [PATCH] RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in
vector-iterators.md.
gcc/ChangeLog:
* config/riscv/vector
;vsetvli "?
"vsetvli zero" is the same cost as "vsetvli gpr",
I think for (b), solution 2 and solution 3 should be almost the same.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-06-05 15:57
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther
Subject
ame
+DEF_RVV_WCONVERT_U_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_WCONVERT_U_OPS (vuint32m1_t, 0)
+DEF_RVV_WCONVERT_U_OPS (vuint32m2_t, 0)
+DEF_RVV_WCONVERT_U_OPS (vuint32m4_t, 0)
+DEF_RVV_WCONVERT_U_OPS (vuint32m8_t, 0)
same
Otherwise, LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023
...
vsetvli zero. length <=== insert by VSETLVI PASS
load (pointer IV)
vadd.
...
pointer IV = pointer IV + VF
I want to optimize it into:
...
length = vsetvli (Vf)
... <=== not need to insert vsetvlli.
load (pointer IV)
vadd.
...
pointer IV = pointer IV + length (adjust in bytesize).
T
Hi, I fixed it :
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620462.html
Just feel free to commit it.
Thanks.
juzhe.zh...@rivai.ai
From: Andreas Schwab
Date: 2023-06-02 17:29
To: juzhe.zhong
CC: gcc-patches; kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc
Subject: Re
Oh there is 2 INTVAL (op) == GET_MODE_MASK...
I only change one :)
juzhe.zh...@rivai.ai
From: Andreas Schwab
Date: 2023-06-02 17:29
To: juzhe.zhong
CC: gcc-patches; kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Fix warning in predicated.md
Thanks Richi. I am gonna merge it after Richard's final approve.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-06-02 16:56
To: juzhe.zh...@rivai.ai
CC: gcc-patches; richard.sandiford; linkw
Subject: Re: [PATCH V3] VECT: Change flow of decrement IV
On Thu, 1 Jun 2023, juzhe.zh
Thanks. I am gonna wait for Jeff or Kito final approve.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-02 15:18
To: juzhe.zh...@rivai.ai; gcc-patches
CC: rdapp.gcc; kito.cheng; Kito.cheng; palmer; palmer; jeffreyalaw
Subject: Re: [PATCH V2] RISC-V: Add pseudo vwmul.wv pattern to enhance
o, for such combining, I would like take a another approach to combine this
pattern carefully with accurate register pressure calculation.
However, for this patch.
vext.vf2 + vext.vf2 + vadd ==> vwadd.vv is always better.
I don't think it is possible that using vwadd.vv will be worse.
Thank
Oh. Yes. Thanks for catching this!
Will send V2 soon.
juzhe.zh...@rivai.ai
From: KuanLin Chen
Date: 2023-06-02 09:26
To: gcc-patches; juzhe.zhong
CC: kito.cheng; palmer; rdapp.gcc; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Add _mu C++ overloaded intrinsics for load &&
viota &&a
Hi， forget about this patch.
Just go directly the V2 patch with same title.
That's the last patch I fine tune for integer widening auto-vectorization.
Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-06-01 15:31
To: gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw
Thanks Kewen. Let's wait for Richard and Richi.
juzhe.zh...@rivai.ai
From: Kewen.Lin
Date: 2023-06-01 13:24
To: juzhe.zh...@rivai.ai
CC: richard.sandiford; rguenther; gcc-patches
Subject: Re: [PATCH V3] VECT: Change flow of decrement IV
Hi,
on 2023/6/1 13:00, juzhe.zh...@rivai.ai wrote
LGTM.
We are waiting for FP16 vector to start floating-point auto-vectorizations
Thanks so much.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-01 15:17
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subject: [PATCH] RISC-V: Introduce vfloat16m{f}*_t and their machine
...@rivai.ai
From: Li, Pan2
Date: 2023-06-01 14:57
To: juzhe.zh...@rivai.ai
Subject: FW: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16
in riscv like x86_64 and arm.
FYI.
-Original Message-
From: Gcc-patches On Behalf
Of Jin Ma via Gcc-patches
Sent: Thursday, June 1
This patch is no difference from V2.
Just add PR tree-optimization/109971 as Kewen's suggested.
Already bootstrapped and Regression on X86 no difference.
Ok for trunk ?
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-06-01 12:36
To: gcc-patches
CC: richard.sandiford; rguenther; linkw; Ju
Thanks kewen.
I have send V3 patch. Could you comment that ?
I want to make sure you do support that patch.
Thanks.
juzhe.zh...@rivai.ai
From: Kewen.Lin
Date: 2023-06-01 12:32
To: juzhe.zh...@rivai.ai
CC: richard.sandiford; rguenther; gcc-patches
Subject: Re: [PATCH V2] VECT: Change flow
Bootstrapped and Regression on X86 no surprise different.
Looking forward Kewen's test report for this patch.
Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-31 23:08
To: gcc-patches
CC: richard.sandiford; rguenther; linkw; Ju-Zhe Zhong
Subject: [PATCH V2] VECT: Change flow
Thanks Richard.
Seems that this patch's approach is ok to trunk?
Maybe the only thing we should do is to wait Kewen's testing feedback, am I
right ?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-31 17:01
To: Richard Biener via Gcc-patches
CC: Richard Biener; juzhe.zhong
Oh, it's correct fix. Thanks for catching this.
juzhe.zh...@rivai.ai
From: Kewen.Lin
Date: 2023-05-31 15:38
To: juzhe.zh...@rivai.ai
CC: richard.sandiford; gcc-patches; rguenther
Subject: Re: [PATCH] VECT: Change flow of decrement IV
> Hi, Richi.
>
>>> Note with SEL
an make this patch merged and record the enhancement of SCEV in
bugzilla to see we can improve that in the future.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-05-31 15:38
To: Richard Sandiford
CC: juzhe.zh...@rivai.ai; gcc-patches; linkw
Subject: Re: [PATCH] VECT: Change fl
SS ? "ivopts" PASS?
Is that right that we can enhance analysis when we see the statement as follows:
remain = remain - step and step is coming from a MIN_EXPR (remain, vf).
Then what we need to do?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-31 15:28
To: Richard Biener
CC
w_bug.cgi?id=109971,
Kewen is happy with this patch, turns out this patch can fix power's issue.
So, Let's wait for Richard's comments.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-05-31 14:41
To: juzhe.zh...@rivai.ai
CC: richard.sandiford; gcc-patches; linkw
Subject: Re: Re: [PATC
should extend SCEV/IVOPTS ?
Thanks.
juzhe.zh...@rivai.ai
From: 钟居哲
Date: 2023-05-30 23:05
To: rguenther
CC: richard.sandiford; gcc-patches; linkw
Subject: Re: Re: [PATCH] VECT: Change flow of decrement IV
More information of power's testcase:
Before this patch:
test_npeel_int16_t:
lui a4,%hi(
by SELET_VL).
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-30 19:31
To: juzhe.zhong
CC: gcc-patches; rguenther; linkw
Subject: Re: [PATCH] VECT: Change flow of decrement IV
juzhe.zh...@rivai.ai writes:
> From: Ju-Zhe Zhong
>
> Follow Richi's suggestion, I change curr
his flow is better to power (SCEV）。
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-30 19:31
To: juzhe.zhong
CC: gcc-patches; rguenther; linkw
Subject: Re: [PATCH] VECT: Change flow of decrement IV
juzhe.zh...@rivai.ai writes:
> From: Ju-Zhe Zhong
>
> Follow Richi's s
...@rivai.ai
From: Richard Biener
Date: 2023-05-30 17:50
To: juzhe.zh...@rivai.ai
CC: gcc-patches; richard.sandiford; linkw
Subject: Re: Re: decremnt IV patch create fails on PowerPC
On Tue, 30 May 2023, juzhe.zh...@rivai.ai wrote:
> Ok.
>
> It seems that for this conditions:
>
>
have a try and send a patch.
Thank you so much.
By the way, could you take a look at SELECT_VL patch?
I guess you want to defer it to Richard and I will wait but still I think your
comment is very important.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-05-30 18:00
To: Kewen.Lin
CC:
I am not familiar with SCEV and I am not sure how to do that SCEV can
analysis the decrement IV.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-05-30 17:50
To: juzhe.zh...@rivai.ai
CC: gcc-patches; richard.sandiford; linkw
Subject: Re: Re: decremnt IV patch create fails on PowerPC
O
VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI VNx16HI (VNx32HI
"TARGET_MIN_VLEN > 32") (VNx64HI "TARGET_MIN_VLEN >= 128")
(VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI
"TARGET_MIN_VLEN > 32") (VNx32SI "TA
terns with new VLS modes
(The patterns are same as VLA patterns, just modes are different).
Then emit codegen this VLS RVV patterns.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-05-30 17:29
To: juzhe.zh...@rivai.ai
CC: Robin Dapp; Kito.cheng; gcc-patches; palmer; kito.cheng; jeffreyalaw
))
+LOOP_VINFO_USING_DECREMENTING_IV_P (loop_vinfo) = true;
I should add direct_supportted_p (SELECT_VL...) to this is that right?
I have send SELECT_VL patch. I will add this in next SELECT_VL patch.
Let's wait Richard's more comments.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 20
in SELECT_VL patch).
>> In general I don't have a good overview of which optimizations we gain by
>> such an approach or rather which ones are prevented by VLA altogether?
These patches VLS modes can help for SLP auto-vectorization.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023
ctor-length >= 128 bits.
This is what this patch want to do.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-05-30 15:13
To: Kito Cheng
CC: gcc-patches; palmer; kito.cheng; juzhe.zhong; jeffreyalaw; rdapp.gcc;
pan2.li
Subject: Re: [PATCH] RISC-V: Basic VLS code gen for RISC-V
ctor length=128. However, LLVM can
run on any RVV CPU with vector length >= 128.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-30 15:27
To: Kito Cheng; gcc-patches; palmer; kito.cheng; juzhe.zhong; jeffreyalaw;
pan2.li
CC: rdapp.gcc
Subject: Re: [PATCH] RISC-V: Basic VLS code g
Hi, this patch is bootstrapped PASS.
Ok for trunk ?
Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-25 23:26
To: gcc-patches
CC: richard.sandiford; rguenther; Ju-Zhe Zhong
Subject: [PATCH] VECT: Add SELECT_VL support
From: Ju-Zhe Zhong
This patch is adding SELECT_VL middle
Ok. LGTM as long as you change the patch as I suggested.
Thanks.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-30 14:51
To: juzhe.zh...@rivai.ai
CC: gcc-patches; palmer; kito.cheng; jeffreyalaw; Robin Dapp; pan2.li
Subject: Re: [PATCH] RISC-V: Basic VLS code gen for RISC-V
x5x2SF,VNx6x2SF,VNx7x2SF,VNx8x2SF,\
VNx2x1SF,VNx3x1SF,VNx4x1SF,VNx5x1SF,VNx6x1SF,VNx7x1SF,VNx8x1SF")
(const_int 32)
(eq_attr "mode" "VNx1DI,VNx2DI,VNx4DI,VNx8DI,VNx16DI,\
VNx1DF,VNx2DF,VNx4DF,VNx8DF,VNx16DF,\
VNx2x8DI,VNx2x4DI,VNx3x4DI,VNx4x4DI,\
VNx2x2
Ok for trunk ?
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-29 12:35
To: gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH V2] RISC-V: Add floating-point to integer conversion RVV
auto-vectorization support
From: Juzhe-Zhong
Hi, this patch is same implementation as FMA which has been merged.
Ok for trunk?
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-29 14:53
To: gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH V2] RISC-V: Add RVV FNMA auto
Yes.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-29 12:36
To: juzhe.zh...@rivai.ai
CC: Kito.cheng; Robin Dapp; gcc-patches; jeffreyalaw; palmer; palmer; pan2.li
Subject: Re: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization
Ok, and just make sure this only appear for trunk
This patch is fixing VSETVL PASS bug. Ok for trunk ?
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-26 11:01
To: gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; pan2.li;
Juzhe-Zhong
Subject: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization
This is existing bug in GCC 13. I think I should split into 2 patches.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-29 11:17
To: juzhe.zhong
CC: gcc-patches; kito.cheng; palmer; rdapp.gcc; jeffreyalaw; pan2.li
Subject: Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support
LGTM
Ping。Ok for trunk？
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-26 19:35
To: gcc-patches
CC: kito.cheng; palmer; rdapp.gcc; jeffreyalaw; kito.cheng; pan2.li; Juzhe-Zhong
Subject: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support
From: Juzhe-Zhong
This patch support FMA auto
here are powerpc machines in the GCC compile farm.
It seems that Power is ok with decrement IV since most cases are improved.
I think Richard may help to explain decrement IV more clearly.
Thanks
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-05-26 14:46
To: 钟居哲
CC: gcc-patches;
{
Doing this just like in riscv_vector::preferred_simd_modes
Others let Kito chime in more comments.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-25 17:03
To: gcc-patches; Kito Cheng; palmer; juzhe.zh...@rivai.ai; jeffreyalaw
CC: rdapp.gcc
Subject: [PATCH] RISC-V: Add aut
hould not use RVV_UNOP+2. Instead, you should add an enum call RVV_UNOP_MU
and replace it.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-25 18:08
To: gcc-patches; Kito Cheng; palmer; juzhe.zh...@rivai.ai; jeffreyalaw
CC: rdapp.gcc
Subject: [PATCH v2] RISC-V: Implement autovec
IN_EXPR <_103, 4>;
_104 = _103 - loop_len_66; -> use MIN - loop_len_66
loop_len_65 = MIN_EXPR <_104, 4>;
_105 = _104 - loop_len_65;
loop_len_64 = MIN_EXPR <_105, 4>;
loop_len_63 = _105 - loop_len_64;
Could you help me with this ?
Thanks.
juzhe.zh...@rivai.ai
From: R
factor
>> != rgc->max_nscalars_per_iter * rgc->factor) ?
When I have this in the condition, ICE for fail to generate IR:
loop_len_76 = MIN_EXPR ;
loop_len_66 = MIN_EXPR ;
loop_len_66 = MIN_EXPR ;
loop_len_65 = MIN_EXPR <0, 4>;
_103 = -loop_len_65;
loop_len_64 = MIN_EXPR <_1
.
Wait for kito's final approval.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-25 17:03
To: gcc-patches; Kito Cheng; palmer; juzhe.zh...@rivai.ai; jeffreyalaw
CC: rdapp.gcc
Subject: [PATCH] RISC-V: Add autovec sign/zero extension and truncation.
Hi,
this patch implements the aut
Bootstrap && Regression on X86 passed.
Ok for trunk ?
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-25 10:58
To: gcc-patches
CC: richard.sandiford; rguenther; Ju-Zhe Zhong
Subject: [PATCH V15] VECT: Add decrement IV iteration loop control by variable
amount support
From: Ju-Z
nce optimize it?
I believe the tablegen mechanism in LLVM is well optimized in case of generated
files and functions
so that they won't be affected to much as instructions go up.
Thanks.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-05-25 12:07
To: juzhe.zh...@rivai.ai; kito.cheng
CC: j
>> IIRC LLVM is using the table driven mechanism, so it's less impact on the
>> compilation time when the instruction becomes more and more.
Oh, I see. Could you share more details ?
Maybe we can support this in GCC.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-25 11:53
Thanks.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-05-25 11:43
To: Palmer Dabbelt; Vineet Gupta
CC: kito.cheng; gcc-patches; Kito Cheng; Patrick O'Neill; Jeff Law; macro;
juzhe.zh...@rivai.ai
Subject: Re: RISC-V Bootstrap problems
On 5/24/23 17:13, Palmer Dabbelt wrote:
> On Wed, 24
segment intrinsics are really huge amount.
Even though I have tried to optimized them, still we have the issues..
How about LLVM? Can kito help with this issue?
LLVM has already support full intrinsics for a long time and no issues.
Thanks.
juzhe.zh...@rivai.ai
From: Jeff Law
Date
is a vector bool mode. */
+#define VECTOR_BOOL_MODE_P(MODE) \
+ (GET_MODE_CLASS (MODE) == MODE_VECTOR_BOOL) \
+
Why do you add this? But no use. You should drop this.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-05-25 11:09
To: gcc-patches
CC: juzhe.zhong
egen.
Could you take a look at it:
V15 patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619534.html
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-25 04:05
To: 钟居哲
CC: gcc-patches; rguenther
Subject: Re: [PATCH V14] VECT: Add decrement IV iteration loop control by
variab
>
> From: Juzhe-Zhong
>
> This patch is adding mask logic auto-vectorization.
> define the pattern as "define_insn_and_split" to allow
>don't forgot to update here ^
I notice I missed changeLog here. Is that you want me to fix in the
commit log?
juzhe.zh...
Thanks kito.，
change it into define_insn_and_split send V2 soon.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-24 15:18
To: juzhe.zhong
CC: gcc-patches; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Add RVV mask logic auto-vectorization
Just one comment
Thanks a lot. Part of the comments has already been fixed in V4.
But forget about V4 patch.
Could you continue review V5 patch that I just send ?
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619366.html
with all comments from you have been fixed.
Thanks.
juzhe.zh...@rivai.ai
From
ond[i])
a[i] = b[i]
We need len_mask_load/len_mask_store for such code and I am gonna support them
in the middle-end after this patch is merged.
Both integer && floating (order and unorder) are tested.
built && regression passed.
Ok for trunk?
Thanks.
juzhe.zh...@rivai.ai
Thanks. I fix it by separating VL and normal operand.
V2 patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619356.html
Does it look more reasonable to you?
Just finished the building test && regression.
Thanks.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-
I always finished build up && regression testsuite before I posted the patches.
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-05-24 09:37
To: palmer
CC: gcc-patches; kito.cheng; Kito.cheng; jeffreyalaw; Robin Dapp
Subject: Re: Re: [PATCH V2] RISC-V: Fix magic number of
Yes, I built it and regression has passed.
juzhe.zh...@rivai.ai
From: Palmer Dabbelt
Date: 2023-05-24 09:37
To: juzhe.zhong
CC: gcc-patches; Kito Cheng; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: Re: [PATCH V2] RISC-V: Fix magic number of RVV auto-vectorization
expander
On Tue, 23 May
Yeah. Can I merge it?
juzhe.zh...@rivai.ai
From: Palmer Dabbelt
Date: 2023-05-24 09:32
To: juzhe.zhong
CC: gcc-patches; Kito Cheng; kito.cheng; jeffreyalaw; rdapp.gcc; juzhe.zhong
Subject: Re: [PATCH V2] RISC-V: Fix magic number of RVV auto-vectorization
expander
On Tue, 23 May 2023 18:28:48
Ok. Let's wait for Kito's more comments.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-24 05:07
To: 钟居哲; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; palmer; palmer; Jeff Law;
richard.sandiford
Subject: Re: [PATCH V2] RISC-V: Add RVV comparison autovectorization
>>&
Bootstrap on X86 passed.
Ok for trunk?
Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-22 16:38
To: gcc-patches
CC: richard.sandiford; rguenther; Ju-Zhe Zhong
Subject: [PATCH V12] VECT: Add decrement IV iteration loop control by variable
amount support
From: Ju-Zhe Zhong
gcc
Oh， Thanks.
Let's wait for Kito's final approved.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-23 17:44
To: juzhe.zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw
Subject: Re: [PATCH V2] RISC-V: Refactor the framework of RVV auto-vectorization
Hi
s" looks codes much cleaner.
Hi, kito. Could you take a look at the V2 refactor patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619291.html
This is important for us since we can't post more autovec patches without
refactor patch.
Thanks
juzhe.zh...@rivai.ai
From: Kito Che
will make codes much cleaner.
I dislike the way making the function argument with multiple operand ,like this:
void func(rtx dest, rtx src1, rtx src2, )
If we are doing this, we will need to add helpers forever...
Sending V2 patch soon.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Da
...@rivai.ai
From: Robin Dapp
Date: 2023-05-22 20:26
To: juzhe.zh...@rivai.ai; gcc-patches
CC: rdapp.gcc; Kito.cheng; palmer; jeffreyalaw; richard.sandiford
Subject: Re: [PATCH] RISC-V: Add RVV comparison autovectorization
> I do refactoring since we are going to have many different
> auto-vectori
framework suitable for all of them to simplify the
future work.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-22 20:14
To: juzhe.zh...@rivai.ai; gcc-patches
CC: rdapp.gcc; Kito.cheng; palmer; jeffreyalaw; richard.sandiford
Subject: Re: [PATCH] RISC-V: Add RVV comparison
ue for RVV).
So you could image I will post more middle-end patches for RVV
auto-vectorization in the future.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-05-22 18:12
To: Richard Sandiford; juzhe.zh...@rivai.ai; gcc-patches; rguenther
Subject: Re: [PATCH V11] VECT: Add decrement IV
Yeah, I agree wit kito.
For example, I see you have rename "get_prefer_***" into "get_preferred_**"
I think this NFC patch should be separated patch.
Thanks.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-22 17:05
To: Robin Dapp
CC: 钟居哲; gcc-patches; palmer; Michae
Thanks Robin. Address comment.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-22 16:07
To: juzhe.zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; palmer; jeffreyalaw; Richard Sandiford
Subject: Re: [PATCH] RISC-V: Add RVV comparison autovectorization
Hi Juzhe,
thanks. Some remarks inline
Hi, Richard.
I have rebase to trunk and send the updated patch for "decrement IV support":
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619115.html
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-22 16:00
To: juzhe.zhong
CC: gcc-patches; rguenther; pan2.
pushed,
>> could you post the updated decrementing IV patch?
Sure, I am working on it.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-22 16:00
To: juzhe.zhong
CC: gcc-patches; rguenther; pan2.li
Subject: Re: [PATCH V12] VECT: Fix issue of multiple-rgroup for length is
counting eleme
Hi, Richard and Richi.
This patch bootstrap PASS on X86 and regression no surprise change.
Ok for trunk ?
Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-22 10:08
To: gcc-patches
CC: richard.sandiford; rguenther; pan2.li; Ju-Zhe Zhong
Subject: [PATCH V12] VECT: Fix issue
be abandoned and need to rewrite the whole thing.
Would you mind giving me more information?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-19 18:23
To: juzhe.zhong
CC: gcc-patches; rguenther
Subject: Re: [PATCH V11] VECT: Add decrement IV support in Loop Vectorizer
Thanks
gt; So I think the above part of the patch should go in ahead of the IV changes.
>> But the test should be based on factor rather than
>> TYPE_VECTOR_SUBPARTS.Since the length control measured by bytes instead of
>> bytes is not appropriate for RVV.You mean I can't support R
ate a mask.
>> nit: builder.inner_mode () rather than GET_MODE_INNER (dup_mode)?
They are the same. I can change it using GET_MODE_INNER
>> And I would like have more commnet to explain why we need force_reg here.
Since it will creat ICE.
juzhe.zh...@rivai.ai
From: Kito Cheng
Dat
Oh, I see. Kito has add /* { dg-do run { target { riscv_vector } } } */
But not all RVV tests has use this and I not sure whether it can work.
I think Kito can answer it.
If yes, I think we should add all of them.
Thanks.
juzhe.zh...@rivai.ai
From: Andrew Pinski
Date: 2023-05-17 10:02
does not set up simulator (QEMU
or SPIKE or GEM5) correctly.
For example, did not enable vector extension in simulator, I don't you may try.
Thanks.
juzhe.zh...@rivai.ai
understanding than before.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-16 16:30
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther
Subject: Re: [PATCH V7] VECT: Add decrement IV support in Loop Vectorizer
"juzhe.zh...@rivai.ai" writes:
> Hi, Richard.
>
> RVV inf
tch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618724.html
I think this patch is the reasonable patch now!
Could you take a look at it?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-16 16:30
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther
Subject: Re: [PATC
, I have append my testcases too in this patch too.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-16 16:30
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther
Subject: Re: [PATCH V7] VECT: Add decrement IV support in Loop Vectorizer
"juzhe.zh...@rivai.ai" wr
?
Since I am gonna to put them in RISC-V backend testsuite, I was planning to
post them after this patch is finished and merged into trunk.
What do you suggest ?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-16 16:16
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther
_44; ->remove
+ ...
+ if (ivtmp_46 != 0)
+ goto ; [83.33%]
+ else
+ goto ; [16.67%]
Is it reasonable ? Or you do have better idea for it?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-16 14:57
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-16 14:57
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther
Subject: Re: [PATCH V7] VECT: Add decrement IV support in Loop Vectorizer
"juzhe.zh...@rivai.ai" writes:
>>> The examples are good, but this one made
epending
on the hardward design.
Since our current data reference pointer IV is added by VF (in bytes) by
default.
Then it will be an issue.
So, may be for case 2 like your said, we should not involve undefine behavior
into len_load/len_store,
instead, we should well handle loop control by
ermail/gcc-patches/2023-May/618638.html
which has fixed the comments as you suggested.
Besides, we will going to add more patterns has length included:
len_mask_load/len_mask_stores, len_mask_gather_load/ len_cond...etc
They are all undefine behavior for length larger than the vector length.
Thanks.
Ping。
Is it Ok for trunk ? I have double checked the floating-point instructions
needed FRM.
Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-15 22:53
To: gcc-patches
CC: kito.cheng; palmer; rdapp.gcc; jeffreyalaw; Juzhe-Zhong
Subject: [PATCH V2] RISC-V: Add FRM and rounding
No, ARM SVE is 128bit alignment instead of element align (in aarch64-modes.def).
If you want to tune the alignment, you should add tunning info into
riscv-modes.def
instead of this target hook.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-15 16:58
To: juzhe.zh...@rivai.ai
Address comments.
juzhe.zh...@rivai.ai
From: Bernhard Reutner-Fischer
Date: 2023-05-15 17:22
To: juzhe.zh...@rivai.ai; philipp.tomsich
CC: gcc-patches; kito.cheng; Kito.cheng; palmer; palmer; jeffreyalaw; Robin Dapp
Subject: Re: Re: [PATCH] RISC-V: Add rounding mode operand for fixed-point
I think it is the issue of include file.
Kito may know the better the solution instead of changing stdint.h into
stdint-gcc.h.
Thanks.
juzhe.zh...@rivai.ai
From: Andreas Schwab
Date: 2023-05-15 17:10
To: Robin Dapp via Gcc-patches
CC: juzhe.zh...@rivai.ai; Kito Cheng; Michael Collison
Address comments.
Thanks.
juzhe.zh...@rivai.ai
From: Philipp Tomsich
Date: 2023-05-15 16:21
To: juzhe.zhong
CC: gcc-patches; kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Add rounding mode operand for fixed-point patterns
On Mon, 15 May 2023 at 10
.
And the default behavior in case of alignment which is already in this patch
should not be changed in the future.
Thanks.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-15 16:02
To: Robin Dapp
CC: juzhe.zh...@rivai.ai; gcc-patches; palmer; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Support
Hi, this patch is very interesting patch and I found it's very beneficial after
applying to my downstream RVV GCC.
However, it has been a long time that this patch didn't update.
Is it possible that this patch will be refined and merged into trunk in the
future ?
Thanks
juzhe.zh...@rivai.ai
Thanks. Can you take a look at this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618398.html
This has been fixed 5 rounds. I already fixed it as you suggested
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-15 13:01
To: 钟居哲
CC: GCC Patches; Kito Cheng; Palmer Dabbelt; Palmer
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