On 28 February 2014 10:30, Alex Velenko alex.vele...@arm.com wrote:
Hi Richard,
Thank you for your suggestion. Attached is a patch that includes
implementation of your proposition. A testsuite was run on LE and BE
compilers with no regressions.
Here is the description of the patch:
This
On 25/02/14 18:15, Richard Henderson wrote:
On 02/25/2014 09:02 AM, Alex Velenko wrote:
+(define_expand aarch64_reinterpretdfmode
+ [(match_operand:DF 0 register_operand )
+ (match_operand:VD_RE 1 register_operand )]
+ TARGET_SIMD
+{
+ aarch64_simd_reinterpret (operands[0], operands[1]);
+
Hi,
This patch introduces vreinterpret implementation for 64-bit float
vectors intrinsics and adds testcase for them.
This patch tested on LE or BE with no regressions.
Is this patch ok for stage-1?
Thanks,
Alex
gcc/
2014-02-14 Alex Velenko alex.vele...@arm.com
*
On 02/25/2014 09:02 AM, Alex Velenko wrote:
+(define_expand aarch64_reinterpretdfmode
+ [(match_operand:DF 0 register_operand )
+ (match_operand:VD_RE 1 register_operand )]
+ TARGET_SIMD
+{
+ aarch64_simd_reinterpret (operands[0], operands[1]);
+ DONE;
+})
I believe you want to
