On 2021/12/21 09:32, David Edelsohn wrote:
> Explicit clobbers like this help one side of the issue. For vscr, other
> than the sat bit there is only the nj bit, and we just ignore that :-)
>
>> This patch is okay. Thanks for updating the machine description and
>> for cleaning up the
On 2021/12/21 10:19, Xionghu Luo via Gcc-patches wrote:
>
>
> On 2021/12/21 09:32, David Edelsohn wrote:
>> On Mon, Dec 20, 2021 at 6:55 PM Segher Boessenkool
>> wrote:
>>>
>>> On Mon, Dec 20, 2021 at 11:45:45AM -0500, David Edelsohn wrote:
On Mon, Dec 20, 2021 at 3:24 AM Xionghu Luo
On 2021/12/21 09:32, David Edelsohn wrote:
> On Mon, Dec 20, 2021 at 6:55 PM Segher Boessenkool
> wrote:
>>
>> On Mon, Dec 20, 2021 at 11:45:45AM -0500, David Edelsohn wrote:
>>> On Mon, Dec 20, 2021 at 3:24 AM Xionghu Luo wrote:
These four UNSPECS seems could be replaced with native
On Mon, Dec 20, 2021 at 6:55 PM Segher Boessenkool
wrote:
>
> On Mon, Dec 20, 2021 at 11:45:45AM -0500, David Edelsohn wrote:
> > On Mon, Dec 20, 2021 at 3:24 AM Xionghu Luo wrote:
> > > These four UNSPECS seems could be replaced with native RTL, and why
> > > "(set (reg:SI VSCR_REGNO)
On Mon, Dec 20, 2021 at 11:45:45AM -0500, David Edelsohn wrote:
> On Mon, Dec 20, 2021 at 3:24 AM Xionghu Luo wrote:
> > These four UNSPECS seems could be replaced with native RTL, and why
> > "(set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))"
> > in the RTL pattern, per ISA
On Mon, Dec 20, 2021 at 3:24 AM Xionghu Luo wrote:
>
> These four UNSPECS seems could be replaced with native RTL, and why
> "(set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))"
> in the RTL pattern, per ISA of VSCR bit 127(VECTOR Saturation, SAT):
>
> This bit is sticky;
These four UNSPECS seems could be replaced with native RTL, and why
"(set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))"
in the RTL pattern, per ISA of VSCR bit 127(VECTOR Saturation, SAT):
This bit is sticky; that is, once set to 1 it
remains set to 1 until it is set to 0
