On 9/12/22 01:35, Richard Biener via Gcc-patches wrote:
On Sun, Sep 11, 2022 at 10:51 PM Takayuki 'January June' Suwa via
Gcc-patches wrote:
Hi,
Many RISC machines, as we know, have some restrictions on placing
register-width constants in the source of load-immediate machine instructions,
On Sun, Sep 11, 2022 at 10:51 PM Takayuki 'January June' Suwa via
Gcc-patches wrote:
>
> Hi,
>
> Many RISC machines, as we know, have some restrictions on placing
> register-width constants in the source of load-immediate machine
> instructions, so the target must provide a solution for that in
Hi,
Many RISC machines, as we know, have some restrictions on placing
register-width constants in the source of load-immediate machine instructions,
so the target must provide a solution for that in the machine description.
A naive way would be to solve it early, ie. to replace with read consta
