Re: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

On 6/15/23 03:52, Jin Ma wrote: There are also some problems here, which cannot be simply handled like HF. Many instructions support HF but do not support BF. For example, fadd.h can be used for HF but cannot be used for BF. I guess it may need to be converted to SF first, then fadd.s,

Re: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

> diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md > index 5b70ab20758..6349f032bc8 100644 > --- a/gcc/config/riscv/iterators.md > +++ b/gcc/config/riscv/iterators.md > @@ -61,10 +61,15 @@ > ;; Iterator for hardware-supported floating-point modes. >

Re: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

> diff --git a/gcc/common/config/riscv/riscv-common.cc > b/gcc/common/config/riscv/riscv-common.cc > index ebc1ed7d7e4..2b3ff1f5b8e 100644 > --- a/gcc/common/config/riscv/riscv-common.cc > +++ b/gcc/common/config/riscv/riscv-common.cc > @@ -102,6 +102,8 @@ static const riscv_implied_info_t

Re: FW: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

On 6/1/23 10:56, Palmer Dabbelt wrote: On Thu, 01 Jun 2023 09:48:47 PDT (-0700), jeffreya...@gmail.com wrote: On 6/1/23 01:01, juzhe.zh...@rivai.ai wrote: I plan to implement BF16 vector in GCC but still waiting for ISA ratified since GCC policy doesn't allow un-ratified ISA. Right.  So

Re: FW: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

On Thu, 1 Jun 2023 at 18:49, Jeff Law via Gcc-patches wrote: > > > > On 6/1/23 01:01, juzhe.zh...@rivai.ai wrote: > > I plan to implement BF16 vector in GCC but still waiting for ISA > > ratified since GCC policy doesn't allow un-ratified ISA. > Right. So those specs need to move along further

Re: FW: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

On Thu, 01 Jun 2023 09:48:47 PDT (-0700), jeffreya...@gmail.com wrote: On 6/1/23 01:01, juzhe.zh...@rivai.ai wrote: I plan to implement BF16 vector in GCC but still waiting for ISA ratified since GCC policy doesn't allow un-ratified ISA. Right. So those specs need to move along further

Re: FW: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

On 6/1/23 01:01, juzhe.zh...@rivai.ai wrote: I plan to implement BF16 vector in GCC but still waiting for ISA ratified since GCC policy doesn't allow un-ratified ISA. Right. So those specs need to move along further before we can start integrating code. Currently, we are working on

Re: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

Hi, Ma Jin     1. There are few developments since May in GCC because the spec of Zfbf is constantly changing.     2. We (PLCT lab) will implement Zvfbfmin and Zvfbfwma after Zvfh has been merged in GCC.     3. I will send a patch to support

Re: FW: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

I plan to implement BF16 vector in GCC but still waiting for ISA ratified since GCC policy doesn't allow un-ratified ISA. Currently, we are working on INT8,INT16,INT32,INT64,FP16,FP32,FP64 auto-vectorizaiton. It should very simple BF16 in current vector framework in GCC. Thanks.

[RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

hi, Are there any new developments about Zfb? Are there any plans to implement the Zvfbfmin and Zvfbfwma expansion? I see that Zfb is being reviewed in llvm, maybe we should do the same on gcc. Ref: https://reviews.llvm.org/D151313 https://reviews.llvm.org/D150929

Re: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

Hi ShiHua: Thanks for your contribution to the zfbfmin extension :) General comments: - Add zfbfmin to riscv_ext_version_table - Add test case to verify the -march is accepted. - Add testcase to test argument passing. - Add testcase for operations. - Add testcase for compares. > +(define_insn

[RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

According to https://github.com/riscv/riscv-bfloat16 , zfbfmin extension depends on zfh/zfhmin extension. According to the discussion https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/367, this use __bf16 and use DF16b in riscv_mangle_type like x86. gcc\ChangeLog: *