Hao
cbranchcc4 is a named pattern and requires a specific operand ordering. If
you change *cbranch to cbranchcc4, you must change the order of the
operands, not a quick and dirty hack to *cbranch. Also, you should change
*cbranch_2insn and *creturn as well so that all of the patterns are
On Wed, Nov 16, 2022 at 06:06:19AM -0600, Segher Boessenkool wrote:
> Hi guys,
>
> On Tue, Nov 15, 2022 at 10:04:04PM -0500, David Edelsohn wrote:
> > On Tue, Nov 15, 2022 at 9:32 PM HAO CHEN GUI wrote:
> > > The patch enables have_cbrnachcc4 which is a flag in ifcvt.cc to
> > > indicate if
Hi guys,
On Tue, Nov 15, 2022 at 10:04:04PM -0500, David Edelsohn wrote:
> On Tue, Nov 15, 2022 at 9:32 PM HAO CHEN GUI wrote:
> > The patch enables have_cbrnachcc4 which is a flag in ifcvt.cc to
> > indicate if branch by CC bits is invalid or not. As rs6000 already has
> > "*cbranch" insn
Hi David,
I found definition of the operands in 'cbranch'. The argumnets matters.
I will create a new expand pattern for cbranchcc4. Thanks a lot for your
comments.
'cbranchmode4’
Conditional branch instruction combined with a compare instruction.
Operand 0 is a comparison operator. Operand 1
On Tue, Nov 15, 2022 at 9:32 PM HAO CHEN GUI wrote:
> Hi,
> The patch enables have_cbrnachcc4 which is a flag in ifcvt.cc to
> indicate if branch by CC bits is invalid or not. As rs6000 already has
> "*cbranch" insn which does branching according to CC bits, the flag
> should be enabled and
Hi,
The patch enables have_cbrnachcc4 which is a flag in ifcvt.cc to
indicate if branch by CC bits is invalid or not. As rs6000 already has
"*cbranch" insn which does branching according to CC bits, the flag
should be enabled and relevant branches can be optimized out. The test
case illustrates
