On 6/1/23 10:56, Palmer Dabbelt wrote:
On Thu, 01 Jun 2023 09:48:47 PDT (-0700), jeffreya...@gmail.com wrote:
On 6/1/23 01:01, juzhe.zh...@rivai.ai wrote:
I plan to implement BF16 vector in GCC but still waiting for ISA
ratified since GCC policy doesn't allow un-ratified ISA.
Right. So t
On Thu, 1 Jun 2023 at 18:49, Jeff Law via Gcc-patches
wrote:
>
>
>
> On 6/1/23 01:01, juzhe.zh...@rivai.ai wrote:
> > I plan to implement BF16 vector in GCC but still waiting for ISA
> > ratified since GCC policy doesn't allow un-ratified ISA.
> Right. So those specs need to move along further be
On Thu, 01 Jun 2023 09:48:47 PDT (-0700), jeffreya...@gmail.com wrote:
On 6/1/23 01:01, juzhe.zh...@rivai.ai wrote:
I plan to implement BF16 vector in GCC but still waiting for ISA
ratified since GCC policy doesn't allow un-ratified ISA.
Right. So those specs need to move along further befor
On 6/1/23 01:01, juzhe.zh...@rivai.ai wrote:
I plan to implement BF16 vector in GCC but still waiting for ISA
ratified since GCC policy doesn't allow un-ratified ISA.
Right. So those specs need to move along further before we can start
integrating code.
Currently, we are working on INT8,
he.zh...@rivai.ai
From: Li, Pan2
Date: 2023-06-01 14:57
To: juzhe.zh...@rivai.ai
Subject: FW: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16
in riscv like x86_64 and arm.
FYI.
-Original Message-
From: Gcc-patches On Behalf
Of Jin Ma via Gcc-patches
Sent: Thursday, J
