[PATCH 6/6] RISC-V Port: gcc/testsuite

From: Kito Cheng --- gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C| 2 +- gcc/testsuite/gcc.c-torture/execute/20101011-1.c | 3 +++ gcc/testsuite/gcc.dg/20020312-2.c | 2 ++ gcc/testsuite/gcc.dg/builtin-apply2.c

New Port for RISC-V

We'd like to submit for inclusion in GCC a port for the RISC-V architecture. The port suffices to build a substantial body of software (including Linux and some 2,000 Fedora packages) and passes most of the gcc and g++ test suites; so, while it is doubtlessly not complete, we think it is far

[PATCH/AARCH64] Add scheduler for Thunderx2t99

Hi James, The scheduling patch for vulcan was posted at the following link:- https://gcc.gnu.org/ml/gcc-patches/2016-07/msg01205.html We are working on the patch and addressed the comments for thunderx2t99. >> I tried lowering the repeat expressions as so: Done. >>split off the AdvSIMD/FP

Re: [RFA] [PR tree-optimization/33562] [PATCH 1/4] Byte tracking in DSE - v3

On 01/04/2017 06:22 AM, Richard Biener wrote: Bootstrapped and regression tested on x86_64-linux-gnu. OK for the trunk? New functions in sbitmap.c lack function comments. Bah. Sophomoric on my part. Fixed. bitmap_count_bits fails to guard against GCC_VERSION >= 3400 (the version is

Re: [PATCH C++] Fix PR77489 -- mangling of discriminator >= 10

On 2017.01.11 at 13:03 +0100, Jakub Jelinek wrote: > On Wed, Jan 11, 2017 at 12:48:29PM +0100, Markus Trippelsdorf wrote: > > @@ -1965,7 +1966,11 @@ write_discriminator (const int discriminator) > >if (discriminator > 0) > > { > >write_char ('_'); > > + if

[PATCH 1/6] RISC-V Port: gcc/config/riscv/riscv.c

This is split from the rest of the gcc submission so I can fit this patch on the mailing list's 200KiB limit. --- gcc/config/riscv/riscv.c | 4157 ++ 1 file changed, 4157 insertions(+) create mode 100644 gcc/config/riscv/riscv.c diff --git

[PATCH 3/6] RISC-V Port: libgcc

From: Andrew Waterman --- libgcc/config.host | 12 ++ libgcc/config/riscv/atomic.c | 111 + libgcc/config/riscv/crti.S | 1 + libgcc/config/riscv/crtn.S | 1 + libgcc/config/riscv/div.S | 146

[PATCH 4/6] RISC-V Port: libsanitizer

--- libsanitizer/sanitizer_common/sanitizer_linux.cc | 5 + libsanitizer/sanitizer_common/sanitizer_platform.h | 4 ++-- libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc | 2 +- libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h | 7

[PATCH 5/6] RISC-V Port: libatomic

From: Andrew Waterman --- libatomic/configure.tgt | 1 + 1 file changed, 1 insertion(+) diff --git a/libatomic/configure.tgt b/libatomic/configure.tgt index 6d77c94..b8af3ab 100644 --- a/libatomic/configure.tgt +++ b/libatomic/configure.tgt @@ -37,6 +37,7 @@ case

Re: [RFA][PATCH 3/4] Trim mem* calls in DSE

On 01/04/2017 07:04 AM, Richard Biener wrote: Didn't see a re-post of this one so reviewing the old. Didn't figure mem* trimming was suitable for gcc-7 as I couldn't justify it as a bugfix, so I didn't ping it. I don't think it changed materially. All your comments are still applicable to

[PATCH v2 C++] Fix PR70182 -- missing "on" in mangling of unresolved operators

On 2017.01.11 at 08:21 -0500, Nathan Sidwell wrote: > On 01/11/2017 08:16 AM, Markus Trippelsdorf wrote: > > > --- a/gcc/cp/mangle.c > > +++ b/gcc/cp/mangle.c > > @@ -2813,6 +2813,8 @@ write_template_args (tree args) > > static void > > write_member_name (tree member) > > { > > + if

Re: [RFA] [PR tree-optimization/33562] [PATCH 1/4] Byte tracking in DSE - v3

On 01/04/2017 06:23 AM, Richard Biener wrote: On Wed, Jan 4, 2017 at 2:22 PM, Richard Biener wrote: On Thu, Dec 22, 2016 at 7:26 AM, Jeff Law wrote: This is the first of the 4 part patchkit to address deficiencies in our DSE implementation. This

[PATCH] PR78273 fix count to work with partitioning function

I thought it would be an optimization to use _M_find_tr(k) != end() for the unique associative containers, but as the PR points out the heterogeneous version of count() can find multiple matches even in a unique container. We need to use _M_count_tr(k) to find all matches. PR

Re: Use a specfile that actually allows building programs on NetBSD

On Mon, 9 Jan 2017, co...@sdf.org wrote: 3 month ping, 1 week ping (trying again), etc... Apologies for not getting back to you sooner. Like most operating systems, NetBSD has a libc which contains stuff it needs for most programs to work, and people expect it to be linked without

Re: [ARM] PR 78253 do not resolve weak ref locally

On 01/12/16 14:27, Christophe Lyon wrote: > Hi, > > > On 10 November 2016 at 15:10, Christophe Lyon > wrote: >> On 10 November 2016 at 11:05, Richard Earnshaw >> wrote: >>> On 09/11/16 21:29, Christophe Lyon wrote: Hi,

[arm] Replace command-line option .def files with single definition file

The files arm-cores.def, arm-fpus.def and arm-arches.def are parsed and used in several places and the format is slightly awkward to maintain as they must be parsable in C and by certain scripts. Furthermore, changes to the content that affects every entry is particularly awkward for dealing with

Re: [PATCH] TS_OPTIMIZATION/TS_TARGET_OPTION need no chain/type

On Wed, 11 Jan 2017, Richard Biener wrote: > > LTO bootstrapped on x86_64-unknown-linux-gnu, testing in progress. > > (most "gross" are still TS_LIST having a type and TS_VEC having type > and chain, but that's been hard to fix with the C++ FE in place) Forgot the tree-core.h part.

Re: [PATCH] avoid infinite recursion in maybe_warn_alloc_args_overflow (pr 78775)

On 01/11/2017 02:05 AM, Christophe Lyon wrote: Hi Martin, On 9 January 2017 at 04:14, Jeff Law wrote: On 01/08/2017 02:04 PM, Martin Sebor wrote: On 01/06/2017 09:45 AM, Jeff Law wrote: On 01/05/2017 08:52 PM, Martin Sebor wrote: So Richi asked for removal of the

Re: [patch,avr] PR78883: Implement a dummy scheduler

On 04.01.2017 20:29, Jeff Law wrote: On 01/04/2017 12:18 PM, Segher Boessenkool wrote: On Wed, Jan 04, 2017 at 06:42:23PM +, Richard Sandiford wrote: 1. reload has a bug that no-one really wants to fix (understandable) 2. the bug is triggered by paradoxical subregs of mems 3. those subregs

Re: [PATCH] c++/78771 ICE with inheriting ctor

On 01/04/2017 12:53 AM, Jason Merrill wrote: Hmm, that seems like where the problem is. We shouldn't try to instantiate the inheriting constructor until we've already chosen the base constructor; in the new model the inheriting constructor is just an implementation detail. Oh what fun. This

Re: [PATCH][ARM] [gcc] Add __artificial__ attribute to all NEON intrinsics

On 10/01/17 10:40, Tamar Christina wrote: > Hi all, > > This patch adds the __artificial__ and __gnu_inline__ > attributes to the intrinsics in arm_neon.h so that > costs are associated to the user function during profiling > and during debugging the intrinsics are hidden in trace. > > A similar

Re: [PATCH][AArch64] Improve Cortex-A53 scheduling of int/fp transfers

On 10/01/17 17:18, Wilco Dijkstra wrote: > My previous change to the Cortex-A53 scheduler resulted in a 13% regression > on a > proprietary benchmark. This turned out to be due to non-optimal scheduling > of int > to float conversions. This patch separates int to FP transfers from int to >

Re: [PATCH] PR78255: Make postreload aware of NO_FUNCTION_CSE

On 06/01/17 15:47, Jeff Law wrote: > On 01/06/2017 03:53 AM, Andre Vieira (lists) wrote: >> On 09/12/16 16:31, Bernd Schmidt wrote: >>> On 12/09/2016 05:16 PM, Andre Vieira (lists) wrote: >>> Regardless, 'reload_cse_simplify' would never perform the opposite transformation. It checks

[PATCH] PR78134 fix return types of heterogeneous lookup functions

As with PR 68190 I was returning the _Rb_tree iterator types, not converting them to the container's iterator types. PR libstdc++/78134 * include/bits/stl_map.h (map::lower_bound, map::upper_bound) (map::equal_range): Fix return type of heterogeneous overloads. *

[PATCH][GIMPLE FE] Add parsing of MEM_REFs

The following fills the gap of missed handling of MEM_REF parsing. As we want to represent all info that is on a MEM_REF the existing dumping isn't sufficent so I resorted to __MEM '<' type-name [ ',' number ] '>' '(' [ '(' type-name ')' ] unary-expression [ '+' number ] ')'

Re: [PATCH] PR77528 add default constructors for container adaptors

On 11/01/17 13:25 +, Jonathan Wakely wrote: On 11/01/17 08:04 -0500, Tim Song wrote: On Wed, Jan 11, 2017 at 7:21 AM, Jonathan Wakely wrote: This patch uses the _Enable_default_constructor mixin to properly delete the default constructors. It's a bit cumbersome,

Re: [PATCH] PR77528 add default constructors for container adaptors

On Wed, Jan 11, 2017 at 8:30 AM, Jonathan Wakely wrote: >>> Re the new DMI, my brain compiler says that _Sequence c = _Sequence(); >>> breaks anything with an explicit copy/move constructor pre-C++17, but >>> I also don't think we care about those, right? >> >> >> I dislike

Re: [PATCH] Avoid generating code when writing PCH (PR c++/72813)

OK. On Tue, Jan 10, 2017 at 5:33 PM, Jakub Jelinek wrote: > Hi! > > The comments in both the C and C++ FEs say that after writing PCH file > when --output-pch= is used, we don't want to do anything else and the > routines return to the caller early, especially for C++ FE

Re: [C++ PATCH] Fix ICE on invalid (PR c++/78341)

OK. On Tue, Jan 10, 2017 at 5:35 PM, Jakub Jelinek wrote: > Hi! > > As mentioned in the PR, cp_parser_parse_definitely may fail even when > alignas_expr actually is meaningful, e.g. when the error is due to the > missing closing paren. > > Bootstrapped/regtested on x86_64-linux

Re: [RFC] combine: Handle zero_extend without subreg in change_zero_ext.

On Thu, Jan 05, 2017 at 05:46:51PM +0100, Dominik Vogt wrote: > The attached patch deals with another type of zero_extend that is > not yet handled in change_zero_ext, i.e. (zero_extend > (pseudoreg)), without a "subreg" in between. What do you think? > (Mostly untested yet.) My main question

Go patch committed: add Bfunction to conditional_expression backend method

This patch by Than McIntosh modifies the conditional_expression method in the Backend interface to take a Bfunction. Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed to mainline. Ian 2017-01-11 Than McIntosh * go-gcc.cc (conditional_expression): Add

Re: [PATCH] Enable SGX intrinsics

On Wed, Jan 11, 2017 at 8:59 PM, Koval, Julia wrote: > Hi, I rebased the patch onto latest trunk version and changed specification > according to ICC: > _enclu_u32 (const int __L, size_t *__D) --> _enclu_u32 (const int __L, > size_t __D[]) I have committed the patch

RE: Make MIPS soft-fp preserve NaN payloads for NAN2008

Maciej Rozycki writes: > On Thu, 5 Jan 2017, Matthew Fortune wrote: > > It is true to say that users are discouraged from using 2008-NaN with > > soft-float for pre-R6 architectures simply to avoid further fragmentation > > of software for no real gain. However, for R6

[PATCH, i386]: Increase memory address length only when rip_relative_addr_p returns false.

Hello! Revision 204369 [1] inadvertently reversed the detection of RIP-relative address, resulting in the incorrect calculation of the insn length. Attached patch fixes this problem. 2017-01-11 Uros Bizjak * config/i386/i386.c (memory_address_length): Increase len

Re: [PATCH, rs6000] Add vec_nabs builtin support

Hi Carl, On Mon, Jan 09, 2017 at 10:02:40AM -0800, Carl E. Love wrote: > * config/rs6000/rs6000-c: Add support for built-in functions rs6000-c.c > vector signed char vec_nabs (vector signed char) > vector signed short vec_nabs (vector signed short) > vector signed int

Re: [PATCH] Optimize n + 1 for automatic n array (PR c++/71537)

On 01/10/2017 11:40 PM, Jakub Jelinek wrote: +constexpr bool +foo () +{ + constexpr int n[42] = { 1 }; + constexpr int o = n ? 1 : 0; + constexpr int p = n + 1 ? 1 : 0; + constexpr int q = "abc" + 1 ? 1 : 0; + return p + p + q == 3; +} Not o + p + q ? John.

Re: [PATCH] Optimize n + 1 for automatic n array (PR c++/71537)

On Wed, Jan 11, 2017 at 10:27:23PM +0100, John Tytgat wrote: > On 01/10/2017 11:40 PM, Jakub Jelinek wrote: > > +constexpr bool > > +foo () > > +{ > > + constexpr int n[42] = { 1 }; > > + constexpr int o = n ? 1 : 0; > > + constexpr int p = n + 1 ? 1 : 0; > > + constexpr int q = "abc" + 1 ? 1

C++ PATCH for c++/78337 (ICE with invalid generic lambda)

We instantiate the return type of the lambda outside of the function context, at which point trying to walk from the template instantiation context up to the context of 'f' hits NULL_TREE. So we should handle that. There was also a SFINAE issue whereby we skipped the error in SFINAE context, but

Re: [patch,avr] PR78883: Implement a dummy scheduler

On Wed, Jan 04, 2017 at 12:29:49PM -0700, Jeff Law wrote: > >We should split off a new "SUBREGS_OF_MEM_ALLOWED" from !INSN_SCHEDULING, > >and then probably even default it to false. > That would work for me :-) The question in my mind would be unexpected > fallout at this point in the release

Re: [PATCH] [PR rtl-optimization/65618] Fix MIPS ADA bootstrap failure

On Wed, 11 Jan 2017, James Cowgill wrote: > > From this consideration I gather you have a program source which can be > > used as a test case to reproduce the issue, so can you please file a > > problem report and include the source and a recipe to reproduce it? Is > > this a GCC issue with

Re: [PATCH] [PR rtl-optimization/65618] Fix MIPS ADA bootstrap failure

On Mon, 19 Dec 2016, James Cowgill wrote: > This bug causes the ADA bootstrap comparison failure in a-except.o > because the branch delay scheduling operates slightly differently for > that file if debug information is turned on. This looks like a bug to me -- actual code produced is supposed

Re: [ARM] PR 78253 do not resolve weak ref locally

On 11/01/17 16:14, Christophe Lyon wrote: > On 11 January 2017 at 17:13, Christophe Lyon > wrote: >> On 11 January 2017 at 16:48, Richard Earnshaw (lists) >> wrote: >>> On 01/12/16 14:27, Christophe Lyon wrote: Hi, On 10

[PATCH][AArch64][GCC 6] PR target/79041: Correct -mpc-relative-literal-loads logic in aarch64_classify_symbol

Hi all, In this PR we generated ADRP/ADD instructions with :lo12: relocations on symbols even though -mpc-relative-literal-loads is used. This is due to the confusing double-negative logic of the nopcrelative_literal_loads aarch64 variable and its relation to the

Re: Go patch committed: drop size arguments to hash/equal functions

On Tue, Jan 10, 2017 at 11:45 AM, Rainer Orth wrote: > >> Drop the size arguments for the hash/equal functions stored in type >> descriptors. Types know what size they are. To make this work, >> generate hash/equal functions for types that can use an identity >>

Re: [PATCH v2] Offer suggestions for unrecognized sanitizer options (PR driver/78877)

On Tue, Jan 10, 2017 at 08:47:26PM -0500, David Malcolm wrote: > + /* For -fsanitize-recover= (and not -fno-sanitize-recover=), > + don't offer the non-recoverable options. */ > + if (!sanitizer_opts[i].can_recover && code == OPT_fsanitize_recover_ > + && value) If a

Re: [PATCH] Optimize n + 1 for automatic n array (PR c++/71537)

On Wed, Jan 11, 2017 at 09:31:38AM +0100, Richard Biener wrote: > > Or shall I add the function local address check into maybe_nonzero_address > > instead (return 1 for those)? > > Yes please, and cleanup the other user of maybe_nonzero_address then > (which contains the code you added). Ok,

[committed] Small tweak for the decomp4.C testcase

Hi! When compiling this testcase with trunk clang++, I've noticed the error is different, because there are in fact 2 errors, one that a struct has 2 non-static data members and the decomposition just one identifier, the other that one of those non-static data members is private. I've committed

[PATCH C++] Fix PR77489 -- mangling of discriminator >= 10

Currently gcc mangles symbols wrongly when the discriminator is greater than ten. The fix is straightforward. The demangler now handles both the old and the new correct mangling. Tested on ppc64le. OK for trunk? Thanks. libiberty: PR c++/77489 * cp-demangle.c (d_discriminator):

Re: [PATCH] Enable SGX intrinsics

On Wed, Jan 11, 2017 at 12:40 PM, Koval, Julia wrote: > Ok, fixed it. Can you please commit it for me, cause I don't have rights to > commit? OK, but please send me updated ChangeLogs. Uros. > Thanks, > Julia > > -Original Message- > From: Uros Bizjak

Re: [PATCH C++] Fix PR77489 -- mangling of discriminator >= 10

On Wed, Jan 11, 2017 at 12:48:29PM +0100, Markus Trippelsdorf wrote: > @@ -1965,7 +1966,11 @@ write_discriminator (const int discriminator) >if (discriminator > 0) > { >write_char ('_'); > + if (abi_version_at_least(11) && discriminator - 1 >= 10) > + write_char ('_'); >

Re: [Aarch64][PATCH] Fix gcc.dg/zero_bits_compound-2.c for aarch64

On 06/12/16 00:46, Michael Collison wrote: This patches fixes a regression in gcc.dg/zero_bits_compound-2.c. A recent patch (https://gcc.gnu.org/ml/gcc-patches/2016-11/msg02392.html) to the aarch64 backend improved generation for 'and' instructions with constants. The patch changed the number

Re: [ARM] PR 78253 do not resolve weak ref locally

Ping? On 3 January 2017 at 16:45, Christophe Lyon wrote: > Ping? > > The patch is at https://gcc.gnu.org/ml/gcc-patches/2016-12/msg00078.html > > > On 14 December 2016 at 16:29, Christophe Lyon > wrote: >> Ping^2 ? >> >> As a reminder,

Re: [PATCH 2/2] IPA ICF: make algorithm stable to survive -fcompare-debug

Hi Martin, On 10 January 2017 at 15:40, Martin Liška wrote: > On 01/10/2017 02:56 PM, Richard Biener wrote: >> >> On Mon, Jan 9, 2017 at 4:05 PM, Martin Liška wrote: >>> >>> Second part of the patch does sorting of final congruence classes, it's >>> groups >>>

Re: [hsa] Exclude parallel outlines from hsa_callable_functions_p

Hi, On Fri, Dec 02, 2016 at 02:55:46PM +0100, Martin Jambor wrote: > Hi, > > after the merge of nvidia OpenMP implementation, the normal parallel > outline functions were also marked as "omp declare target" which lead > to them being cloned and compiled to HSA which is not only unnecessary > but

Re: [PATCH 2/2] IPA ICF: make algorithm stable to survive -fcompare-debug

On Wed, Jan 11, 2017 at 11:21:08AM +0100, Christophe Lyon wrote: > Since then, I've noticed that > gcc.dg/tree-ssa/flatten-3.c scan-assembler cycle[123][: \t\n] > now fails on aarch64 and arm targets. It fails on x86_64-linux and i686-linux too. Jakub

Re: [Aarch64][PATCH] Fix gcc.dg/zero_bits_compound-2.c for aarch64

On Wed, Jan 11, 2017 at 09:41:42AM +, Kyrill Tkachov wrote: > > On 06/12/16 00:46, Michael Collison wrote: > >This patches fixes a regression in gcc.dg/zero_bits_compound-2.c. A recent > >patch (https://gcc.gnu.org/ml/gcc-patches/2016-11/msg02392.html) > >to the aarch64 backend improved

Re: [Patch][ARM,AArch64] more poly64 intrinsics and tests

Ping? James, I'm not sure whether your comment was a request for a new version of my patch or just FYI? On 3 January 2017 at 16:47, Christophe Lyon wrote: > Ping? > > > On 14 December 2016 at 23:09, Christophe Lyon > wrote: >> On 14

Re: [v3 PATCH] Reduce the size of variant, it doesn't need an index of type size_t internally.

On 11/01/17 00:19 +0200, Ville Voutilainen wrote: @@ -1086,7 +1099,12 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION { return !this->_M_valid(); } constexpr size_t index() const noexcept - { return this->_M_index; } + { + if (this->_M_index == + typename

Re: [PATCH 2/2] IPA ICF: make algorithm stable to survive -fcompare-debug

On 01/11/2017 11:28 AM, Jakub Jelinek wrote: > On Wed, Jan 11, 2017 at 11:21:08AM +0100, Christophe Lyon wrote: >> Since then, I've noticed that >> gcc.dg/tree-ssa/flatten-3.c scan-assembler cycle[123][: \t\n] >> now fails on aarch64 and arm targets. > > It fails on x86_64-linux and i686-linux

RE: [PATCH] Enable SGX intrinsics

Ok. I fixed the enum formatting and the enums remain internal. -Julia -Original Message- From: Andrew Senkevich [mailto:andrew.n.senkev...@gmail.com] Sent: Tuesday, January 10, 2017 5:48 PM To: Uros Bizjak Cc: Koval, Julia ; GCC Patches

RE: [patch mips/gcc] add build-time and runtime options to disable or set madd.fmt type

Sandra Loosemore writes: > On 01/10/2017 07:24 AM, Yunqiang Su wrote: > > Hi, folks, any idea about this patch? > > I can only comment on the documentation parts. I am reviewing the patch but need to determine if the changes are sufficient and safe to meet the goal.

Re: [PATCH] adding missing LTO to some warning options (PR 78606)

On Tue, 10 Jan 2017, Martin Sebor wrote: > The -Walloca-larger-than, -Wformat-length, and -Wformat-truncation > options do not mention LTO among the supported languages and so are > disabled when -flto is used, causing false negatives. > > The attached patch adds the missing LTO to the three

[PATCH][PR lto/79042] Propagate node->dynamically_initialized bit for varpool node to LTRANS stage.

Hi, as mentioned in PR, LTO doesn't propagate node->dynamically_initialized bit for varpool nodes that leads to ASan fails to detect initialization order fiasco even for trivial example (e.g. from here: https://github.com/google/sanitizers/wiki/AddressSanitizerExampleInitOrderFiasco). This

Re: [PATCH] avoid infinite recursion in maybe_warn_alloc_args_overflow (pr 78775)

Hi Martin, On 9 January 2017 at 04:14, Jeff Law wrote: > On 01/08/2017 02:04 PM, Martin Sebor wrote: >> >> On 01/06/2017 09:45 AM, Jeff Law wrote: >>> >>> On 01/05/2017 08:52 PM, Martin Sebor wrote: >>> >>> So Richi asked for removal of the VR_ANTI_RANGE handling, which

Re: [PATCH] DOn't miscompile programs with -flto -fno-merge-constants (PR middle-end/50199)

On Tue, 10 Jan 2017, Jakub Jelinek wrote: > Hi! > > LTO partitioning can actually take appart uses of STRING_CSTs or other > constants and put those into multiple partitions. When -fno-merge-constants > is in effect, it means those constants aren't merged by the linker and > e.g. following

Re: [PATCH] Optimize n + 1 for automatic n array (PR c++/71537)

On Tue, 10 Jan 2017, Jakub Jelinek wrote: > Hi! > > This patch allows to fold n + 1 != 0 into true for automatic array n. > We already handle it for variables in the symbol table (if not weak), > but automatic vars are never in the symbol table. > > Bootstrapped/regtested on x86_64-linux and

Re: [PATCH] Optimize n + 1 for automatic n array (PR c++/71537)

On Wed, 11 Jan 2017, Jakub Jelinek wrote: > On Wed, Jan 11, 2017 at 09:31:38AM +0100, Richard Biener wrote: > > > Or shall I add the function local address check into maybe_nonzero_address > > > instead (return 1 for those)? > > > > Yes please, and cleanup the other user of maybe_nonzero_address

[PATCH] Fix EVRP not setting ranges on PHI reults

This fixes EVRP to also set range-info/nonnull for PHI results as well as not doing useless work in setting such info for SSA defs we'll propagate out later. Bootstrapped and tested on x86_64-unknown-linux-gnu, installed. Richard. 2017-01-11 Richard Biener *

RE: [PATCH] Enable SGX intrinsics

Here is it. gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_SGX_UNSET, OPTION_MASK_ISA_SGX_SET): New. (ix86_handle_option): Handle OPT_msgx. * config.gcc: Added sgxintrin.h. * config/i386/cpuid.h (bit_SGX): New. * config/i386/driver-i386.c

[PATCH] TS_OPTIMIZATION/TS_TARGET_OPTION need no chain/type

LTO bootstrapped on x86_64-unknown-linux-gnu, testing in progress. (most "gross" are still TS_LIST having a type and TS_VEC having type and chain, but that's been hard to fix with the C++ FE in place) Richard. 2017-01-11 Richard Biener * tree.c

Re: [PATCH C++] Fix PR70182 -- missing "on" in mangling of unresolved operators

On 01/11/2017 08:16 AM, Markus Trippelsdorf wrote: --- a/gcc/cp/mangle.c +++ b/gcc/cp/mangle.c @@ -2813,6 +2813,8 @@ write_template_args (tree args) static void write_member_name (tree member) { + if (abi_version_at_least (11) && IDENTIFIER_OPNAME_P (member)) +write_string ("on"); It

Re: [PATCH] PR77528 add default constructors for container adaptors

On 10/01/17 13:15 -0500, Tim Song wrote: On Tue, Jan 10, 2017 at 12:33 PM, Jonathan Wakely wrote: The standard says that the container adaptors have a constructor with a default argument, which serves as a default constructor. That involves default-constructing the

Re: [PATCH] PR77528 add default constructors for container adaptors

On Wed, Jan 11, 2017 at 7:21 AM, Jonathan Wakely wrote: > This patch uses the _Enable_default_constructor mixin to properly > delete the default constructors. It's a bit cumbersome, because we > have to add an initializer for the base class to every > ctor-initializer-list,

[PATCH C++] Fix PR70182 -- missing "on" in mangling of unresolved operators

The ABI says: ::= [gs] ::= sr ::= srN + E ::= [gs] sr + E ::= ::= on ::= on ::= dn int f (); diff --git a/gcc/testsuite/g++.dg/abi/mangle37.C b/gcc/testsuite/g++.dg/abi/mangle37.C index 691566b384ba..4dd87e84c108 100644 ---

Re: [PATCH] PR77528 add default constructors for container adaptors

On 11/01/17 08:04 -0500, Tim Song wrote: On Wed, Jan 11, 2017 at 7:21 AM, Jonathan Wakely wrote: This patch uses the _Enable_default_constructor mixin to properly delete the default constructors. It's a bit cumbersome, because we have to add an initializer for the base

Re: [v3 PATCH] Reduce the size of variant, it doesn't need an index of type size_t internally.

On 11/01/17 10:29 +, Jonathan Wakely wrote: On 11/01/17 00:19 +0200, Ville Voutilainen wrote: @@ -1086,7 +1099,12 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION { return !this->_M_valid(); } constexpr size_t index() const noexcept - { return this->_M_index; } + { + if

Re: [PATCH 2/2] IPA ICF: make algorithm stable to survive -fcompare-debug

On 01/11/2017 11:28 AM, Jakub Jelinek wrote: > On Wed, Jan 11, 2017 at 11:21:08AM +0100, Christophe Lyon wrote: >> Since then, I've noticed that >> gcc.dg/tree-ssa/flatten-3.c scan-assembler cycle[123][: \t\n] >> now fails on aarch64 and arm targets. > > It fails on x86_64-linux and i686-linux

Re: [LRA] Fix PR rtl-optimization/79032

On Tue, Jan 10, 2017 at 9:31 PM, Eric Botcazou wrote: > Hi, > > LRA generates an unaligned memory access for 32-bit SPARC on the attached > testcase when it is compiled with optimization. It's again the business of > paradoxical subregs of memory dealt with by

Re: [PATCH] Enable SGX intrinsics

On Wed, Jan 11, 2017 at 11:31 AM, Koval, Julia wrote: > Ok. I fixed the enum formatting and the enums remain internal. @@ -7023,7 +7029,6 @@ ix86_can_inline_p (tree caller, tree callee) bool ret = false; tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);

Re: [PATCH 2/2] IPA ICF: make algorithm stable to survive -fcompare-debug

On Wed, Jan 11, 2017 at 11:48 AM, Martin Liška wrote: > On 01/11/2017 11:28 AM, Jakub Jelinek wrote: >> On Wed, Jan 11, 2017 at 11:21:08AM +0100, Christophe Lyon wrote: >>> Since then, I've noticed that >>> gcc.dg/tree-ssa/flatten-3.c scan-assembler cycle[123][: \t\n] >>> now

Re: [PATCH][PR lto/79042] Propagate node->dynamically_initialized bit for varpool node to LTRANS stage.

On 11/01/17 14:17, Richard Biener wrote: On Wed, Jan 11, 2017 at 10:00 AM, Maxim Ostapenko wrote: Hi, as mentioned in PR, LTO doesn't propagate node->dynamically_initialized bit for varpool nodes that leads to ASan fails to detect initialization order fiasco even for

RE: [PATCH] Enable SGX intrinsics

Ok, fixed it. Can you please commit it for me, cause I don't have rights to commit? Thanks, Julia -Original Message- From: Uros Bizjak [mailto:ubiz...@gmail.com] Sent: Wednesday, January 11, 2017 12:11 PM To: Koval, Julia Cc: Andrew Senkevich

Re: [PATCH] Enable SGX intrinsics

On Wed, Jan 11, 2017 at 10:31:33AM +, Koval, Julia wrote: > Ok. I fixed the enum formatting and the enums remain internal. No further objections from me, if Uros acks it, check it in. > > Sure. Plus it depends on if users of the APIs should just write the > > operands on their own as

Re: [PATCH][PR tree-optimization/78856] Invalidate cached iteration information when threading across multiple loop headers

On Tue, Jan 10, 2017 at 8:16 PM, Jeff Law wrote: > On 01/04/2017 05:25 AM, Richard Biener wrote: >> >> On Wed, Jan 4, 2017 at 6:31 AM, Jeff Law wrote: >>> >>> >>> So as noted in the BZ comments the jump threading code has code that >>> detects >>> when a jump

Re: [PATCH] avoid infinite recursion in maybe_warn_alloc_args_overflow (pr 78775)

On Jan 11 2017, Christophe Lyon wrote: > The new test (gcc.dg/pr78973.c) fails on arm targets (there's no warning). Also fails on m68k. > In addition, I have noticed a new failure: > gcc.dg/attr-alloc_size-4.c (test for warnings, line 140) > on target

Re: [PATCH][PR lto/79042] Propagate node->dynamically_initialized bit for varpool node to LTRANS stage.

On Wed, Jan 11, 2017 at 10:00 AM, Maxim Ostapenko wrote: > Hi, > > as mentioned in PR, LTO doesn't propagate node->dynamically_initialized bit > for varpool nodes that leads to ASan fails to detect initialization order > fiasco even for trivial example (e.g. from here: >

[PATCH] Fix parts of PR79052 (gimplefe)

The following hopefully fixes the gimplefe ubsan bootstrap warnings. Bootstrapped / tested on x86_64-unknown-linux-gnu, applied. Richard. 2017-01-11 Richard Biener PR bootstrap/79052 * gimple-parser.c (c_parser_gimple_switch_stmt): Add missing

Re: C++ PATCH for C++17 NB comment FI20 (parenthesized initialization with decomposition)

On Tue, Jan 10, 2017 at 02:03:14PM -0500, Jason Merrill wrote: > The FI20 comment on the decomposition declarations proposal complained > that the syntax unnecessarily excluded parenthesized initialization. > This patch implements the resolution. > > Tested x86_64-pc-linux-gnu, applying to trunk.

Re: [PATCH][PR lto/79042] Propagate node->dynamically_initialized bit for varpool node to LTRANS stage.

On Wed, Jan 11, 2017 at 12:21 PM, Maxim Ostapenko wrote: > On 11/01/17 14:17, Richard Biener wrote: >> >> On Wed, Jan 11, 2017 at 10:00 AM, Maxim Ostapenko >> wrote: >>> >>> Hi, >>> >>> as mentioned in PR, LTO doesn't propagate

Re: [patch,avr] PR78883: Implement a dummy scheduler

Segher Boessenkool schrieb: On Wed, Jan 04, 2017 at 12:29:49PM -0700, Jeff Law wrote: We should split off a new "SUBREGS_OF_MEM_ALLOWED" from !INSN_SCHEDULING, and then probably even default it to false. That would work for me :-) The question in my mind would be unexpected fallout at this

RE: Make MIPS soft-fp preserve NaN payloads for NAN2008

On Thu, 5 Jan 2017, Matthew Fortune wrote: > > > AFAIR we deliberately decided not to define a 2008-NaN soft-float > > > ABI, and chose to require all soft-float binaries to use the legacy > > encoding. > > > > Soft-float and 2008-NaN are naturally completely orthogonal and the > > combination

[C++ PATCH] Overload pushing cleanup

In fixing 77812, a name lookup bug, I got confused by the overload creation code, which seemed a bit complex. This simplifies it by clearly separating the optional wrapping of a single decl from the subsequent prepending of the new decl. applied to trunk nathan -- Nathan Sidwell 2017-01-11

RE: [PATCH] Enable SGX intrinsics

Hi, I rebased the patch onto latest trunk version and changed specification according to ICC: _enclu_u32 (const int __L, size_t *__D) --> _enclu_u32 (const int __L, size_t __D[]) The Changelogs remained the same: gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_SGX_UNSET,

Re: [PATCH] MIPS: Fix generation of DIV.G and MOD.G for Loongson targets.

On Mon, 9 Jan 2017, Toma Tabacu wrote: > The expand_DIVMOD function, introduced in r241660, will pick the divmod4 > (or the udivmod4) pattern when it checks for the presence of hardware > div/mod instructions, which results in the generation of the old DIV > instruction. > > Unfortunately, this

Build failure cris-elf, gcc-5 backport of PR rtl-optimization/78255 fix, gcc/postreload.c:reload_cse_simplify

For cris-elf on the gcc-5-branch at r244321: g++ -c -g -O2 -DIN_GCC -DCROSS_DIRECTORY_STRUCTURE -fno-exceptions -fno-rtti -fasynchronous-unwind-tables -W -Wall -Wno-narrowing -Wwrite-strings -Wcast-qual -Wmissing-format-attribute -Woverloaded-virtual -pedantic -Wno-long-long

Re: [PATCH] combine ignoring a check

On Tue, Jan 10, 2017 at 09:12:38AM -0500, Nathan Sidwell wrote: > Segher commented on IRC that a single loop would be slower. I disagree. Slower *and less readable*, which is the main point. Oh well. > - /* Make sure this PARALLEL is not an asm. We do not allow combining > +

RE: Make MIPS soft-fp preserve NaN payloads for NAN2008

On Wed, 11 Jan 2017, Maciej W. Rozycki wrote: > > > In any case, the soft-fp change is relevant in the hard-float case as > > > well, to make software TFmode behave consistently with hardware SFmode > > > and DFmode regarding NaN payload preservation. > > Is mixing TFmode, DFmode and SFmode

Re: [PATCH, rs6000] Fix PR79044 (ICE in swap optimization)

On Tue, Jan 10, 2017 at 02:18:38PM -0600, Bill Schmidt wrote: > PR79044 reports a situation where swap optimization ICEs in GCC 6 and in > trunk. The > problem is that swap optimization doesn't properly recognize that > element-reversing > loads and stores (e.g., lxvw4x) cannot be treated as

Re: [PATCH, gcc, wwwdocs] Document upcoming Qualcomm Falkor processor support

On Wed, Jan 11, 2017 at 8:29 AM, Richard Earnshaw (lists) wrote: > On 06/01/17 12:11, Siddhesh Poyarekar wrote: >> Hi, >> >> This patch documents the newly added flag in gcc 7 for the upcoming >> Qualcomm Falkor processor core. >> >> Siddhesh >> >> Index:

Re: [PATCH] PR 78534 Change character length from int to size_t

On Sun, Jan 8, 2017 at 4:29 PM, Dominique d'Humières wrote: >> r244027 reverts r244011. Sorry for the breakage. It seems to affect >> all i686 as well in addition to power, maybe all 32-bit hosts. > > For the record, I see the following failures with an instrumented r244026

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