RE: [patch] tweak gcc.target/mips/msa.c options

Hi Sandra, > The testcase gcc.target/mips/msa.c gives dozens of FAILs if it's tested > with a GCC configured to default to -fno-common, because of patterns > like > > /* { dg-final { scan-assembler-times "\t.comm\tv16i8_\\d+,16,16" 3 } } > */ > > Seems like the simplest solution is to force

Re: [PATCH][AArch64] Set default sched pressure algorithm

On Fri, Nov 3, 2017 at 6:38 AM, Andrew Pinski wrote: > On Fri, Nov 3, 2017 at 12:11 AM, Wilco Dijkstra > wrote: >> The Arm backend sets the default sched-pressure algorithm to >> SCHED_PRESSURE_MODEL. Benchmarking on AArch64 shows this >> speeds up

[patch] Do not report non-executed blocks in Ada coverage

Hi, as explained in https://gcc.gnu.org/ml/gcc-patches/2017-11/msg00105.html we don't (necessarily) want to report non-executed blocks in Ada. The couple of attached patches prevent this from happening by detecting whether we are dealing with an Ada file; the first variant is optimal, the

Re: [PATCH] Make inlining consistent in LTO and non-LTO mode (PR target/71991).

Hi. Honza can you please take a look at this, because Richi installed patch that I originally suggested and you were not happy about: r251333. Thanks, Martin

Re: [PATCH] New option saphira for Qualcomm server part

On 3 November 2017 at 15:50, Richard Earnshaw wrote: >> 2017-10-27 Siddhesh Poyarekar >> Jim Wilson >> >> gcc/ >> * config/aarch64/aarch64-cores.def (saphira): New. >>

Re: [PATCH][AArch64] Set default sched pressure algorithm

Richard Biener wrote: > On Fri, Nov 3, 2017 at 6:38 AM, Andrew Pinski wrote: > > On Fri, Nov 3, 2017 at 12:11 AM, Wilco Dijkstra > > wrote: > >> The Arm backend sets the default sched-pressure algorithm to > >> SCHED_PRESSURE_MODEL.  Benchmarking on

Re: [PATCH] Initialize variable in order to survive PGO bootstrap.

On Fri, Nov 3, 2017 at 9:52 AM, Martin Liška wrote: > Hi. > > This is oneliner that fixes PGO bootstrap. I've discussed that with Richi and > the core is correct. > However we probably don't have an attribute that will ignore the warning? I think wide_int res = res; might do

Re: [PATCH] RFC: add taxonomy IDs to diagnostics (CERT C, CWE, etc)

On Thu, Nov 2, 2017 at 10:28 PM, Martin Sebor wrote: > On 11/02/2017 02:51 PM, David Malcolm wrote: >> >> We currently identify our diagnostics via command-line options, and by >> the text of the option itself. >> >> This patch adds a way to supply metadata with a diagnostic,

Re: PR82808

On Fri, Nov 3, 2017 at 6:15 AM, Prathamesh Kulkarni wrote: > Hi Martin, > As mentioned in PR, the issue here for propagating value of 'm' from > f_c1 to foo() is that the jump function operation is FLOAT_EXPR, and > the type of input param 'm' is int, so

Re: [PATCH] Simplify _Node_insert_return to avoid including

On 03/11/17 09:29 +, Jonathan Wakely wrote: On 02/11/17 18:00 -0400, Tim Song wrote: Um, why are those member get's there at all (and with an index mapping that doesn't agree with the member order)? [container.insert.return] says that "It has no base classes or members other than those

Re: [RFA][PATCH] Refactor duplicated code used by various dom walkers

On Fri, Nov 3, 2017 at 4:49 AM, Jeff Law wrote: > > > > Several passes which perform dominator walks want to identify when block has > a single incoming edge, ignoring loop backedges. > > I'm aware of 4 implementations of this code. 3 of the 4 are identical in > function. The

RE: [PATCH 5/6] [ARC] Add 'uncached' attribute.

> > I see no documentation here. > Ups, forgot this one :) Please find it attached. I'll merge it into the final patch when everything is approved. Thanks, Claudiu 0001-ARC-DOC-Add-uncached-documentation.patch Description: 0001-ARC-DOC-Add-uncached-documentation.patch

[PATCH PR82726][1/2]Revert previous fixes for PR70754 and PR79663

Hi, When fixing PR70754, I thought the issue only happens for ZERO-length chains. Well, that's apparently not true with PR82726. The whole story is, with chain combination/re-association, new stmts may be created/inserted at position not dominating following uses. This happens in two scenarios:

[PATCH PR82726/PR70754][2/2]New fix by finding correct root reference in combined chains

Hi, As described in message of previous patch: This patch set fixes both PRs in the opposite way: Instead of find dominance insertion position for root reference, we resort zero-distance references of combined chain by their position information so that new root reference must dominate others.

Re: Generalize -(-X) a little

On Fri, Nov 3, 2017 at 2:06 AM, Marc Glisse wrote: > On Thu, 2 Nov 2017, Richard Biener wrote: > >> You can handle floats as followup but some testcases that shouldn't be >> optimized for the INT_MIN / unsigned case would be nice. > > > New version, that does a bit more. -

Re: [RFA][PATCH] Improve initial probe for noreturn functions for x86 target

On Fri, Nov 3, 2017 at 9:38 AM, Uros Bizjak wrote: >>* config/i386/i386.c (ix86_emit_restore_reg_using_pop): Prototype. >>(ix86_adjust_stack_and_probe_stack_clash): Use a push/pop sequence >>to probe at the start of a noreturn function. >> >>

Re: [RFA][PATCH] Improve initial probe for noreturn functions for x86 target

On Fri, Nov 3, 2017 at 11:14 AM, Richard Biener wrote: > On Fri, Nov 3, 2017 at 9:38 AM, Uros Bizjak wrote: >>>* config/i386/i386.c (ix86_emit_restore_reg_using_pop): >>> Prototype. >>>

GCC 8.0.0 Status Report (2017-11-03)

Status == The feature development phase of GCC 8, Stage 1, is coming to its ends at Friday, Nov. 17th (as usual you can use your local timezone to your own advantage). This means that from Saturday, Nov. 18th we will be in Stage 3 which allows for general bugfixing. All feature

[PATCH PR82776]Exploit more undefined pointer overflow behavior in loop niter analysis

Hi, This is a simple patch exploiting more undefined pointer overflow behavior in loop niter analysis. Originally, it only supports POINTER_PLUS_EXPR if the offset part is IV. This patch also handles the case if pointer is IV. With this patch, the while(true) loop in test can be removed by

[PATCH OBVIOUS]Fix memory leak in tree-predcom.c

Hi, I ran into this memory leak issue in tree-predcom.c when investigating other PRs. This is the obvious fix by freeing reference of trivial component. Bootstrap and test on x86_64. Is it OK? Thanks, bin 2017-11-02 Bin Cheng * tree-predcom.c

Re: [PATCH] Simplify _Node_insert_return to avoid including

On 02/11/17 18:00 -0400, Tim Song wrote: Um, why are those member get's there at all (and with an index mapping that doesn't agree with the member order)? [container.insert.return] says that "It has no base classes or members other than those specified." Because I forgot to implement

Re: [PATCH] New option saphira for Qualcomm server part

On 27/10/17 13:43, Siddhesh Poyarekar wrote: > From: Siddhesh Poyarekar > > This patch adds an mcpu option for the Qualcomm saphira server part. > Tested on aarch64 and did not find any regressions resulting from this > patch. > > Siddhesh > > 2017-10-27

RE: [ARC] Fix stack unwinding for ARC

> - Fix to unwinding. Now is is possible to unwind from syscall > wrappers, signals and functions with dynamic stack allocation. > > - Patch also fixes millicode. Although millicode save and restore functions > would change blink, the calls to those functions were not clobbering blink. >

Re: [PATCH][RFC] Instrument function exit with __builtin_unreachable in C++.

On 10/24/2017 04:19 PM, Jason Merrill wrote: > On 10/18/2017 09:07 AM, Martin Liška wrote: >> @@ -1182,7 +1182,13 @@ cxx_eval_builtin_function_call (const constexpr_ctx >> *ctx, tree t, tree fun, >> { >>    new_call = build_call_array_loc (EXPR_LOCATION (t), TREE_TYPE (t), >>

Re: Adjust empty class parameter passing ABI (PR c++/60336)

On Thu, Nov 02, 2017 at 02:50:17PM -0400, Jason Merrill wrote: > We probably want to call them something like default_is_empty_type and > default_is_empty_record, though. Done. > > For one thing I thought we should be consistent in treating these two > > structs, regarding being empty: > > > >

[PATCH] rs6000: move_from_CR_ov_bit is TARGET_PAIRED_FLOAT, not TARGET_ISEL

Tested as usual, committing to trunk. Segher 2017-11-03 Segher Boessenkool * config/rs6000/rs6000.md (move_from_CR_ov_bit): Change condition to TARGET_PAIRED_FLOAT. --- gcc/config/rs6000/rs6000.md | 2 +- 1 file changed, 1 insertion(+), 1

Re: [RFA][PATCH] Refactor duplicated code used by various dom walkers

On 11/03/2017 04:05 AM, Richard Biener wrote: On Fri, Nov 3, 2017 at 4:49 AM, Jeff Law wrote: Several passes which perform dominator walks want to identify when block has a single incoming edge, ignoring loop backedges. I'm aware of 4 implementations of this code. 3 of

Re: [PATCH][AArch64] Set default sched pressure algorithm

On Thu, Nov 02, 2017 at 06:41:58PM +, Wilco Dijkstra wrote: > The Arm backend sets the default sched-pressure algorithm to > SCHED_PRESSURE_MODEL. Benchmarking on AArch64 shows this > speeds up floating point performance on SPEC - eg. CactusBSSN improves > by ~16%. The gains are mostly due

Re: [PATCH] Improve store merging to handle load+store or bitwise logicals (PR tree-optimization/78821, take 2)

On Fri, 3 Nov 2017, Jakub Jelinek wrote: > On Fri, Nov 03, 2017 at 02:14:39PM +0100, Richard Biener wrote: > > > +/* Return true if stmts in between FIRST (inclusive) and LAST (exclusive) > > > + may clobber REF. FIRST and LAST must be in the same basic block and > > > + have non-NULL vdef.

[PATCH] Fix testsuire error message

Someone noticed I'd not updated the error message when cloneing scan-tree-dump into scan-lang-dump. Fixed thusly and applied nathan -- Nathan Sidwell 2017-11-03 Nathan Sidwell * lib/scanlang.exp: Fix error message to refer to scan-lang-dump. Index: lib/scanlang.exp

Re: [PATCH] Zero vptr in dtor for -fsanitize=vptr.

On Fri, Nov 3, 2017 at 10:25 AM, Martin Liška wrote: > On 10/27/2017 09:44 PM, Nathan Sidwell wrote: >> On 10/27/2017 02:34 PM, Jakub Jelinek wrote: >> >>> But when singly inheriting a polymorphic base and thus mapped to the same >>> vptr all but the last dtor will not be in

Re: [PATCH] Fix test-suite fallout of default -Wreturn-type.

On Thu, Oct 26, 2017 at 8:14 AM, Martin Liška wrote: > On 10/24/2017 04:39 PM, Jason Merrill wrote: >> On 10/18/2017 08:48 AM, Martin Liška wrote: >>> This is second patch that addresses test-suite fallout. All these tests >>> fail because -Wreturn-type is >>> now on by default.

Re: [PATCH] Zero vptr in dtor for -fsanitize=vptr.

On Fri, Nov 03, 2017 at 03:25:25PM +0100, Martin Liška wrote: > On 10/27/2017 09:44 PM, Nathan Sidwell wrote: > > On 10/27/2017 02:34 PM, Jakub Jelinek wrote: > > > >> But when singly inheriting a polymorphic base and thus mapped to the same > >> vptr all but the last dtor will not be in charge,

[PATCH][Arm] Cleanup IT attributes

A recent change to remove the movdi_vfp_cortexa8 meant that ldrd was used in ITs block even when arm_restrict_it was enabled. Rather than just fixing this latent issue, change the default of predicable_short_it to "no" so that only 16-bit instructions need to be marked with it. As a result there

PR82816: Widening multiplies of bitfields

In this PR we tried to create a widening multiply of two 3-bit numbers, but that isn't a widening multiply at the optab/rtl level, since both the input and output still have the same mode. We could trap this either in is_widening_mult_p or (as the patch does) in the routines that actually ask for

Re: [PATCH OBVIOUS]Fix memory leak in tree-predcom.c

On Fri, Nov 3, 2017 at 1:36 PM, Bin Cheng wrote: > Hi, > I ran into this memory leak issue in tree-predcom.c when investigating other > PRs. > This is the obvious fix by freeing reference of trivial component. > Bootstrap and test on x86_64. Is it OK? Ok. Thanks, Richard.

Re: [C++ Patch] PR 80955 (Macros expanded in definition of user-defined literals)

Hi, On 02/11/2017 15:42, Jason Merrill wrote: This is a good suggestion. I have attached the revised patch. Thanks. OK, thanks! Thanks Jason. I was about to volunteer committing the patch but then noticed that the testcase includes quite a lot, eg, too, which we never include in the

Re: [PATCH] RISC-V: Handle non-legitimate address in riscv_legitimize_move

Committed. On Thu, 02 Nov 2017 09:03:19 PDT (-0700), Palmer Dabbelt wrote: > From: Kito Cheng > > GCC may generate non-legitimate address due to we allow some > load/store with non-legitimate address in pic.md. > > gcc/ChangeLog > > 2017-11-02 Kito Cheng

Re: [PATCH] New option saphira for Qualcomm server part

On 03/11/17 12:45, Siddhesh Poyarekar wrote: > On 3 November 2017 at 15:50, Richard Earnshaw > wrote: >>> 2017-10-27 Siddhesh Poyarekar >>> Jim Wilson >>> >>> gcc/ >>> *

[PATCH] rs6000: Improve *lt0 patterns

The rs6000 port currently has an *lt0_disi define_insn, setting the DI result to whether the SI argument is negative or not. It turns out the generic optimisers cannot always figure out in the other cases either that this is just a shift for us. This patch adds patterns for all four SI/DI

[0/10] Vectoriser testsuite tweaks

This series of patches generalises the vector testsuite and makes it cope better with arbitrary vector lengths. It also adds some target selectors needed for SVE. Tested on aarch64-linux-gnu without SVE, with various fixed-length SVE modes, and with the default variable-length SVE mode. Also

[6/10] Add a vect_element_align_preferred target selector

This patch adds a target selector for targets whose preferred_vector_alignment is the alignment of one element. We'll never peel in that case, and the step of a loop that operates on normal (as opposed to packed) elements will always divide the preferred alignment. 2017-11-03 Richard Sandiford

[7/10] Add a vect_unaligned_possible target selector

This patch adds a target selector that says whether we can ever generate an "unaligned" accesses, where "unaligned" is relative to the target's preferred vector alignment. This is already true if: vect_no_align && { ! vect_hw_misalign } i.e. if the target doesn't have any alignment mechanism

Improve canonicalisation of TARGET_MEM_REFs

A general TARGET_MEM_REF is: BASE + STEP * INDEX + INDEX2 + OFFSET After classifying the address in this way, the code that builds TARGET_MEM_REFs tries to simplify the address until it's valid for the current target and for the mode of memory being addressed. It does this in a fixed order:

Use extract_bit_field_as_subreg for vectors

extract_bit_field_1 tries to use vec_extract to extract part of a vector. However, if that pattern isn't defined or if the operands aren't suitable, another good approach is to try a direct subreg reference. This is particularly useful for multi-vector modes on SVE (e.g. when extracting one

[PATCH] ipa-fnsummary.c: fix use-after-free crash (PR jit/82826)

PR jit/82826 reports a crash when running jit.dg/test-benchmark.c, introduced by r254140 (aka "Extend ipa-pure-const pass to propagate malloc attribute.") I see the crash on the 28th of 400 in-process iterations of the compiler; on turning on GCC_JIT_BOOL_OPTION_SELFCHECK_GC, it shows up on the

Re: [PATCH] Fix libsanitizer bootstrap with glibc 2.26

On Fri, Nov 03, 2017 at 10:22:12AM -0700, Andi Kleen wrote: > > It looks like some non POSIX symbols got removed from the header > files, which breaks the libsanitizer build. nm, looks like i was on a old checkout. Seems to be already fixed in current trunk. -Andi

[2/10] Add VECTOR_BITS to tree-vect.h

Several vector tests are sensitive to the vector size. This patch adds a VECTOR_BITS macro to tree-vect.h to select the expected vector size and uses it to influence iteration counts and array sizes. The tests keep the original values if the vector size is small enough. For now VECTOR_BITS is

[PATCH] RISC-V: Emit "i" suffix for instructions with immediate operands

From: Michael Clark This changes makes GCC asm output use instruction names that are consistent with the RISC-V ISA manual. The assembler accepts immediate-operand instructions without the "i" suffix, so this all worked before, it's just a bit cleaner to match the ISA

[3/10] Add available_vector_sizes to target-supports.exp

This patch adds a routine that lists the available vector sizes for a target and uses it for some existing target conditions. Later patches add more uses. The cases are taken from multiple_sizes. 2017-11-03 Richard Sandiford Alan Hayward

Re: [RFC, PR 80689] Copy small aggregates element-wise

Hi, On Thu, Oct 26, 2017 at 02:43:02PM +0200, Richard Biener wrote: > On Thu, Oct 26, 2017 at 2:18 PM, Martin Jambor wrote: > > > > Nevertheless, I still intend to experiment with the limit, I sent out > > this RFC exactly so that I don't spend a lot of time benchmarking > >

[PATCH] Fix libsanitizer bootstrap with glibc 2.26

It looks like some non POSIX symbols got removed from the header files, which breaks the libsanitizer build. struct sigaltstack now only exists as stack_t (which is the offical POSIX name) __res_state typedef is now only struct __res_state This fixes bootstrap of trunk on a current opensuse

[1/10] Consistently use asm volatile ("" ::: "memory") in vect tests

The vectoriser tests used a combination of: 1) if (impossible condition) abort (); 2) volatile int x; ... *x = ...; 3) asm volatile ("" ::: "memory"); to prevent vectorisation of a set-up loop. The problem with 1) is that the compiler can often tell that the condition is false and optimise it

[PATCH] RISC-V: If -m[no-]strict-align is not passed, assume its value from -mtune

From: Andrew Waterman 2017-11-03 Andrew Waterman * config/riscv/riscv.c (riscv_option_override): Conditionally set TARGET_STRICT_ALIGN based upon -mtune argument. --- gcc/config/riscv/riscv.c | 10 +++--- 1 file changed, 7

[9/10] Add a vect_align_stack_vars target selector

This patch adds a target selector to say whether it's possible to align a local variable to the target's preferred vector alignment. This can be false for large vectors if the alignment is only a preference and not a hard requirement (and thus if there is no need to support a stack realignment

Re: [RFA][PATCH] Refactor duplicated code used by various dom walkers

On 11/03/2017 09:01 AM, Jeff Law wrote: On 11/03/2017 04:05 AM, Richard Biener wrote: On Fri, Nov 3, 2017 at 4:49 AM, Jeff Law wrote: Several passes which perform dominator walks want to identify when block has a single incoming edge, ignoring loop backedges. I'm aware

Re: [RFA][PATCH] Improve initial probe for noreturn functions for x86 target

On 11/03/2017 04:46 AM, Uros Bizjak wrote: On Fri, Nov 3, 2017 at 11:14 AM, Richard Biener wrote: On Fri, Nov 3, 2017 at 9:38 AM, Uros Bizjak wrote: * config/i386/i386.c (ix86_emit_restore_reg_using_pop): Prototype.

Re: [RFA][PATCH] Improve initial probe for noreturn functions for x86 target

On Fri, Nov 3, 2017 at 6:13 PM, Jeff Law wrote: > On 11/03/2017 04:46 AM, Uros Bizjak wrote: >> >> On Fri, Nov 3, 2017 at 11:14 AM, Richard Biener >> wrote: >>> >>> On Fri, Nov 3, 2017 at 9:38 AM, Uros Bizjak wrote: > >

[PATCH] Define std::endian for C++2a (P0463R1)

This is a tiny feature, small but perfectly formed. And easy to implement. * include/std/type_traits (endian): Define new enumeration type. * testsuite/20_util/endian/1.cc: New test. Tested powerpc64le-linux, committed to trunk. commit ad69c5875cdefc5c699b50975ee6016a424d450b

[5/10] Add vect_perm3_* target selectors

SLP load permutation fails if any individual permutation requires more than two vector inputs. For 128-bit vectors, it's possible to permute 3 contiguous loads of 32-bit and 8-bit elements, but not 16-bit elements or 64-bit elements. The results are reversed for 256-bit vectors, and so on for

Re: Adjust empty class parameter passing ABI (PR c++/60336)

On Fri, Nov 3, 2017 at 9:55 AM, Marek Polacek wrote: > + TYPE_EMPTY_P (t) = targetm.calls.empty_record_p (t); I think we want to set this in finalize_type_size; since the point of all this is becoming compliant with the psABI (and compatible with the C front end), I wouldn't

Improve vectorisation of COND_EXPR

This patch allows us to recognise: ... = bool1 != bool2 ? x : y as equivalent to: bool tmp = bool1 ^ bool2; ... = tmp ? x : y For the latter we were already able to find the natural number of vector units for tmp based on the types that feed bool1 and bool2, whereas with the former

Improve ivopts handling of forced scales

This patch improves the ivopts address cost calculcation for modes in which an index must be scaled rather than unscaled. Previously we would only try the scaled form if the unscaled form was valid. Many of the SVE tests rely on this when matching scaled indices. Tested on aarch64-linux-gnu,

Improve spilling for variable-size slots

Once SVE is enabled, a general AArch64 spill slot offset will be A + B * VL where A is a constant and B is a multiple of the SVE vector length. The offsets in SVE load and store instructions are a multiple of VL (and so can encode some values of B), while offsets for base AArch64 load and

[PATCH, testsuite]: PR 82828: Fix invalid gcc.target/i386/pr70263-2.c testcase

Hello! This testcase uses undefined values. Attached patch fixes the testcase; the scan for message in the RTL dump assures us that the fix for PR 70263 still performs its magic. 2017-11-03 Uros Bizjak PR testsuite/82828 PR rtl-optimization/70263 *

Re: [RFA][PATCH] Improve initial probe for noreturn functions for x86 target

On 11/03/2017 04:14 AM, Richard Biener wrote: On Fri, Nov 3, 2017 at 9:38 AM, Uros Bizjak wrote: * config/i386/i386.c (ix86_emit_restore_reg_using_pop): Prototype. (ix86_adjust_stack_and_probe_stack_clash): Use a push/pop sequence to probe

[4/10] Don't assume vect_multiple_sizes means 2 sizes

Some tests assumed that there would only be 2 vector sizes if vect_multiple_sizes, whereas for SVE there are three (SVE, 128-bit and 64-bit). This patch replaces scan-tree-dump-times with scan-tree-dump for vect_multiple_sizes but keeps it for !vect_multiple_sizes. 2017-11-03 Richard Sandiford

[8/10] Add a vect_variable_length target selector

This patch adds a target selector for variable-length vectors. Initially it's always false, but the SVE patch provides a case in which it's true. 2017-11-03 Richard Sandiford Alan Hayward David Sherwood

[10/10] Add a vect_masked_store target selector

This patch adds a target selector that says whether the target supports IFN_MASK_STORE. 2017-11-03 Richard Sandiford Alan Hayward David Sherwood gcc/ * doc/sourcebuild.texi

Re: [PATCH][AArch64] Simplify frame layout for stack probing

James Greenhalgh wrote: > > This caused: > >  Failures: >    gcc.target/aarch64/test_frame_4.c >    gcc.target/aarch64/test_frame_2.c >    gcc.target/aarch64/test_frame_7.c >    gcc.target/aarch64/test_frame_10.c Sorry, I missed that in testing. I've reverted part of the patch

[C++ Patch/RFC] PR 82593 ("Internal compiler error: in process_init_constructor_array, at cp/typeck2.c:1294")

Hi, this ICE on valid (given GNU's designated initializers) is rather simple to analyze: for the testcase, the gcc_assert in process_init_constructor_array triggers because at that time INDEX1 is still a CONST_DECL, not an INTEGER_CST. As regards fixing the problem, I immediately noticed

[PATCH] rs6000: Remove rs6000_emit_sISEL

Instead of calling rs6000_emit_sISEL, call rs6000_emit_int_cmove directly, in the one place it is used. Tested as usual; committing to trunk. Segher 2017-11-03 Segher Boessenkool * config/rs6000/rs6-protos.h (rs6000_emit_sISEL): Delete.

[PATCH] RISC-V: Set SLOW_BYTE_ACCESS=1

From: Andrew Waterman When implementing the RISC-V port, I took the name of this macro at face value. It appears we were mistaken in what this means, here's a quote from the SPARC port that better describes what SLOW_BYTE_ACCESS does /* Nonzero if access to memory by

Re: [RFA][PATCH] Improve initial probe for noreturn functions for x86 target

On 11/03/2017 02:38 AM, Uros Bizjak wrote: * config/i386/i386.c (ix86_emit_restore_reg_using_pop): Prototype. (ix86_adjust_stack_and_probe_stack_clash): Use a push/pop sequence to probe at the start of a noreturn function. *

[PATCH] Set default to -fomit-frame-pointer

Almost all targets add an explict -fomit-frame-pointer in the target specific options. Rather than doing this in a target-specific way, do this in the generic options so it works identically across all targets. In many cases the target no longer needs to define TARGET_OPTION_OPTIMIZATION_TABLE,

Re: [RFA][PATCH] Improve initial probe for noreturn functions for x86 target

On 11/03/2017 04:46 AM, Uros Bizjak wrote: On Fri, Nov 3, 2017 at 11:14 AM, Richard Biener wrote: On Fri, Nov 3, 2017 at 9:38 AM, Uros Bizjak wrote: * config/i386/i386.c (ix86_emit_restore_reg_using_pop): Prototype.

Re: [PATCH] C/C++: more stdlib header hints (PR c/81404) (v4)

On Thu, 2 Nov 2017, David Malcolm wrote: > +{"offsetof", {"", ""} }, offsetof is in stddef.h for C, not stdalign.h. -- Joseph S. Myers jos...@codesourcery.com

[Committed] un-XFAIL gfortran testcase on FreeBSD.

The Changelog entry and patch are somewhat self-explanatory. 2017-11-3 Steven G. Kargl * gfortran.dg/large_real_kind_2.F90: Test passes on FreeBSD. Remove dg-xfail-if directive. Index: gcc/testsuite/gfortran.dg/large_real_kind_2.F90

[Patch, fortran] PR81735 - [6/7/8 Regression] double free or corruption (fasttop) error (SIGABRT) with character(:) and custom return type with allocatable

This was already fixed by the patch for PR82375 on trunk, albeit less well than the patch applied here. I will correct trunk tomorrow. Committed as 'obvious' on 6-branch(r254393) and 7-branch(r254389) after bootstrapping and regtesting. Cheers Paul 2017-11-03 Paul Thomas

Re: [RFA][PATCH] Improve initial probe for noreturn functions for x86 target

On 11/03/2017 11:38 AM, Uros Bizjak wrote: On Fri, Nov 3, 2017 at 6:13 PM, Jeff Law wrote: On 11/03/2017 04:46 AM, Uros Bizjak wrote: On Fri, Nov 3, 2017 at 11:14 AM, Richard Biener wrote: On Fri, Nov 3, 2017 at 9:38 AM, Uros Bizjak

[2/4] [AArch64] Testsuite markup for SVE

This patch adds new target selectors for SVE and updates existing selectors accordingly. It also XFAILs some tests that don't yet work for some SVE modes; most of these go away with follow-on vectorisation enhancements. 2017-11-03 Richard Sandiford

[3/4] [AArch64] SVE tests

This patch adds gcc.target/aarch64 tests for SVE, and forces some existing Advanced SIMD tests to use -march=armv8-a. 2017-11-03 Richard Sandiford Alan Hayward David Sherwood

Re: [PATCH] Set default to -fomit-frame-pointer

On Fri, 3 Nov 2017, Wilco Dijkstra wrote: > Almost all targets add an explict -fomit-frame-pointer in the target specific > options. Rather than doing this in a target-specific way, do this in the Which targets do not? You should explicitly list them and CC their maintainers and seek

[0/4] [AArch64] Add SVE support

This series adds support for ARM's Scalable Vector Extension. More details on SVE can be found here: https://developer.arm.com/products/architecture/a-profile/docs/arm-architecture-reference-manual-supplement-armv8-a There are four parts for ease of review, but it probably makes sense to

[PATCH] C/C++: more stdlib header hints (PR c/81404) (v5)

On Fri, 2017-11-03 at 17:49 +, Joseph Myers wrote: > On Thu, 2 Nov 2017, David Malcolm wrote: > > > +{"offsetof", {"", ""} }, > > offsetof is in stddef.h for C, not stdalign.h. Thanks. Here's an updated version of the patch which fixes that. OK for trunk? (assuming bootstrap and

Re: [PATCH 5/6] [ARC] Add 'uncached' attribute.

On 11/03/2017 05:22 AM, Claudiu Zissulescu wrote: I see no documentation here. Ups, forgot this one :) Please find it attached. I'll merge it into the final patch when everything is approved. Thanks, Claudiu +@node ARC Type Attributes +@subsection ARC Type Attributes + +@cindex

Re: [PATCH] Improve store merging to handle load+store or bitwise logicals (PR tree-optimization/78821, take 2)

On November 3, 2017 8:17:30 PM GMT+01:00, Jakub Jelinek wrote: >On Fri, Nov 03, 2017 at 03:04:18PM +0100, Jakub Jelinek wrote: >> single-use vs. multiple uses is something I've thought about, but >don't >> know whether it is better to require single-use or not (or sometimes, >>

Re: [RFA][PATCH] Improve initial probe for noreturn functions for x86 target

3. nov. 2017 20:30 je oseba "Jeff Law" napisala: > > On 11/03/2017 11:38 AM, Uros Bizjak wrote: >> >> On Fri, Nov 3, 2017 at 6:13 PM, Jeff Law wrote: >>> >>> On 11/03/2017 04:46 AM, Uros Bizjak wrote: On Fri, Nov 3, 2017 at 11:14 AM, Richard

RE: [patch][x86] GFNI enabling [2/4]

Here is the solution I propose: gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET): Remove MPX from flag. (ix86_handle_option): Move MPX to isa_flags2 and GFNI to isa_flags. * config/i386/i386-c.c (ix86_target_macros_internal): Ditto.

[1/4] [AArch64] SVE backend support

This patch adds support for ARM's Scalable Vector Extension. The patch just contains the core features that work with the current vectoriser framework; later patches will add extra capabilities to both the target-independent code and AArch64 code. The patch doesn't include: - support for

[PATCH] Use rcrt1.o%s/grcrt1.o%s to relocate static PIE

On Wed, Nov 1, 2017 at 9:39 AM, H.J. Lu wrote: > On Wed, Nov 1, 2017 at 9:32 AM, Rich Felker wrote: >> On Sun, Oct 15, 2017 at 06:16:57AM -0700, H.J. Lu wrote: >>> crt1.o is used to create dynamic and non-PIE static executables. Static >>> PIE needs to link

Re: [PATCH] Set default to -fomit-frame-pointer

On 11/03/2017 10:54 AM, Wilco Dijkstra wrote: diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 71b2445f70fd5b832c68c08e69e71d8ecad37a4a..1c56f4b12495fe97c604200ef245c9fa02684b0f 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -7436,16 +7436,17 @@ machine-description

[4/4] SVE unwinding

This patch adds support for unwinding frames that use the SVE pseudo VG register. We want this register to act like a normal register if the CFI explicitly sets it, but want to provide a default value otherwise. Computing the default value requires an SVE target, so we only want to compute it on

Re: [C++ Patch] PR 65579 ("gcc requires definition of a static constexpr member...")

On Thu, Oct 26, 2017 at 6:17 AM, Paolo Carlini wrote: > Hi again, > > On 24/10/2017 20:58, Jason Merrill wrote: >> >> This seems like an odd place to add the complete_type call. What >> happens if we change the COMPLETE_TYPE_P (type) in >> cp_apply_type_quals_to_decl to

Re: [PATCH] Improve store merging to handle load+store or bitwise logicals (PR tree-optimization/78821, take 2)

On Fri, Nov 03, 2017 at 03:04:18PM +0100, Jakub Jelinek wrote: > single-use vs. multiple uses is something I've thought about, but don't > know whether it is better to require single-use or not (or sometimes, > under some condition?). Say if we have: So, here is what I've committed in the end

RE: [patch][x86] GFNI enabling [2/4]

> But what do you think about adding AVX/SSE flags to this special set instead? Ok, was wrong, it is impossible to add SSE, because it is used in normal "or" way. Then I'll add GFNI/VAES instead. There is also another problem there: GFNI belongs to isa_flags2, while AVX512VL/AVX/SSE belong to

Re: [RFA][PATCH] Improve initial probe for noreturn functions for x86 target

>* config/i386/i386.c (ix86_emit_restore_reg_using_pop): Prototype. >(ix86_adjust_stack_and_probe_stack_clash): Use a push/pop sequence >to probe at the start of a noreturn function. > >* gcc.target/i386/stack-check-12.c: New test -

Re: [RFA][PATCH][PR target/82788] Remove uses of PROBE_INTERVAL in x86 target files

Hello! -ENOCHANGELOG diff --git a/gcc/testsuite/gcc.c-torture/execute/pr82788.c b/gcc/testsuite/gcc.c-torture/execute/pr82788.c new file mode 100644 index 000..ceaa25f --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/pr82788.c @@ -0,0 +1,2 @@ + +int main() { int a[1442]; return 0;}

[PATCH] Initialize variable in order to survive PGO bootstrap.

Hi. This is oneliner that fixes PGO bootstrap. I've discussed that with Richi and the core is correct. However we probably don't have an attribute that will ignore the warning? Only option is to push/pop Wuninitialized warning. Ready for trunk? Thanks, Martin gcc/ChangeLog: 2017-11-03 Martin

Re: [PATCH 2/2] [i386] PR82002 Part 2: Correct non-immediate offset/invalid INSN

On 11/03/2017 04:22 PM, Daniel Santos wrote: > ... > How does this patch look?  (Also, I've updated comments for > choose_baseaddr.)  Currently re-running tests. > > Thanks, > Daniel > > @@ -13110,10 +13125,26 @@ ix86_expand_prologue (void) >target. */ >if (TARGET_SEH) >

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