On 27.04.23 20:36, Julian Brown wrote:
This patch fixes several cases where multiple attach or detach mapping
nodes were being created for stand-alone attach or detach clauses
in Fortran. After the introduction of stricter checking later during
compilation, these extra nodes could cause ICEs,
Hi Thomas,
maybe I misunderstood your suggestion, but "Wait on a memory location"
assumes that there will be a change – but if a target region happens to
have no reverse offload, the memory location will never change, but
still the target region should return to the host.
What we would need:
Hi all,
More of the straightforward cases to annotate plus tests, this time for simple
integer unary ops.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
Pushing to trunk.
Thanks,
Kyrill
gcc/ChangeLog:
PR target/99195
* config/aarch64/aarch64-simd.md
OK
On Fri, Apr 28, 2023 at 2:12 PM Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> RISC-V does currently not support index registers.
> However, there are some vendor extensions that specify them.
> Let's do the necessary changes in the backend so that we can
> add support for such a
On Fri, 28 Apr 2023 at 08:34, Jakub Jelinek wrote:
> Hi!
>
> GCC used to emit an instance of an empty ios_base::Init class in
> every TU which included to ensure it is std::cout etc.
> is initialized, but thanks to Patrick work on some targets (which have
> init_priority attribute support) it
Feel free to just commit those patch got approved, I think last two
patch will take longer time to review than others :P
On Fri, Apr 28, 2023 at 2:12 PM Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> This series improves the support for the XThead* ISA extensions
> which are
LGTM, I like this refactor.
On Fri, Apr 28, 2023 at 2:12 PM Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> This patch moves the XThead*-specific peephole passes
> into thead-peephole.md with the intend to keep vendor-specific
> code separated from RISC-V standard code.
>
> This
Hi Thomas,
On 21.03.23 16:53, Thomas Schwinge wrote:
On 2022-08-26T11:07:28+0200, Tobias Burnus
wrote:
This patch adds initial [OpenMP reverse offload] support for nvptx.
CUDA does lockup when trying to copy data from the currently running
stream; hence, a new stream is generated to do the
From: Christoph Müllner
This series improves the support for the XThead* ISA extensions
which are available e.g. on the T-Head XuanTie C906.
The ISA spec can be found here:
https://github.com/T-head-Semi/thead-extension-spec
So far the following extension support has been merged in GCC:
*
From: Christoph Müllner
The current support of the bitfield-extraction instructions
th.ext and th.extu (XTheadBb extension) only covers sign_extract
and zero_extract. This patch add support for sign_extend and
zero_extend to avoid any shifts for sign or zero extensions.
gcc/ChangeLog:
From: Christoph Müllner
We have the following situation for MEM RTX objects:
* TARGET_PRINT_OPERAND expands to riscv_print_operand()
* This falls into the default case (unknown or on letter) of the outer
switch-case-block and the MEM case of the inner switch-case-block and
calls
From: Christoph Müllner
A recent change adjusted the constraints of ZBA's shNadd INSN.
Let's mirror this change here as well.
gcc/ChangeLog:
* config/riscv/thead.md: Adjust constraints of th_addsl.
Signed-off-by: Christoph Müllner
---
gcc/config/riscv/thead.md | 5 ++---
1 file
From: Christoph Müllner
The XTheadFMemIdx ISA extension provides additional load and store
instructions for floating-point registers with new addressing modes.
The following memory accesses types are supported:
* ftype = [w,d] (single-precision, double-precision)
The following addressing modes
From: Christoph Müllner
The XTheadMemIdx ISA extension provides a additional load and store
instructions with new addressing modes.
The following memory accesses types are supported:
* ltype = [b,bu,h,hu,w,wu,d]
* stype = [b,h,w,d]
The following addressing modes are supported:
* immediate
> The defined predicate of vector_move_operand composes of (non-imm || (const
> vector && (reload_completed ? constraint_vi (op) : constraint_wc0(op))).
I may not quit understand why we group them together and named as vector_move.
I forgot the detail reason about that, but vaguely remember that
LGTM
I thought it can optimization __riscv_vmseq_vv_i8m8_b1(v1, v1, vl)
too, but don't know why it's not evaluated
(eq:VNx128BI (reg/v:VNx128QI 137 [ v1 ])
(reg/v:VNx128QI 137 [ v1 ]))
to true, anyway, I guess it should be your next step to investigate :)
On Fri, Apr 28,
On 28.04.2023 00:24, Nathan Sidwell wrote:
> On 4/25/23 11:04, Jan Beulich wrote:
>> On 28.06.2022 16:06, Jan Beulich wrote:
>>> The pathname underneath gcm.cache/ is determined from the effective name
>>> used for the main input file of a particular module. When modules are
>>> built, no
On Sun, Apr 23, 2023 at 10:14 PM Roger Sayle wrote:
>
>
> This patch fixes PR rtl-optimization/109476, which is a code quality
> regression affecting AVR. The cause is that the lower-subreg pass is
> sometimes overly aggressive, lowering the LSHIFTRT below:
>
> (insn 7 4 8 2 (set (reg:HI 51)
>
My first impression is that it should be the same as Pmode, but I
admit it has more clear semantics, and would be useful when we have
ilp32 on rv64.
So LGTM
On Fri, Apr 28, 2023 at 2:16 PM Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> Define a Xmode macro that specifies the
OK :)
On Fri, Apr 28, 2023 at 2:15 PM Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> enum riscv_address_type and struct riscv_address_info are used
> to store address classification information. Let's move this types
> into our common header file in order to share them with other
>
From: Christoph Müllner
The current implementation triggers an assertion in
dwarf2out_frame_debug_cfa_offset() under certain circumstances.
The standard code uses REG_FRAME_RELATED_EXPR notes instead
of REG_CFA_OFFSET notes when saving registers on the stack.
So let's do this as well.
From: Christoph Müllner
enum riscv_address_type and struct riscv_address_info are used
to store address classification information. Let's move this types
into our common header file in order to share them with other
compilation units.
This is a non-functional change without any intendet
From: Christoph Müllner
Define a Xmode macro that specifies the registers size (XLEN)
similar to Pmode. This allows the backend code to write generic
RV32/RV64 C code (under certain circumstances).
gcc/ChangeLog:
* config/riscv/riscv.h (Xmode): New macro.
Signed-off-by: Christoph
From: Christoph Müllner
This patch moves the XThead*-specific peephole passes
into thead-peephole.md with the intend to keep vendor-specific
code separated from RISC-V standard code.
This patch does not contain any functional changes.
gcc/ChangeLog:
* config/riscv/peephole.md: Remove
From: Christoph Müllner
RISC-V does currently not support index registers.
However, there are some vendor extensions that specify them.
Let's do the necessary changes in the backend so that we can
add support for such a vendor extension in the future.
This is a non-functional change without any
From: Christoph Müllner
There is an incorrect sentence in the documentation of the function
th_mempair_order_operands(). Let's remove it.
gcc/ChangeLog:
* config/riscv/thead.cc (th_mempair_operands_p):
Fix documentation of th_mempair_order_operands().
Signed-off-by: Christoph
On Thu, Apr 27, 2023 at 5:15 PM Roger Sayle wrote:
>
>
> This patch updates include/ctf.h to match the current libctf version in
> binutils' include/. I recently attempted to build a uber tree (following
> some notes that are so old they used CVS) and noticed that binutils won't
> build with
Thanks, kito.
Yes, you are right. I am investigating this right now from simplify rtl. Given
we have one similar case VMORN in previous.
Pan
-Original Message-
From: Kito Cheng
Sent: Friday, April 28, 2023 2:41 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang,
ok
On Fri, Apr 28, 2023 at 2:15 PM Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> The current implementation triggers an assertion in
> dwarf2out_frame_debug_cfa_offset() under certain circumstances.
> The standard code uses REG_FRAME_RELATED_EXPR notes instead
> of REG_CFA_OFFSET
ok
On Fri, Apr 28, 2023 at 2:13 PM Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> The current support of the bitfield-extraction instructions
> th.ext and th.extu (XTheadBb extension) only covers sign_extract
> and zero_extract. This patch add support for sign_extend and
>
LGTM
On Fri, Apr 28, 2023 at 2:17 PM Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> There is an incorrect sentence in the documentation of the function
> th_mempair_order_operands(). Let's remove it.
>
> gcc/ChangeLog:
>
> * config/riscv/thead.cc (th_mempair_operands_p):
>
LGTM, personally I also like this way too.
On Fri, Apr 28, 2023 at 2:13 PM Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> A recent change adjusted the constraints of ZBA's shNadd INSN.
> Let's mirror this change here as well.
>
> gcc/ChangeLog:
>
> * config/riscv/thead.md:
LGTM, thanks :)
On Fri, Apr 28, 2023 at 2:13 PM Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> We have the following situation for MEM RTX objects:
> * TARGET_PRINT_OPERAND expands to riscv_print_operand()
> * This falls into the default case (unknown or on letter) of the outer
>
Committed as r14-319-g7ebd4a1d61993c0a75e9ff3098aded21ef04a4da
Tobias
-
Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634
München; Gesellschaft mit beschränkter Haftung; Geschäftsführer: Thomas
Heurung, Frank Thürauf; Sitz der Gesellschaft: München;
Hi!
GCC used to emit an instance of an empty ios_base::Init class in
every TU which included to ensure it is std::cout etc.
is initialized, but thanks to Patrick work on some targets (which have
init_priority attribute support) it is now initialized only inside of
libstdc++.so.6/libstdc++.a.
On 4/27/23 10:22, Patrick O'Neill wrote:
This patchset aims to make the RISCV atomics implementation stronger
than the recommended mapping present in table A.6 of the ISA manual.
https://github.com/riscv/riscv-isa-manual/blob/c7cf84547b3aefacab5463add1734c1602b67a49/src/memory.tex#L1083-L1157
Hi Andrea, Stam,
> -Original Message-
> From: Andrea Corallo
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; Stam Markianos-Wright wri...@arm.com>
> Subject: [PATCH 04/10] arm: Stop vadcq, vsbcq intrinsics from
This adds the patterns for
POPCOUNT BSWAP FFS PARITY CLZ and CTZ.
For "a != 0 ? FUNC(a) : CST".
CLRSB, CLRSBL, and CLRSBLL will be moved next.
Note this is not enough to remove
cond_removal_in_builtin_zero_pattern as we need to handle
the case where there is an NOP_CONVERT inside the conditional
While moving working on moving
cond_removal_in_builtin_zero_pattern to match, I noticed
that functions were not allowed to move as we reject all
non-assignments.
This changes to allowing a few calls which are known not
to throw/trap. Right now it is restricted to ones
which
Hi Kwok,
On 17.02.23 12:45, Kwok Cheung Yeung wrote:
This is a revised version of the patch for the 'present' modifier for
OpenMP. Compared to the first version, three improvements have been made:
- A bug which caused bootstrapping with a '-m32' multilib on x86-64 to
fail due to pointer size
On 4/27/23 10:22, Patrick O'Neill wrote:
This patch sets the relevant .rl bits on amo operations.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_print_operand): change behavior
of %A to include release bits.
Capitalize "change" in the ChangeLog
On Fri, 28 Apr 2023 10:40:15 PDT (-0700), jeffreya...@gmail.com wrote:
On 4/27/23 10:22, Patrick O'Neill wrote:
This change makes atomic stores strictly stronger than table A.6 of the
ISA manual. This mapping makes the overall patchset compatible with
table A.7 as well.
2023-04-27 Patrick
On 4/27/23 10:22, Patrick O'Neill wrote:
This change brings atomic fences in line with table A.6 of the ISA
manual.
Relax mem_thread_fence according to the memmodel given.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/sync.md (mem_thread_fence_1): Change fence
On 4/28/23 10:44, Patrick O'Neill wrote:
On 4/28/23 09:29, Palmer Dabbelt wrote:
On Fri, 28 Apr 2023 09:14:00 PDT (-0700), jeffreya...@gmail.com wrote:
On 4/27/23 10:22, Patrick O'Neill wrote:
...
LLVM mapping notes
LLVM emits corresponding fences for atomic_signal_fence
On Fri, 28 Apr 2023, Patrick Palka wrote:
> After mechanically replacing RESULT_DECL within a constexpr call result
> (for sake of RVO), we can in some cases simplify the call result
> further.
>
> In the below testcase the result of get() during evaluation of a's
> initializer is the
On Fri, 28 Apr 2023, Patrick Palka wrote:
> On Fri, 28 Apr 2023, Patrick Palka wrote:
>
> > After mechanically replacing RESULT_DECL within a constexpr call result
> > (for sake of RVO), we can in some cases simplify the call result
> > further.
> >
> > In the below testcase the result of get()
On 4/26/23 15:45, Michael Collison wrote:
2023-04-24 Michael Collison
Juzhe Zhong
* config/riscv/riscv-v.cc
(riscv_vector_preferred_simd_mode): New function.
(get_mask_policy_no_pred): Ditto.
(get_tail_policy_no_pred): Ditto.
On 4/26/23 15:45, Michael Collison wrote:
2023-03-02 Michael Collison
Juzhe Zhong
* config/riscv/riscv-vector-builtins.cc (get_tail_policy_for_pred):
Remove static declaration to to make externally visible.
(get_mask_policy_for_pred): Ditto.
*
The RISC-V psABI pull request is at
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/378 . Pointers to
Paul Kirth's corresponding LLVM patches are also there.
On Fri, Apr 28, 2023 at 2:42 PM Hans Boehm wrote:
> The concern with making the new behavior non-default is of course that the
On 4/28/23 16:42, Hans-Peter Nilsson wrote:
On Sat, 22 Apr 2023, Ajit Agarwal via Gcc-patches wrote:
Hello All:
This new version of patch 4 use improve ree pass for rs6000 target using
defined ABI interfaces.
Bootstrapped and regtested on power64-linux-gnu.
Thanks & Regards
Ajit
There is no canonical form for this case defined. So the aarch64 backend needs
a pattern to match both of these forms.
The forms are:
(set (reg/i:SI 0 x0)
(if_then_else:SI (eq (reg:CC 66 cc)
(const_int 0 [0]))
(reg:SI 97)
(const_int -1 [0x])))
and
On 4/16/23 07:20, Ajit Agarwal wrote:
Hello All:
This patch improves code sinking pass to sink the blocks before calls
in the use blocks or immediate dominator blocks that reduces register pressure.
Bootstrapped and regtested on powerpc64-linux-gnu.
Thanks & Regards
Ajit
On 4/26/23 15:45, Michael Collison wrote:
2023-04-24 Michael Collison
Juzhe Zhong
* config/riscv/riscv-protos.h
(riscv_vector_preferred_simd_mode): New.
(riscv_vector_mask_mode_p): Ditto.
(riscv_vector_get_mask_mode): Ditto.
Thanks Jeff for comments.
It makes sense to me. For the EQ operator we should have CONSTM1. Does this
mean s390 parts has similar issue here? Then for instructions like VMSEQ, we
need to adjust the simplify_rtx up to a point.
Please help to correct me if any mistake. Thank you again.
Pan
On 4/20/23 15:03, Ajit Agarwal wrote:
Currently I support AND with const1_rtx. This is what is equivalent to zero
extension instruction in power instruction set. When you specify many other
constants and Could you please specify what other constants needs to be
supported and how to
On Fri, 28 Apr 2023, Jeff Law wrote:
> On 4/28/23 16:42, Hans-Peter Nilsson wrote:
> > On Sat, 22 Apr 2023, Ajit Agarwal via Gcc-patches wrote:
> > I don't see anything in those functions that checks if
> > ZERO_EXTEND is actually a feature of the ABI, e.g. as opposed to
> > no extension or
On 4/28/23 09:58, Hans-Peter Nilsson via Gcc-patches wrote:
Ok to commit?
-- >8 --
I tried to make use of check-function-bodies for cris-elf and was a
bit surprised to see it failing. There's a deliberate empty line
after the filled delay slot of the return-function which was
mishandled. I
OpenMP 5.0 removed the restriction that multiple collapsed loops must
be perfectly nested, allowing "intervening code" (including nested
BLOCKs) before or after each nested loop. In GCC this code is moved
into the inner loop body by the respective front ends.
This patch changes the C++ front end
OpenMP 5.0 removed the restriction that multiple collapsed loops must
be perfectly nested, allowing "intervening code" (including nested
BLOCKs) before or after each nested loop. In GCC this code is moved
into the inner loop body by the respective front ends.
This patch changes the C front end
OpenMP 5.0 removed the restriction that multiple collapsed loops must
be perfectly nested, allowing "intervening code" (including nested
BLOCKs) before or after each nested loop. In GCC this code is moved
into the inner loop body by the respective front ends.
In the Fortran front end, most of
OpenMP 5.0 removed the restriction that collapsed loops in "omp
for/do" and related constructs must be perfectly nested; it now allows
intervening code to appear before/after each nested loop level. The
spec allows implementations considerable freedom in how many times this
intervening code is
On Sat, 22 Apr 2023, Ajit Agarwal via Gcc-patches wrote:
> Hello All:
>
> This new version of patch 4 use improve ree pass for rs6000 target using
> defined ABI interfaces.
> Bootstrapped and regtested on power64-linux-gnu.
>
> Thanks & Regards
> Ajit
>
>
> ree: Improve ree pass for
Ok to commit?
-- >8 --
I tried to make use of check-function-bodies for cris-elf and was a
bit surprised to see it failing. There's a deliberate empty line
after the filled delay slot of the return-function which was
mishandled. I thought "aha" and tried to add an empty line
(containing just a
On 4/27/23 10:22, Patrick O'Neill wrote:
Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
libgcc/ChangeLog:
* config/riscv/atomic.c: Change LR.aq/SC.rl pairs into
sequentially consistent
These two patches implement the base support of builtin_zero_pattern
into match.pd. To implement the other part requires match-and-simplify
inside phiopt to support moving 2 statements from the middle-bb. The
match.pd part is already incldued. I will try to get to it next week.
Also
On 4/27/23 10:22, Patrick O'Neill wrote:
This change makes atomic stores strictly stronger than table A.6 of the
ISA manual. This mapping makes the overall patchset compatible with
table A.7 as well.
2023-04-27 Patrick O'Neill
PR 89835
Should be "PR target/89835"
gcc/ChangeLog:
After mechanically replacing RESULT_DECL within a constexpr call result
(for sake of RVO), we can in some cases simplify the call result
further.
In the below testcase the result of get() during evaluation of a's
initializer is the self-referential CONSTRUCTOR:
{._M_p=(char *) &._M_local_buf}
On 4/21/23 04:07, Fei Gao wrote:
Currently in rv32e, stack allocation for GPR callee-saved registers is
always 12 bytes w/o save-restore. Actually, for the case without save-restore,
less stack memory can be reserved. This patch decouples stack allocation for
rv32e w/o save-restore and makes
Hi,
I figured I'm going to start sending some patches that build on top
of the upcoming RISC-V autovectorization. This one is obviously
not supposed to be installed before the basic support lands but
it's small enough that it shouldn't hurt to send it now.
This patch allows vector constants in
PR target/105525 is a build regression for the vax and lm32 linux
targets present in gcc-12/13/head, where the builds fail due to
unsatisfied references to __INTPTR_TYPE__ and __UINTPTR_TYPE__,
caused by these two targets failing to provide glibc-stdint.h.
Fixed thusly, tested by building
GCC_11.0 is an aarch64-specific outlier.
* doc/xml/manual/abi.xml (abi.versioning.history): Add
GCC_7.0.0, GCC_9.0.0, GCC_11.0, GCC_12.0.0, GCC_13.0.0 for
libgcc_s.
---
libstdc++-v3/doc/xml/manual/abi.xml | 5 +
1 file changed, 5 insertions(+)
diff --git
The concern with making the new behavior non-default is of course that the
generated code will eventually end up on an A.7-capable platform.
An A.6-classic option for compiling code that will never run on a newer
machine seems OK. But I'm not sure that seq_cst stores are dynamically
frequent
On 4/12/23 07:18, shiyul...@iscas.ac.cn wrote:
From: yulong
This patch fix a redefinition bug.
There are have a definition about mode_t in the fd-4.c, but it duplicates the
definition in types.h that be included by stdio.h.
Thanks to Jeff Law for reviewing the previous version.
> -Original Message-
> From: Andrea Corallo
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; Andrea Corallo
> Subject: [PATCH 02/10] arm: Fix vstrwq* backend + testsuite
>
> Hi all,
>
> this patch fixes the vstrwq* MVE
On 4/27/23 10:22, Patrick O'Neill wrote:
Atomic operations with the appropriate bits set already enfore release
semantics. Remove unnecessary release fences from atomic ops.
This change brings AMO ops in line with table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
On 4/28/23 10:10, Robin Dapp wrote:
Hi,
I figured I'm going to start sending some patches that build on top
of the upcoming RISC-V autovectorization. This one is obviously
not supposed to be installed before the basic support lands but
it's small enough that it shouldn't hurt to send it
On 4/20/23 09:56, Jeff Law via Gcc-patches wrote:
On 1/17/23 15:59, Vineet Gupta wrote:
This could be useful for library writers who want to write code variants
for fast vs. slow unaligned accesses.
We distinguish explicit -mstrict-align (1) vs. slow_unaligned_access
cpu tune param (2)
On 25/04/2023 13:30, Richard Biener wrote:
On Mon, 24 Apr 2023, Richard Sandiford wrote:
Richard Biener writes:
On Thu, Apr 20, 2023 at 3:24?PM Andre Vieira (lists) via Gcc-patches
wrote:
Rebased all three patches and made some small changes to the second one:
- removed sub and abd
> -Original Message-
> From: Andrea Corallo
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; Stam Markianos-Wright wri...@arm.com>
> Subject: [PATCH 06/10] arm: Fix overloading of MVE scalar constant
> parameters on
> -Original Message-
> From: Andrea Corallo
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; Stam Markianos-Wright wri...@arm.com>
> Subject: [PATCH 05/10] arm: Add vorrq_n overloading into vorrq _Generic
>
> From: Stam
> -Original Message-
> From: Andrea Corallo
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; Stam Markianos-Wright wri...@arm.com>
> Subject: [PATCH 09/10] arm testsuite: XFAIL or relax registers in some tests
>
> From:
On 4/27/23 10:23, Patrick O'Neill wrote:
These tests cover basic cases to ensure the atomic mappings follow the
strengthened Table A.6 mappings that are compatible with Table A.7.
2023-04-27 Patrick O'Neill
gcc/testsuite/ChangeLog:
* gcc.target/riscv/amo-table-a-6-amo-add-1.c: New
On 4/27/23 10:22, Patrick O'Neill wrote:
Remove references to MEMMODEL_SYNC_* models by converting via
memmodel_base().
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/riscv.cc: Remove MEMMODEL_SYNC_* cases and
sanitize memmodel input with memmodel_base.
OK. Not
On Fri, 28 Apr 2023 08:20:24 PDT (-0700), jeffreya...@gmail.com wrote:
On 4/27/23 01:39, Jan Beulich via Gcc-patches wrote:
On 26.04.2023 17:45, Palmer Dabbelt wrote:
On Wed, 26 Apr 2023 08:26:26 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
On 4/25/23 08:50, Jan Beulich via Gcc-patches
> -Original Message-
> From: Andrea Corallo
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; Stam Markianos-Wright wri...@arm.com>
> Subject: [PATCH 10/10] arm testsuite: Shifts and get_FPSCR ACLE optimisation
> fixes
>
On 4/28/23 09:29, Palmer Dabbelt wrote:
On Fri, 28 Apr 2023 09:14:00 PDT (-0700), jeffreya...@gmail.com wrote:
On 4/27/23 10:22, Patrick O'Neill wrote:
This patchset aims to make the RISCV atomics implementation stronger
than the recommended mapping present in table A.6 of the ISA manual.
Hi Andrea,
> -Original Message-
> From: Andrea Corallo
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; Andrea Corallo
> Subject: [PATCH 03/10] arm: Mve backend + testsuite fixes 2
>
> Hi all,
>
> this patch improves a
On 4/28/23 10:43, Palmer Dabbelt wrote:
On Fri, 28 Apr 2023 08:20:24 PDT (-0700), jeffreya...@gmail.com wrote:
On 4/27/23 01:39, Jan Beulich via Gcc-patches wrote:
On 26.04.2023 17:45, Palmer Dabbelt wrote:
On Wed, 26 Apr 2023 08:26:26 PDT (-0700), gcc-patches@gcc.gnu.org
wrote:
On
On 4/27/23 10:23, Patrick O'Neill wrote:
This change brings atomic loads in line with table A.6 of the ISA
manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/sync.md (atomic_load): Implement atomic
load mapping.
OK.
jeff
On 28 April 2023 09:26:06 CEST, Tobias Burnus wrote:
>Committed as r14-319-g7ebd4a1d61993c0a75e9ff3098aded21ef04a4da
> Only other changes are fixing the variable name a(b)breviated_modproc_decl
I think this is not good, I've mentioned it somewhere, i think, but I'll rename
it.
thanks!
We're certainly pushing for the same ABI (A.6 + trailing fence on store) in
LLVM as well. I'm about to upload a pull request for the psABI document
that describes this version of the ABI, and a bit of the rationale for it.
I'll attach the current draft here.
I agree that compatibility is critical
Kito and I were talking this morning, he's going to try and find the
time to actually write this. Kind of odd to send to the mailing list,
but I figure that's the easist way to get it out. It's very much not
mergeable as is...
---
gcc/doc/invoke.texi | 87
On 2/17/23 07:02, Matevos Mehrabyan via Gcc-patches wrote:
Hi all,
If we have division and remainder calculations with the same operands:
a = b / c;
d = b % c;
We can replace the calculation of remainder with multiplication +
subtraction, using the result from the previous division:
On 4/6/23 21:37, shiyul...@iscas.ac.cn wrote:
From: yulong
This patch fixes the problem of the contracts-tmpl-spec2.c running failure.
When run the dejagnu test, I find that the output is inconsistent with that
verified
in the testcase. So I try to modify it, and then it can be passed.
On Fri, Apr 28, 2023 at 09:35:49AM +0100, Jonathan Wakely wrote:
> Yes, for both, thanks for the fix.
>
> After it lands on the gcc-13 branch I'll also update the manual with:
>
> --- a/libstdc++-v3/doc/xml/manual/abi.xml
> +++ b/libstdc++-v3/doc/xml/manual/abi.xml
> @@ -275,6 +275,7 @@
On 4/6/23 19:37, juzhe.zh...@rivai.ai wrote:
From: Juzhe-Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/rvv.exp: Add auto-vectorization testing.
* gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: Adapt testcase.
*
On Fri, 28 Apr 2023 09:14:00 PDT (-0700), jeffreya...@gmail.com wrote:
On 4/27/23 10:22, Patrick O'Neill wrote:
This patchset aims to make the RISCV atomics implementation stronger
than the recommended mapping present in table A.6 of the ISA manual.
On 4/27/23 10:22, Patrick O'Neill wrote:
This patch enforces SEQ_CST for atomic compare_exchange ops.
Replace Fence/LR.aq/SC.aq pairs with SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/sync.md:
On 4/27/23 10:22, Patrick O'Neill wrote:
Introduce the %I and %J flags for setting the .aqrl bits on LR/SC pairs
as needed.
Atomic compare and exchange ops provide success and failure memory
models. C++17 and later place no restrictions on the relative strength
of each model, so ensure we
On 28 April 2023 11:23:55 CEST, Florian Weimer via Fortran
wrote:
>* Martin Liška:
>But that's okay for me as well.
Even better.
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