On 8/31/23 06:51, Jeff Law wrote:
On 8/30/23 15:57, Vineet Gupta wrote:
This was tripping up gcc.c-torture/execute/pr60003.c at -O1 since the
pattern semantics can't be expressed by zicond instructions.
This involves test code snippet:
if (a == 0)
return 0;
else
On Thu, Aug 31, 2023 at 01:11:57PM -0400, Jason Merrill wrote:
> > 2023-08-28 Jakub Jelinek
> >
> > PR c++/111069
> > gcc/
> > * common.opt (fabi-version=): Document version 19.
> > * doc/invoke.texi (-fabi-version=): Likewise.
> > gcc/c-family/
> > * c-opts.cc
On 8/31/23 04:08, Jakub Jelinek wrote:
Hi!
C++17 had in [basic.block.scope]/2
"A parameter name shall not be redeclared in the outermost block of the function
definition nor in the outermost block of any handler associated with a
function-try-block."
and in [basic.block.scope]/4 similar rule
On Thu, Aug 31, 2023 at 05:56:26PM +, Joseph Myers wrote:
> On Thu, 31 Aug 2023, Yujie Yang wrote:
>
> > -If none of such suffix is present, the configured value of
> > -@option{--with-multilib-default} can be used as a common default suffix
> > -for all library ABI variants. Otherwise, the
On 2023-08-29 09:46 Jeff Law wrote:
>
>
>
>On 8/28/23 19:28, Fei Gao wrote:
>> On 2023-08-29 06:54 Jeff Law wrote:
>>>
>>>
>>>
>>> On 8/28/23 01:47, Fei Gao wrote:
no functional changes but allow targets to check shrink-wrap-separate
enabled or not.
gcc/ChangeLog:
On Wed, 2023-08-30 at 18:15 -0400, Eric Feng wrote:
> On Tue, Aug 29, 2023 at 5:14 PM David Malcolm
> wrote:
> >
> > On Tue, 2023-08-29 at 13:28 -0400, Eric Feng wrote:
> > > Additionally, by using the old model and the pointer per your
> > > suggestion,
> > > we are able to find the
Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/
This patch updates the riscv instructions to ensure that no insn is left
without a type attribute. Added new types: "trap" (self explanatory) and "cbo"
(for cache related instructions)
On Thu, 31 Aug 2023, 18:43 Jonathan Wakely via Libstdc++, <
libstd...@gcc.gnu.org> wrote:
> On Thu, 31 Aug 2023 at 16:26, Christophe Lyon
> wrote:
> >
> > As discussed in PR104167 (comments #8 and below), and PR111238, using
> > -Wl,-gc-sections in the libstdc++ testsuite for arm-eabi
> >
Dear all,
gfortran's array bounds-checking code does a mostly reasonable
job for array sections in expressions and assignments, but
forgot the case that (rank-1) expressions can involve array
constructors, which have a shape ;-)
The attached patch walks over the loops generated by the
Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/
This patch updates the pic instructions to ensure that no insn is left
without a type attribute.
Tested for regressions using rv32/64 multilib with newlib/linux.
gcc/Changelog:
> From: Hans-Peter Nilsson
> Date: Thu, 31 Aug 2023 19:05:19 +0200
> > Date: Thu, 31 Aug 2023 17:25:45 +0200
> > From: Christophe Lyon via Gcc-patches
> > However, this would hide the fact that libstdc++ somehow forces the
> > user to use -Wl,-gc-sections to avoid undefined references to
On 8/31/23 03:20, Jakub Jelinek wrote:
Hi!
As the following testcase shows, while check_local_shadow diagnoses most of
the [basic.scope.block]/2 violations, it doesn't diagnose when parameter's
name is redeclared inside of the compound-stmt of a function-try-block.
There is in that case an
From: benjamin priour
Hi,
Succesfully regstrapped off trunk 7f2ed06ddc825e8a4e0edfd1d66b5156e6dc1d34
on x86_64-linux-gnu.
Is it OK for trunk ?
Thanks,
Benjamin.
Patch below.
---
Fixed spurious possibly-NULL warning always tagging along throwing
operator new despite it never returning NULL.
On 8/28/23 09:58, Jakub Jelinek wrote:
Hi!
On Thu, Aug 24, 2023 at 06:39:10PM +0200, Jakub Jelinek via Gcc-patches wrote:
Maybe do this in mangle_decomp, based on the actual mangling in process
instead of this pseudo-mangling?
Not sure that is possible, for 2 reasons:
1)
This patch adds the following match patterns to optimize these:
/* (a != b) ? (a - b) : 0 -> (a - b) */
/* (a != b) ? (a ^ b) : 0 -> (a ^ b) */
/* (a != b) ? (a & b) : a -> (a & b) */
/* (a != b) ? (a | b) : a -> (a | b) */
/* (a != b) ? min(a,b) : a -> min(a,b) */
/* (a != b) ? max(a,b) : a
We are going to support dynamic LMUL support.
gcc/ChangeLog:
* config/riscv/riscv-opts.h (enum riscv_autovec_lmul_enum): Add dynamic
enum.
* config/riscv/riscv.opt: Add dynamic compile option.
---
gcc/config/riscv/riscv-opts.h | 4 +++-
gcc/config/riscv/riscv.opt| 3 +++
2
On Thu, 31 Aug 2023 at 16:26, Christophe Lyon
wrote:
>
> As discussed in PR104167 (comments #8 and below), and PR111238, using
> -Wl,-gc-sections in the libstdc++ testsuite for arm-eabi
> (cross-toolchain) avoids link failures for a few tests:
>
> 27_io/filesystem/path/108636.cc
I think this one
On Thu, Aug 31, 2023 at 5:15 AM Richard Biener via Gcc-patches
wrote:
>
> On Thu, 31 Aug 2023, Filip Kastl wrote:
>
> > > The most obvious places would be right after SSA construction and before
> > > RTL expansion.
> > > Can you provide measurements for those positions?
> >
> > The algorithm
On Fri, 2023-09-01 at 00:04 +0200, priour...@gmail.com wrote:
> Hi,
>
> Succesfully regstrapped off trunk 7f2ed06ddc825e8a4e0edfd1d66b5156e6dc1d34
> on x86_64-linux-gnu.
>
> Is it OK for trunk ?
Hi Benjamin.
Thanks for the patch. It's OK as-is, but it doesn't cover every
case...
> Date: Thu, 31 Aug 2023 17:25:45 +0200
> From: Christophe Lyon via Gcc-patches
> As discussed in PR104167 (comments #8 and below), and PR111238, using
> -Wl,-gc-sections in the libstdc++ testsuite for arm-eabi
> (cross-toolchain) avoids link failures for a few tests:
>
>
Hi,
Thanks Sandra and Iain.
Patch pushed.
FX
On 8/31/23 15:14, Jakub Jelinek wrote:
On Thu, Aug 31, 2023 at 01:11:57PM -0400, Jason Merrill wrote:
2023-08-28 Jakub Jelinek
PR c++/111069
gcc/
* common.opt (fabi-version=): Document version 19.
* doc/invoke.texi (-fabi-version=): Likewise.
gcc/c-family/
*
since we have added COST framework, we by default enable VECT_COMPARE_COSTS.
Also, add 16/32/64 to provide more choices for COST comparison.
This patch doesn't change any behavior from the current testsuite since we are
using
default COST model.
gcc/ChangeLog:
*
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*cond_):
New combine pattern.
(*cond_): Ditto.
(*cond_): Ditto.
(*cond_trunc): Ditto.
* config/riscv/autovec.md (2): Adjust.
(2): Ditto.
gcc/testsuite/ChangeLog:
*
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*cond_):
New combine pattern.
(*cond_): Ditto.
(*cond_): Ditto.
(*cond_): Ditto.
(*cond_): Ditto.
(*cond_2): Ditto.
* config/riscv/autovec.md (2): Adjust.
(2): Adjust.
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*cond_extend):
New combine pattern.
(*cond_trunc): Ditto.
* config/riscv/autovec.md: Adjust.
* config/riscv/riscv-v.cc (needs_fp_rounding): Add FP extend.
gcc/testsuite/ChangeLog:
*
On Thu, Aug 31, 2023 at 03:09:52PM +0200, Marc Poulhiès wrote:
>
> Yang Yujie writes:
>
> Hello Yujie,
>
> > gcc/ChangeLog:
> >
> > * ada/Makefile.rtl: Add LoongArch support.
> > * ada/libgnarl/s-linux__loongarch.ads: New.
> > * ada/libgnat/system-linux-loongarch.ads: New.
> >
(Looks like this was committed as r14-3580-g597b9ec69bca8a)
> Cc: g...@gcc.gnu.org, gcc-patches@gcc.gnu.org, Eric Feng
> From: Eric Feng via Gcc
> gcc/testsuite/ChangeLog:
> PR analyzer/107646
> * gcc.dg/plugin/analyzer_cpython_plugin.c: Implements reference count
> * checking for
Brief version history of patch set:
v1 -> v2:
According to the GNU code specification, adjust the format of the
function implementation with "q" as the suffix function.
v2 - >v3:
1.On the LoongArch architecture, refer to the functionality of 64-bit
functions and modify the underlying
Hi,
these patchs support combining convert_op + vcond_mask to convert_op with mask
operand. The method is to keep the vector convert pattern simple (by changing
define_expand to define_insn_and_split) until the combine pass and introduce
the corresponding pattern to match the pattern after the
This patch change expand_cond_len_{unary,binop}'s argument `rtx_code code`
to `unsigned icode` and use the icode directly to determine whether the
rounding_mode operand is required.
gcc/ChangeLog:
* config/riscv/autovec.md: Adjust.
* config/riscv/riscv-protos.h
This pushes the conversion further down the chain which allows to optimize away
more
conversions in many cases.
OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.
PR tree-optimization/107765
PR tree-optimization/107137
gcc/ChangeLog:
* match.pd
From: Pan Li
This patch would like to allow the VLS mode autovec for the
floating-point binary operation ADD/SUB/MUL/DIV.
Given below code example:
test (float *out, float *in1, float *in2)
{
for (int i = 0; i < 128; i++)
out[i] = in1[i] + in2[i];
}
Before this patch:
test:
csrr
Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/
This patch updates the THEAD instructions to ensure that no insn is left
without a type attribute.
Tested for regressions using rv32/64 multilib for linux/newlib.
gcc/Changelog:
On Thu, 31 Aug 2023, Yujie Yang wrote:
> -If none of such suffix is present, the configured value of
> -@option{--with-multilib-default} can be used as a common default suffix
> -for all library ABI variants. Otherwise, the default build option
> -@code{-march=abi-default} is applied when
On Thu, 31 Aug 2023 at 18:42, Jonathan Wakely wrote:
>
> On Thu, 31 Aug 2023 at 16:26, Christophe Lyon
> wrote:
> >
> > As discussed in PR104167 (comments #8 and below), and PR111238, using
> > -Wl,-gc-sections in the libstdc++ testsuite for arm-eabi
> > (cross-toolchain) avoids link failures
Enalble zcmp for -Os and shrink-warp-separate for
the speed perfered optimization by default.
To force enabling zcmp multi push/pop in speed perfered case,
fno-shrink-wrap-separate has to be explictly given.
gcc/ChangeLog:
* config/riscv/riscv.cc
Enalble zcmp for -Os and shrink-warp-separate for
the speed perfered optimization by default.
Fei Gao (2):
allow targets to check shrink-wrap-separate enabled or not
[RISC-V] Enalble zcmp for -Os
gcc/config/riscv/riscv.cc | 21 -
gcc/shrink-wrap.cc
No functional changes but restructure and expose use_shrink_wrapping_separate
to the TARGETs.
gcc/ChangeLog:
* shrink-wrap.cc (try_shrink_wrapping_separate):call
use_shrink_wrapping_separate.
(use_shrink_wrapping_separate): wrap the condition
check in
On Thu, Aug 31, 2023 at 11:14:13AM +0800, Yujie Yang wrote:
> On Wed, Aug 30, 2023 at 09:36:22PM +, Joseph Myers wrote:
> > On Wed, 30 Aug 2023, Yang Yujie wrote:
> >
> > > +A suffix @code{[/ARCH][/OPTION]...]} may follow immediately after the ABI
> > > +identifier to customize the compiler
Hi Peter,
on 2023/8/31 06:42, Peter Bergner wrote:
> Commit r14-3258-ge7a36e4715c716 increased the amount of folding we perform,
> leading to better code. Update the expected instruction counts to match the
> the number of associated vec_* built-in calls.
>
> Tested on powerpc64le-linux with
On Wed, Aug 30, 2023 at 5:02 PM Andre Vieira (lists)
wrote:
>
>
>
> On 30/08/2023 14:01, Richard Biener wrote:
> > On Wed, Aug 30, 2023 at 11:15 AM Andre Vieira (lists) via Gcc-patches
> > wrote:
> >>
> >> This patch adds a machine_mode parameter to the TARGET_SIMD_CLONE_USABLE
> >> hook to
Tested and Bootstrapped and tested on x86_64-linux with no regressions.
There's a few test cases that are not properly diagnosed yet, but everything
that is known to fail is marked as xfail. When I tested the new tests I got 390
expected passes and 64 expected failures.
Alright, I have a flight
Brief version history of patch set:
v1 -> v2:
According to the GNU code specification, adjust the format of the
function implementation with "q" as the suffix function.
v2 - >v3:
1.On the LoongArch architecture, refer to the functionality of 64-bit
functions
and modify the underlying
Bootstrapped and tested on x86_64-linux with no regressions.
I would like to quickly thank everyone who helped me for their patience as I
learned the ropes of the codebase and toolchain. It is much appretiated and
this would
have been much much more difficult without the support.
This patch
on 2023/8/31 13:47, HAO CHEN GUI wrote:
> Kewen,
> I refined the patch according to your comments and it passed bootstrap
> and regression test.
>
> I committed it as
> https://gcc.gnu.org/g:946b8967b905257ac9f140225db744c9a6ab91be
Thanks! We want this to be backported, so it's also ok for
On Thu, 31 Aug 2023, Jiang, Haochen wrote:
> On Linux/x86_64,
>
> caa7a99a052929d5970677c5b639e1fa5166e334 is the first bad commit
> commit caa7a99a052929d5970677c5b639e1fa5166e334
> Author: Richard Biener
> Date: Wed Aug 30 11:57:47 2023 +0200
>
> tree-optimization/111228 - combine two
Hi!
As the following testcase shows, while check_local_shadow diagnoses most of
the [basic.scope.block]/2 violations, it doesn't diagnose when parameter's
name is redeclared inside of the compound-stmt of a function-try-block.
There is in that case an extra scope (sk_try with parent artificial
Thanks for the cleanup, the new interface is really much simpler than before!
Only few minor comment, you can go ahead to commit that after address
those comment.
(OK, I don't want to review whole patch again, it's really huge change :P
>
> - void set_rounding_mode (enum
On Wed, Aug 30, 2023 at 8:18 PM Richard Biener via Gcc-patches
wrote:
>
> On Wed, Aug 30, 2023 at 12:38 PM liuhongt via Gcc-patches
> wrote:
> >
> > r14-332-g24905a4bd1375c adjusts costing of emulated vectorized
> > gather/scatter.
> >
> > commit 24905a4bd1375ccd99c02510b9f9529015a48315
> >
From: Kong Lingling
In inline asm, we do not know if the insn can use EGPR, so disable EGPR
usage by default from mapping the common reg/mem constraint to non-EGPR
constraints. Use a flag mapx-inline-asm-use-gpr32 to enable EGPR usage
for inline asm.
gcc/ChangeLog:
*
From: Kong Lingling
Add -mapx-features= enumeration to separate subfeatures of APX_F.
-mapxf is treated same as previous ISA flag, while it sets
-mapx-features=apx_all that enables all subfeatures.
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (XSTATE_APX_F): New macro.
For vector move insns like vmovdqa/vmovdqu, their evex counterparts
requrire explicit suffix 64/32/16/8. The usage of these instruction
are prohibited under AVX10_1 or AVX512F, so for AVX2+APX_F we select
vmovaps/vmovups for vector load/store insns that contains EGPR.
gcc/ChangeLog:
*
From: Kong Lingling
Add backend helper functions to verify if a rtx_insn can adopt EGPR to
its base/index reg of memory operand. The verification rule goes like
1. For asm insn, enable/disable EGPR by ix86_apx_inline_asm_use_gpr32.
2. Disable EGPR for unrecognized insn.
3. If
From: Kong Lingling
Disable EGPR usage for below legacy insns in opcode map2/3 that have vex
but no evex counterpart.
insn list:
1. phminposuw/vphminposuw
2. ptest/vptest
3. roundps/vroundps, roundpd/vroundpd,
roundss/vroundss, roundsd/vroundsd
4. pcmpestri/vpcmpestri, pcmpestrm/vpcmpestrm
From: Kong Lingling
Current reload infrastructure does not support selective base_reg_class
for backend insn. Add insn argument to base_reg_class for
lra/reload usage.
gcc/ChangeLog:
* addresses.h (base_reg_class): Add insn argument.
Pass to MODE_CODE_BASE_REG_CLASS.
From: Kong Lingling
For APX, as we extended the GENERAL_REG_CLASS, new constraints are
needed to restrict insns that cannot adopt EGPR either in its reg or
memory operands.
gcc/ChangeLog:
* config/i386/constraints.md (h): New register constraint
for GENERAL_GPR16.
(Bt):
Intel Advanced performance extension (APX) has been released in [1].
It contains several extensions such as extended 16 general purpose registers
(EGPRs), push2/pop2, new data destination (NDD), conditional compare
(CCMP/CTEST) combined with suppress flags write version of common instructions
We only emit that on linux target before, that not problem before,
however Qemu has fix a bug to make qemu user mode honor PT_GNU_STACK[1],
that will cause problem when we test baremetal with qemu.
So the straightforward is enable that as well for non-linux toolchian,
the price is that will
On Thu, Aug 31, 2023 at 04:20:17PM +0800, Hongyu Wang via Gcc-patches wrote:
> From: Kong Lingling
>
> In inline asm, we do not know if the insn can use EGPR, so disable EGPR
> usage by default from mapping the common reg/mem constraint to non-EGPR
> constraints. Use a flag
On Thu, Aug 31, 2023 at 10:20 AM Hongyu Wang wrote:
>
> From: Kong Lingling
>
> These legacy insn in opcode map0/1 only support GPR16,
> and do not have vex/evex counterpart, directly adjust constraints and
> add gpr32 attr to patterns.
>
> insn list:
> 1. xsave/xsave64, xrstor/xrstor64
> 2.
Thanks for the testing work! I will continue to try to find and resolve
some subtle issues too (Such as use compiler to compile some large
project). I'm also curious about the partly saved register problem and
will take some learning and investigation in the future.
On Thu, 2023-08-31 at 17:41
On Thu, Aug 31, 2023 at 10:20 AM Hongyu Wang wrote:
>
> From: Kong Lingling
>
> Current reload infrastructure does not support selective base_reg_class
> for backend insn. Add insn argument to base_reg_class for
> lra/reload usage.
I don't think this is the correct approach. Ideally, a memory
Like base_reg_class, INDEX_REG_CLASS also does not support backend insn.
Add index_reg_class with insn argument for lra/reload usage.
gcc/ChangeLog:
* addresses.h (index_reg_class): New wrapper function like
base_reg_class.
* doc/tm.texi: Document INSN_INDEX_REG_CLASS.
This patch change the vsetvl policy to default policy
(returned by get_prefer_mask_policy and get_prefer_tail_policy) instead
fixed policy. Any policy is now returned, allowing change to agnostic
or undisturbed. In the future, users may be able to control the default
policy, such as keeping
LGTM
On Thu, Aug 31, 2023 at 5:07 PM Lehua Ding wrote:
>
> This patch change the vsetvl policy to default policy
> (returned by get_prefer_mask_policy and get_prefer_tail_policy) instead
> fixed policy. Any policy is now returned, allowing change to agnostic
> or undisturbed. In the future,
On 2023/08/31 18:10, Kito Cheng wrote:
> Hi Tsukasa:
>
> I guess you might did something wrong during commit this patch and
> "RISC-V: Add stub support for existing extensions"
>
> https://github.com/gcc-mirror/gcc/commit/f30d6a48635b5b180e46c51138d0938d33abd942
>
It's fine. That patch was a
Ok, I just went through the patchlist and found this patch seems
not committed yet, anyway I will mark this as commit now :)
On Thu, Aug 31, 2023 at 5:14 PM Tsukasa OI via Gcc-patches
wrote:
>
> On 2023/08/31 18:10, Kito Cheng wrote:
> > Hi Tsukasa:
> >
> > I guess you might did something wrong
On Thu, Aug 31, 2023 at 11:26 AM Richard Biener
wrote:
>
> On Thu, Aug 31, 2023 at 10:25 AM Hongyu Wang via Gcc-patches
> wrote:
> >
> > From: Kong Lingling
> >
> > Disable EGPR usage for below legacy insns in opcode map2/3 that have vex
> > but no evex counterpart.
> >
> > insn list:
> > 1.
On Thu, Aug 31, 2023 at 11:18 AM Jakub Jelinek via Gcc-patches
wrote:
>
> On Thu, Aug 31, 2023 at 04:20:17PM +0800, Hongyu Wang via Gcc-patches wrote:
> > From: Kong Lingling
> >
> > In inline asm, we do not know if the insn can use EGPR, so disable EGPR
> > usage by default from mapping the
The testcase requires hardware support for V2DImode vectors because
otherwise we do not rewrite inserts via BIT_FIELD_REF to
BIT_INSERT_EXPR. There's no effective target for this so the
following makes the testcase x86 specific, requiring and enabling SSE2.
Pushed.
*
Hi!
C++17 had in [basic.block.scope]/2
"A parameter name shall not be redeclared in the outermost block of the function
definition nor in the outermost block of any handler associated with a
function-try-block."
and in [basic.block.scope]/4 similar rule for selection/iteration
statements. My
From: Kong Lingling
These vex insn may have legacy counterpart that could support EGPR,
but they do not have evex counterpart. Split out its vex part from
patterns and set the vex part to non-EGPR supported by adjusting
constraints and attr_gpr32.
insn list:
1. vmovmskpd/vmovmskps
2. vpmovmskb
On Thu, Aug 31, 2023 at 06:02:36AM +, waffl3x via Gcc-patches wrote:
> From e485a79ec5656e72ba46053618843c3d69331eab Mon Sep 17 00:00:00 2001
> From: Waffl3x
> Date: Thu, 31 Aug 2023 01:05:25 -0400
> Subject: [PATCH] P0847R7 (deducing this) Initial support
>
> Most things should be
On Thu, Aug 31, 2023 at 10:06 AM Hongtao Liu wrote:
>
> On Wed, Aug 30, 2023 at 8:18 PM Richard Biener via Gcc-patches
> wrote:
> >
> > On Wed, Aug 30, 2023 at 12:38 PM liuhongt via Gcc-patches
> > wrote:
> > >
> > > r14-332-g24905a4bd1375c adjusts costing of emulated vectorized
> > >
On Thu, Aug 31, 2023 at 10:22 AM Hongyu Wang via Gcc-patches
wrote:
>
> Intel Advanced performance extension (APX) has been released in [1].
> It contains several extensions such as extended 16 general purpose registers
> (EGPRs), push2/pop2, new data destination (NDD), conditional compare
>
On Thu, Aug 31, 2023 at 04:20:19PM +0800, Hongyu Wang via Gcc-patches wrote:
> For vector move insns like vmovdqa/vmovdqu, their evex counterparts
> requrire explicit suffix 64/32/16/8. The usage of these instruction
> are prohibited under AVX10_1 or AVX512F, so for AVX2+APX_F we select
>
Could you rebase the patch again, it seems got some conflict with zcmt
which I commit in the past few days...
On Wed, Aug 30, 2023 at 9:54 AM Lehua Ding wrote:
>
> Because functions which follow vector calling convention variant has
> callee-saved vector reigsters but functions which follow
Committed, thanks Kito.
On 2023/8/31 17:13, Kito Cheng via Gcc-patches wrote:
LGTM
On Thu, Aug 31, 2023 at 5:07 PM Lehua Ding wrote:
This patch change the vsetvl policy to default policy
(returned by get_prefer_mask_policy and get_prefer_tail_policy) instead
fixed policy. Any policy is now
On Thu, 2023-08-31 at 15:02 +0800, chenxiaolong wrote:
> +;; Implement __builtin_copysignf128 function.
> +
> +(define_insn_and_split "copysigntf3"
> + [(set (match_operand:TF 0 "register_operand" "=")
> + (unspec:TF [(match_operand:TF 1 "register_operand" "r")
> +
From: Kong Lingling
The APX enabled hardware should also be AVX10 enabled, thus for map2/3 insns
with evex counterpart, we assume auto promotion to EGPR under APX_F if the
insn uses GPR32. So for below insns, we disabled EGPR usage for their sse
mnenomics, while allowing egpr generation of their
From: Kong Lingling
Extend GENERAL_REGS with extra r16-r31 registers like REX registers,
named as REX2 registers. They will only be enabled under
TARGET_APX_EGPR.
gcc/ChangeLog:
* config/i386/i386-protos.h (x86_extended_rex2reg_mentioned_p):
New function prototype.
*
From: Kong Lingling
These legacy insns in opcode map2/3 have vex but no evex
counterpart, disable EGPR for them by adjusting alternatives and
attr_gpr32.
insn list:
1. phaddw/vphaddw, phaddd/vphaddd, phaddsw/vphaddsw
2. phsubw/vphsubw, phsubd/vphsubd, phsubsw/vphsubsw
3. psignb/vpsginb,
From: Kong Lingling
These legacy insn in opcode map0/1 only support GPR16,
and do not have vex/evex counterpart, directly adjust constraints and
add gpr32 attr to patterns.
insn list:
1. xsave/xsave64, xrstor/xrstor64
2. xsaves/xsaves64, xrstors/xrstors64
3. xsavec/xsavec64
4.
在 2023-08-31四的 15:57 +0800，Xi Ruoyao写道：
> On Thu, 2023-08-31 at 15:02 +0800, chenxiaolong wrote:
> > +;; Implement __builtin_copysignf128 function.
> > +
> > +(define_insn_and_split "copysigntf3"
> > + [(set (match_operand:TF 0 "register_operand" "=")
> > + (unspec:TF [(match_operand:TF 1
Committed after addressing these comments.
Many thanks to Kito for taking the time to review such a large patch :)
On 2023/8/31 15:51, Kito Cheng wrote:
Thanks for the cleanup, the new interface is really much simpler than before!
Only few minor comment, you can go ahead to commit that after
This is an update of:
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628303.html
Changes since last version of patch set:
- "dg-skip-if"-related Changes of the g++.dg/torture/vshuf* testcases are
reverted.
(Replaced by __builtin_shuffle fix)
- Add fix of __builtin_shuffle() for Loongson
Hi Tsukasa:
I guess you might did something wrong during commit this patch and
"RISC-V: Add stub support for existing extensions"
https://github.com/gcc-mirror/gcc/commit/f30d6a48635b5b180e46c51138d0938d33abd942
On Tue, Aug 29, 2023 at 4:55 PM Tsukasa OI via Gcc-patches
wrote:
>
> On
Hi Lehua,
thanks, this definitely goes into the direction of what I had in mind and
simplifies a lot of the reduntant emit_... so it's good to have it.
I was too slow for a detailed response :) So just some high-level comments.
One thing I noticed is the overloading of "MASK_OP", we use it as
On Thu, Aug 31, 2023 at 10:25 AM Hongyu Wang via Gcc-patches
wrote:
>
> From: Kong Lingling
>
> Disable EGPR usage for below legacy insns in opcode map2/3 that have vex
> but no evex counterpart.
>
> insn list:
> 1. phminposuw/vphminposuw
> 2. ptest/vptest
> 3. roundps/vroundps,
On Thu, Aug 31, 2023 at 11:26:26AM +0200, Richard Biener wrote:
> On Thu, Aug 31, 2023 at 10:25 AM Hongyu Wang via Gcc-patches
> wrote:
> >
> > From: Kong Lingling
> >
> > Disable EGPR usage for below legacy insns in opcode map2/3 that have vex
> > but no evex counterpart.
> >
> > insn list:
> >
On Thu, 2023-08-31 at 17:08 +0800, Chenghui Pan wrote:
> This is an update of:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628303.html
>
> Changes since last version of patch set:
> - "dg-skip-if"-related Changes of the g++.dg/torture/vshuf* testcases are
> reverted.
> (Replaced by
Hi Robin,
Thanks for these comments.
On 2023/8/31 17:16, Robin Dapp wrote:
Hi Lehua,
thanks, this definitely goes into the direction of what I had in mind and
simplifies a lot of the reduntant emit_... so it's good to have it.
I was too slow for a detailed response :) So just some
Hi,
on some targets we fail to vectorize with the first type the vectorizer
tries but succeed with the second. This patch changes several regex
patterns to reflect that behavior.
Before we would look for a single occurrence of e.g.
"vect_recog_dot_prod_pattern" but would possible find two (one
On Thu, 31 Aug 2023, Robin Dapp wrote:
> Hi,
>
> on some targets we fail to vectorize with the first type the vectorizer
> tries but succeed with the second. This patch changes several regex
> patterns to reflect that behavior.
>
> Before we would look for a single occurrence of e.g.
>
On Thu, Aug 31, 2023 at 12:27 AM Andrew Pinski via Gcc-patches
wrote:
>
> This simple patch extends the min_value/max_value match to vector integer
> types.
> Using uniform_integer_cst_p makes this easy.
>
> OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.
>
> The testcases
Before optimization, the operation of taking fixed-point numbers from memory
and then forcing type conversion needs to be loaded into fixed-point registers
before conversion. After the optimization is completed, the fixed-point value
is directly transferred to the floating-point register for type
> The most obvious places would be right after SSA construction and before RTL
> expansion.
> Can you provide measurements for those positions?
The algorithm should only remove PHIs that break SSA form minimality. Since
GCC's SSA construction already produces minimal SSA form, the algorithm
Hi FX,
+Sandra
> On 31 Aug 2023, at 12:13, FX Coudert wrote:
>
> This patch homogenizes to some extent the use of “Mac OS X” or “OS X” or “Mac
> OS” in the gcc/ folder to “macOS”, which is the modern way of writing it. It
> is not a global replacement though, and each use was audited.
>
> -
This patch removes zero extension from vctzlsbb as it already zero extends.
Bootstrapped and regtested on powerpc64-linux-gnu.
Thanks & Regards
Ajit
rs6000: unnecessary clear after vctzlsbb in vec_first_match_or_eos_index
For rs6000 target we dont need zero_extend after vctzlsbb as vctzlsbb
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