[PATCH] Fix coroutine tests for libstdc++ gnu-version-namespace mode

I'm eventually fixing those tests the same way we manage this problem in libstdc++ testsuite.    testsuite: Add optional libstdc++ version namespace in expected diagnostic     When libstdc++ is build with --enable-symvers=gnu-versioned-namespace diagnostics are     showing this namespace,

[PATCH 1/1] gcc/d: add LoongArch64 support for D frontend

gcc/ChangeLog: * config.gcc: add loongarch-d.o to d_target_objs for LoongArch architecture. gcc/config/ChangeLog: * loongarch/loongarch-d.cc (loongarch_d_target_versions): add interface function to define builtin D versions for LoongArch architecture.

[PATCH 0/1] Add LoongArch64 support for D frontend

This patch adds the LoongArch64 support for GCC D frontend. The runtime support is submitted as a separate patch here: https://github.com/dlang/dmd/pull/15628. You can find more information about the LoongArch architecture on this website:

[PATCH 0/1] Add LoongArch64 support for D frontend

From: Zixing Liu This patch adds the LoongArch64 support for GCC D frontend. The runtime support is submitted as a separate patch here: https://github.com/dlang/dmd/pull/15628. You can find more information about the LoongArch architecture on this website:

[PATCH 1/1] gcc/d: add LoongArch64 support for D frontend

gcc/ChangeLog: * config.gcc: add loongarch-d.o to d_target_objs for LoongArch architecture. gcc/config/ChangeLog: * loongarch/loongarch-d.cc (loongarch_d_target_versions): add interface function to define builtin D versions for LoongArch architecture.

[PATCH] RISC-V: Fix AVL/VL bug of VSETVL PASS[PR111548]

This patch fixes that AVL/VL reg incorrect fetch in VSETVL PASS. C/C++ regression passed. But gfortran didn't run yet. I am still finding a way to run it. Will commit it when I pass the fortran regression. PR target/111548 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc

Re: RISC-V: Added support for CRC.

Mariam Harutyunyan: +++ b/gcc/ChangeLog @@ -1,3 +1,45 @@ +2023-08-03 Mariam Arutunian + It is common courtesy to include all authors in the list of authors for the ChangeLog; also, this may help people in the future understand the history of the code better. While must of your patch is new, it

[PATCH] MATCH: Add `(X & ~Y) & Y` and `(X | ~Y) | Y`

Even though this gets optimized by reassociation, catching it more often will always be better. Note the reason why I didn't add `(X ^ ~Y) ^ Y` is that it gets caught by prefering `~(X ^ Y)` to `(X ^ ~Y)` which then it is caught by the the pattern for `(X ^ Y) ^ Y` already. PR

Re: [PATCH v1] RISC-V: Remove FP run test for ceil.

I guess it just needs more checks than `target { riscv_vector }`, maybe something like `target { riscv_vector_zvfh }`, but anyway I am fine to drop this for now. On Sat, Sep 23, 2023 at 2:11 AM Li, Pan2 wrote: > > Committed, thanks Juzhe. > > > > Pan > > > > From: 钟居哲 > Sent: Saturday,

[committed] d: Merge upstream dmd, druntime 4574d1728d, phobos d7e79f024.

Hi, This patch merges the D front-end and run-time library with upstream dmd 4574d1728d, and standard library with phobos d7e79f024. Updating the latest changes from the v2.105.0 release. D front-end changes: - Import dmd v2.105.0. - Catch clause must take only `const' or

Re: [PATCH v4] c++: Check for indirect change of active union member in constexpr [PR101631,PR102286]

On Sat, 23 Sept 2023, 01:39 Nathaniel Shead via Libstdc++, < libstd...@gcc.gnu.org> wrote: > Now that bootstrap has finished, I have gotten regressions in the > following libstdc++ tests: > > Running libstdc++:libstdc++-dg/conformance.exp ... > FAIL: 20_util/bitset/access/constexpr.cc

Re: [PATCH 2/2] RISC-V: Add support for XCValu extension in CV32E40P

Hi Mary: Several inline comments, mostly are related to the RTX pattern. I guess we don't really need those unspec except clip*. > diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md > index 59aeafe485f..30c8bcbe476 100644 > --- a/gcc/config/riscv/corev.md > +++

[PATCH] libstdc++: Ensure active union member is correctly set

On Sat, Sep 23, 2023 at 07:40:48AM +0100, Jonathan Wakely wrote: > On Sat, 23 Sept 2023, 01:39 Nathaniel Shead via Libstdc++, < > libstd...@gcc.gnu.org> wrote: > > > Now that bootstrap has finished, I have gotten regressions in the > > following libstdc++ tests: > > > > Running

RE: [PATCH v1] RISC-V: Remove FP run test for ceil.

Sure, will re-visit this part later. Pan -Original Message- From: Kito Cheng Sent: Saturday, September 23, 2023 3:47 PM To: Li, Pan2 Cc: 钟居哲 ; gcc-patches ; Wang, Yanzhang Subject: Re: [PATCH v1] RISC-V: Remove FP run test for ceil. I guess it just needs more checks than `target {

Re: [PATCH] libstdc++: Ensure active union member is correctly set

On Sat, 23 Sept 2023, 08:30 Nathaniel Shead, wrote: > On Sat, Sep 23, 2023 at 07:40:48AM +0100, Jonathan Wakely wrote: > > On Sat, 23 Sept 2023, 01:39 Nathaniel Shead via Libstdc++, < > > libstd...@gcc.gnu.org> wrote: > > > > > Now that bootstrap has finished, I have gotten regressions in the >

[PATCH v1] RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init

From: Pan Li When broadcast the reperated element, we take the mask machine mode by mistake. This patch would like to fix it by leveraging the machine mode of the element. The below test case in RV32 will be fixed. * gcc/testsuite/gfortran.dg/overload_5.f90 PR target/111546

[PATCH v2] RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init

From: Pan Li When broadcast the reperated element, we take the mask_int_mode by mistake. This patch would like to fix it by leveraging the machine mode of the element. The below test case in RV32 will be fixed. * gcc/testsuite/gfortran.dg/overload_5.f90 PR target/111546

Re: [PATCH v1] RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init

The codes here are quite confusing. Plz rename it: /* We can't use BIT mode (BI) directly to generate mask = 0b01010... since we don't have such instruction in RVV. Instead, we should use INT mode (QI/HI/SI/DI) with integer move instruction to generate the mask data we want. */