Hi Jeff,
Thanks for your comments.
在 2024/3/4 6:02, Jeff Law 写道:
> Why specifically are you worried here? Propagation of a volatile shouldn't
> in and of itself cause a problem. We're not changing the number of volatile
> accesses or anything like that -- we're just moving them around a
The constraint of op[1] is inconsistent with the output template.
gcc/ChangeLog:
* config/loongarch/loongarch.md
(define_insn "*sge_"): Fix inconsistency
error.
---
gcc/config/loongarch/loongarch.md | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
On 3/3/24 19:56, HAO CHEN GUI wrote:
Hi Jeff,
Thanks for your comments.
在 2024/3/4 6:02, Jeff Law 写道:
Why specifically are you worried here? Propagation of a volatile shouldn't in
and of itself cause a problem. We're not changing the number of volatile
accesses or anything like that
On 2/9/24 03:26, Richard Biener wrote:
The following allows a base term to be derived from an existing
MEM_EXPR, notably the points-to set of a MEM_REF base. For the
testcase in the PR this helps RTL DSE elide stores to a stack
temporary. This covers pointers to NONLOCAL which can be mapped
Could you rebase to the trunk ? I don't think segment load store cost depends
on previous patch you sent.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-03-01 23:07
To: 钟居哲; gcc-patches; palmer; kito.cheng
CC: rdapp.gcc; Jeff Law
Subject: Re: [PATCH] RISC-V: Add initial cost handling for
On 3/1/24 17:29, Sandra Loosemore wrote:
On 3/1/24 08:23, Tobias Burnus wrote:
Aside: Shouldn't all the HTML documents start with a and
before
the table of content? Currently, it has:
Top (GNU libgomp)
and the body starts with
Short Table of Contents
I think this is a bug in the
ChangeLog:
* MAINTAINERS: Add myself
Signed-off-by: demin.han
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b01fab16061..a681518d704 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -448,6 +448,7 @@ Wei Guozhi
Excerpts from Richard Biener's message of März 3, 2024 11:41 am:
>
>
>> Am 03.03.2024 um 02:51 schrieb Iain Buclaw :
>>
>> Hi,
>>
>> This patch fixes a wrong code issue in the D front-end where lowered
>> struct comparisons would reinterpret fields with a different (usually
>> bigger)
Hi Harald,
Please find an updated version of the patch that rolls in Steve's patch for
PR114141, fixes unlimited polymorphic function selectors and cures the
memory leaks. I apologise for not working on this sooner but, as I informed
you, I have been away for an extended trip to Australia.
The
Hello, gentle maintainer.
This is a message from the Translation Project robot.
A revised PO file for textual domain 'gcc' has been submitted
by the Swedish team of translators. The file is available at:
https://translationproject.org/latest/gcc/sv.po
(This file,
On 2/29/24 01:35, Richard Biener wrote:
The following amends the PR114070 fix to optimistically allow
the folding when we cannot expand the current vec_cond using
vcond_mask and we're still before vector lowering. This leaves
a small window between vectorization and lowering where we could
Removed the last cc0 remains.
Johann
--
AVR: ad target/92792 - Remove insn attribute "cc" and its (dead) uses.
The backend has remains of cc0 condition code. Unfortunately,
all that information is useless with CCmode, and their use was
removed with the removal of NOTICE_UPDATE_CC in PR92729
> Am 03.03.2024 um 13:56 schrieb Roger Sayle :
>
>
> This patch fixes PR target/114187 a typo/missed-optimization in simplify-rtx
> that's exposed by (my) changes to x86_64's parameter passing. The context
> is that construction of double word (TImode) values now uses the idiom:
>
>
This addendum ports a corner case optimization from -mno-fuse-add
to -mfuse-add: When a base register needs temporal adjustment,
and the base is the frame pointer, then there are cases where the
post-adjustment is not needed.
Passes without new regressions on ATtiny40.
Johann
--
AVR: ad
This patch fixes PR target/114187 a typo/missed-optimization in simplify-rtx
that's exposed by (my) changes to x86_64's parameter passing. The context
is that construction of double word (TImode) values now uses the idiom:
(ior:TI (ashift:TI (zero_extend:TI (reg:DI x)) (const_int 64 [0x40]))
> Am 03.03.2024 um 02:51 schrieb Iain Buclaw :
>
> Hi,
>
> This patch fixes a wrong code issue in the D front-end where lowered
> struct comparisons would reinterpret fields with a different (usually
> bigger) alignment than the original. Use `build_aligned_type' to
> preserve the alignment
On 3/3/24 12:43, Uros Bizjak wrote:
umuldi3_highpart expander does:
if (REG_P (operands[2]))
operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]);
on register_operand predicate, which also allows SUBREG RTX. So,
subregs were emitted without ZERO_EXTEND RTX.
But nowadays we
On Sat, Mar 2, 2024 at 5:51 PM Iain Buclaw wrote:
>
> Hi,
>
> This patch fixes a wrong code issue in the D front-end where lowered
> struct comparisons would reinterpret fields with a different (usually
> bigger) alignment than the original. Use `build_aligned_type' to
> preserve the alignment
This is a no-op patch that uses some more C++ / C99
features if possible.
Johann
--
AVR: Use more C++ ish coding style.
gcc/
* config/avr/avr.cc: Resolve ATTRIBUTE_UNUSED.
Use bool in place of int for boolean logic (if possible).
Move declarations to definitions (if
umuldi3_highpart expander does:
if (REG_P (operands[2]))
operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]);
on register_operand predicate, which also allows SUBREG RTX. So,
subregs were emitted without ZERO_EXTEND RTX.
But nowadays we have UMUL_HIGHPART that allows us to fix this
On 2/29/24 00:06, Xi Ruoyao wrote:
The vect_int_mod target selector is evaluated with the options in
DEFAULT_VECTCFLAGS in effect, but these options are not automatically
passed to tests out of the vect directories. So this test fails on
targets where integer vector modulo operation is
On 2/25/24 20:30, HAO CHEN GUI wrote:
Hi,
This patch tries to fix a potential problem which is raised by the patch
for PR111267. The volatile asm operand tries to be propagated to a single
set insn with the patch for PR111267. It has potential risk as the behavior
is wrong. Currently
Hi,
This patch merges the D front-end and runtime library with upstream dmd
f8bae04558, and the standard library with phobos ba2ade9dec
D front-end changes:
- Import dmd v2.108.1-beta-1.
D runtime changes:
- Import druntime v2.108.1-beta-1.
Phobos changes:
- Import phobos
On 2/29/24 06:28, Robin Dapp wrote:
On 2/29/24 02:38, Li, Pan2 wrote:
So it's going to check if V2SF can be tied to DI and V4QI with SI. I
suspect those are going to fail for RISC-V as those aren't tieable.
Yes, you are right. Different REG_CLASS are not allowed to be tieable in RISC-V.
Excerpts from Andrew Pinski's message of März 3, 2024 11:49 pm:
> On Sat, Mar 2, 2024 at 5:51 PM Iain Buclaw wrote:
>>
>> Hi,
>>
>> This patch fixes a wrong code issue in the D front-end where lowered
>> struct comparisons would reinterpret fields with a different (usually
>> bigger) alignment
Hi All,
The following patch has been bootstrapped and regtested on powerpc64le-linux.
When we expand the __builtin_vsx_splat_2di function, we were allowing immediate
value for second operand which causes an
Hi,
On Sat, Feb 24, 2024 at 06:42:58PM +0100, Mark Wielaard wrote:
> On Thu, Feb 22, 2024 at 11:57:50AM +0800, YunQiang Su wrote:
> > Mark Wielaard 于2024年2月19日周一 06:58写道：
> > > So, I did try the regenerate-opt-urls locally, and it did generate the
> > > attached diff. Which seems to show we
Hi Paul,
welcome back!
On 3/3/24 17:04, Paul Richard Thomas wrote:
Hi Harald,
Please find an updated version of the patch that rolls in Steve's patch for
PR114141, fixes unlimited polymorphic function selectors and cures the
memory leaks. I apologise for not working on this sooner but, as I
Came across this issue while working on another PR.
Bootstrapped and regtested on x86_64-pc-linux-gnu, OK for trunk?
Or otherwise for GCC 15?
-- >8 --
Currently a using-declaration bringing a name into its own namespace is
a no-op, except for functions. This prevents people from being able to
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