Re: [PATCH] Make cp_fold more consistent in its output caching

On Tue, May 31, 2016 at 3:00 PM, Patrick Palka wrote: > Some code paths of cp_fold return early instead of falling through to > the end of the function and so in these cases we fail to cache the > return value of the function into the fold_cache. > > This patch splits

[PATCH], Add PowerPC ISA 3.0 MTVSRDD support

This patch adds support to issue the MTVSRDD on 64-bit ISA 3.0 systems when the compiler has a 64-bit value in a GPR, and it wants to create a vector that has the 64-bit value in both sides of the 128-bit value. In addition, I simplified the alternatives, eliminating the use of separate

[PATCH], PR target/71186, Fix PowerPC splat error

Anton Blanchard found that in some cases, setting V4SImode and V8HImode vector registers to all 0's or all 1's could cause the compiler issue an 'insn does not satisfy its constraints' error message. The reason was, 0/-1 treated specially, since we can generate them using normal ISA 2.06/2.07

Separate loop exit predictor from extra exit predictor

Hi, predict_extra_loop_exits contains poor man's jump threading code for loop exit conditionals pattern matching the following: if (foo() || global > 10) break; This will be translated into: BB3: loop header... BB4: if foo() goto BB6 else goto BB5 BB5: if

Re: [PATCH] integer overflow checking builtins in constant expressions

On 05/31/2016 03:50 PM, Jakub Jelinek wrote: On Sun, May 01, 2016 at 10:39:48AM -0600, Martin Sebor wrote: --- a/gcc/builtins.c +++ b/gcc/builtins.c @@ -7878,50 +7878,101 @@ fold_builtin_unordered_cmp (location_t loc, tree fndecl, tree arg0, tree arg1, static tree

Re: Remove the unused OMP_CLAUSE_DEVICE_RESIDENT

On 05/31/2016 08:45 AM, Thomas Schwinge wrote: > While working on something else, I came across the following. Cesar, can > you please verify that this is really dead code in the Fortran front end, > which currently is the only producer of OMP_CLAUSE_DEVICE_RESIDENT? You're correct. Declare

Re: [PATCH] c++/60760 - arithmetic on null pointers should not be allowed in constant expressions

On 05/17/2016 01:44 PM, Jason Merrill wrote: On 05/12/2016 06:34 PM, Martin Sebor wrote: Attached is a resubmission of the patch for c++/60760 originally submitted late in the 6.0 cycle along with a patch for c++/67376. Since c++/60760 was not a regression, it was decided that it would be safer

Re: [PATCH] integer overflow checking builtins in constant expressions

On Sun, May 01, 2016 at 10:39:48AM -0600, Martin Sebor wrote: > --- a/gcc/builtins.c > +++ b/gcc/builtins.c > @@ -7878,50 +7878,101 @@ fold_builtin_unordered_cmp (location_t loc, tree > fndecl, tree arg0, tree arg1, > > static tree > fold_builtin_arith_overflow (location_t loc, enum

Re: [PATCH] integer overflow checking builtins in constant expressions

On Tue, May 31, 2016 at 05:31:48PM -0400, Jason Merrill wrote: > >I'm not quite sure where to move this hunk so that it could be > >shared or with what. > > > >With the patch, fold_builtin_arith_overflow returns the overflow > >bit alone when the last argument is null. Otherwise it returns > >a

Re: [PATCH] integer overflow checking builtins in constant expressions

On 05/31/2016 04:48 PM, Martin Sebor wrote: On 05/17/2016 12:54 PM, Jason Merrill wrote: On 05/01/2016 12:39 PM, Martin Sebor wrote: + if (TREE_CODE (arg0) == INTEGER_CST && TREE_CODE (arg1) == INTEGER_CST) +{ + if (tree result = size_binop_loc (EXPR_LOC_OR_LOC (t, input_location), +

Re: [PATCH] Fix missing/wrong function declaration in s-osinte-rtems.ads (ada/71317)

> I attached a patch for 5 branch which will only add the > clock_getres-function. Thanks, applied too. -- Eric Botcazou

Re: [PATCH] Fix missing/wrong function declaration in s-osinte-rtems.ads (ada/71317)

Am Dienstag, 31. Mai 2016, 21:00:07 CEST schrieb Eric Botcazou: > > this patch fixes the build failures of recent gnat compiler version for > > RTEMS targets (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71317). > > Attached are patches for trunk, gcc-5-branch and gcc-6-branch. > > I don't have

Re: Moving backwards/FSM threader into its own pass

On 05/31/2016 11:38 AM, Richard Biener wrote: Essentially we want to limit the backwards substitution to single step within a single block for that case (which is trivially easy). That would allow us to run a very cheap threader during early optimizations. Just do double check - the pass

Re: Thoughts on memcmp expansion (PR43052)

On 05/13/2016 10:40 PM, Joseph Myers wrote: On Fri, 13 May 2016, Bernd Schmidt wrote: Thanks. So, this would seem to suggest that BITS_PER_UNIT in memcmp/memcpy expansion is more accurate than a plain 8, although pedantically we might want to use CHAR_TYPE_SIZE? Should I adjust my patch to use

Re: [PATCH] integer overflow checking builtins in constant expressions

On 05/17/2016 12:54 PM, Jason Merrill wrote: On 05/01/2016 12:39 PM, Martin Sebor wrote: + if (TREE_CODE (arg0) == INTEGER_CST && TREE_CODE (arg1) == INTEGER_CST) +{ + if (tree result = size_binop_loc (EXPR_LOC_OR_LOC (t, input_location), +opcode, arg0, arg1)) +

Re: [PATCH 4/4] C: add fixit hint to misspelled field names

Ping: https://gcc.gnu.org/ml/gcc-patches/2016-04/msg01834.html On Thu, 2016-04-28 at 10:28 -0400, David Malcolm wrote: > Similar to the C++ case, but more involved as the location of the > pertinent token isn't readily available. The patch adds it as a > param > to build_component_ref. All

Re: Record likely upper bounds for loops

On May 27, 2016 1:14:09 PM GMT+02:00, Jan Hubicka wrote: >+ fprintf (dump_file, "Loop likely %d iterates at most %i >times.\n", loop->num, >+ (int)likely_max_loop_iterations_int (loop)); s/Loop likely %d/Loop %d likely/ please. thanks,

[patch, fortran] PR52393 I/O: "READ format" statement with parenthesized default-char-expr

The attached patch fixes this by adding code to match a default character expression if the left paren is first matched on a READ statement. If the expression is matched the dt-format is set and processing continues. Otherwise execution drops through to match a control list as usual. Regression

C++ PATCH for c++/60095, partial specialization of variable template

In the implementation of partially specialized variable templates, we decided to put the partial specialization template and args in DECL_TEMPLATE_INFO rather than the general template and args as we do for classes. This decision came out of the fact that for variables, we need to decide what

[PATCH] Make cp_fold more consistent in its output caching

Some code paths of cp_fold return early instead of falling through to the end of the function and so in these cases we fail to cache the return value of the function into the fold_cache. This patch splits cp_fold into two functions, with the wrapper function being responsible for caching the

Re: [PATCH] Fix missing/wrong function declaration in s-osinte-rtems.ads (ada/71317)

> this patch fixes the build failures of recent gnat compiler version for > RTEMS targets (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71317). > Attached are patches for trunk, gcc-5-branch and gcc-6-branch. > I don't have write access to the svn, so if the patches pass the review > process

Re: [PATCH 3/3][AArch64] Emit division using the Newton series

On 05/31/16 04:27, James Greenhalgh wrote: On Fri, May 27, 2016 at 05:57:30PM -0500, Evandro Menezes wrote: On 05/25/16 11:16, James Greenhalgh wrote: On Wed, Apr 27, 2016 at 04:15:53PM -0500, Evandro Menezes wrote: gcc/ * config/aarch64/aarch64-protos.h (tune_params):

[gomp4.5] Add support for target {enter,exit} data translation, some map clause diagnostics

Hi! No testcases yet, tested on x86_64-linux, committed to gomp-4_5-branch. 2016-05-31 Jakub Jelinek * trans-openmp.c (gfc_trans_omp_target_enter_data, gfc_trans_omp_target_exit_data): New functions. (gfc_trans_omp_directive): Handle

Re: [gotools, libcc1] Update copyright dates

Rainer Orth writes: > I noticed that libcc1 copyright dates hadn't been updated since it had > initially been added. Looking around, the same applies to gotools. > > This patch updates update-copyright.py to take care of that. At the > same time, I checked that

Re: [patch] Fix segfault in vectorizer

> This code appears when we try to disable boolean patterns. Boolean patterns > replace booleans with integers of proper size which allow us to simply > determine vectype using get_vectype_for_scalar_type. With no such > replacement we can't determine vectype just out of a scalar type (there are

Re: [C++ Patch] PR 70972 ("[6/7 Regression] Inheriting constructors taking parameters by value should move them, not copy")

On Tue, May 31, 2016 at 12:29 PM, Paolo Carlini wrote: > Hi, > > On 23/05/2016 19:32, Jason Merrill wrote: >> >> OK. > > What about gcc-6-branch? Assuming no issues show up in mainline I think we > want it there too in time for 6.2, right? Definitely. Jason

Re: [PATCH] c++/67376 Comparison with pointer to past-the-end, of array fails inside constant expression

On Tue, May 31, 2016 at 1:18 PM, Martin Sebor wrote: > On 03/31/2016 11:54 AM, Jason Merrill wrote: >> >> OK, thanks. > > This bug was fixed in 6.1 but it is also a GCC 5 regression and > the patch hasn't been applied there yet. Should I go ahead and > backport it to the 5.x

Re: Moving backwards/FSM threader into its own pass

On May 31, 2016 4:55:36 PM GMT+02:00, Jeff Law wrote: >On 05/30/2016 03:16 AM, Richard Biener wrote: >> >> Ok, but the placement (and number of) threading passes then no longer >depends >> on DOM/VRP passes - and as you placed the threading passes _before_ >those >> passes the

Re: [PATCH] c++/67376 Comparison with pointer to past-the-end, of array fails inside constant expression

On 03/31/2016 11:54 AM, Jason Merrill wrote: OK, thanks. This bug was fixed in 6.1 but it is also a GCC 5 regression and the patch hasn't been applied there yet. Should I go ahead and backport it to the 5.x branch? Martin

Re: [AArch64][3/4] Don't generate redundant checks when there is no composite arg

On Fri, May 06, 2016 at 04:00:40PM +0100, Jiong Wang wrote: > 2016-05-06 Jiong Wang > > gcc/ > * config/aarch64/aarch64.c (aarch64_gimplify_va_arg_expr): Avoid > duplicated check code. > > gcc/testsuite/ > * gcc.target/aarch64/va_arg_4.c: New testcase. I wonder

[PATCH] Fix PR ada/71358

This fixes a minor problem where GNAT.Command_Line.Getopt raises CE if there are in fact no program-specified options (only the internally-supplied -h, --help are meant to be available). Tested on GCC 6.1.0, x86_64-apple-darwin15. If OK, can someone commit it (I can't). gcc/ada/Changelog:

Re: [C++ Patch] PR 70972 ("[6/7 Regression] Inheriting constructors taking parameters by value should move them, not copy")

Hi, On 23/05/2016 19:32, Jason Merrill wrote: OK. What about gcc-6-branch? Assuming no issues show up in mainline I think we want it there too in time for 6.2, right? Thanks, Paolo.

Re: ]PATCH][RFC] Initial patch for better performance of 64-bit math instructions in 32-bit mode on x86-64

On Tue, May 31, 2016 at 5:00 PM, Yuri Rumyantsev wrote: > Hi Uros, > > Here is initial patch to improve performance of 64-bit integer > arithmetic in 32-bit mode. We discovered that gcc is significantly > behind icc and clang on rsa benchmark from eembc2.0 suite. > Te problem

[PCH] Add GTY marker

A bunch of PCH tests fail for a PTX target, due to a difference in debug data. It turned out that object pointed to by cur_line_info_table was poisoned by PCH reading, and this led to an is_stmt being emitted erroneously. My suspicion is that ports that support section switching update

[SH][committed] Use default ASM_OUTPUT_SYMBOL_REF

Hi, Since the SH5 stuff is gone, there's no need to override the ASM_OUTPUT_SYMBOL_REF target macro anymore. Tested on sh-elf with make -k check RUNTESTFLAGS="--target_board=sh-sim\{-m2/-ml,-m2/-mb, -m2a/-mb,-m4/-ml,-m4/-mb,-m4a/-ml,-m4a/-mb}" Committed as r236930. Cheers, Oleg

[SH][committeð] Remove SH5 target regs leftovers

Hi, The attached patch removes the SH5 target register leftovers. Tested on sh-elf with make -k check RUNTESTFLAGS="--target_board=sh-sim\{-m2/-ml,-m2/-mb, -m2a/-mb,-m4/-ml,-m4/-mb,-m4a/-ml,-m4a/-mb}" Committed as r236928. Cheers, Oleg gcc/ChangeLog: * config/sh/constraints.md (b):

Re: C/C++ OpenACC routine directive, undeclared name error: try to help the user, once

Hi! On Tue, 31 May 2016 10:26:14 -0400, Nathan Sidwell wrote: > 'lexically following' is implementor-speak. [...] Thanks for the review, and wording suggestion. OK for trunk, as follows? commit 3289032bf7fd7e4a0cce37e7acd71e3330729d83 Author: Thomas Schwinge

Re: Remove the unused OMP_CLAUSE_DEVICE_RESIDENT

On Tue, May 31, 2016 at 05:45:25PM +0200, Thomas Schwinge wrote: > While working on something else, I came across the following. Cesar, can > you please verify that this is really dead code in the Fortran front end, > which currently is the only producer of OMP_CLAUSE_DEVICE_RESIDENT? > > Also,

Remove the unused OMP_CLAUSE_DEVICE_RESIDENT

Hi! While working on something else, I came across the following. Cesar, can you please verify that this is really dead code in the Fortran front end, which currently is the only producer of OMP_CLAUSE_DEVICE_RESIDENT? Also, I noticed that the Fortran front end never creates OMP_CLAUSE_MAP with

C++ PATCH for c++/71227 (error specializing friend)

My fix for 70522 caused us to reject this testcase as well. I think that this is correct; I don't see any reason why lookup to find a template to specialize should be treated differently from other normal lookup. But we could be more helpful in the diagnostic, especially since this breaks

[SH][committed] Simplify DImode add, sub, neg patterns

Hi, The attached patch simplifies some DImode patterns on SH. The force_reg in the expand patterns can also be expressed by using the appropriate predicate, which eliminates the need for the expand patterns altogether. Tested on sh-elf with make -k check

Re: [PATCH AArch64]Support missing vcond pattern by adding/using vec_cmp/vcond_mask patterns.

On Tue, May 17, 2016 at 09:02:22AM +, Bin Cheng wrote: > Hi, > Alan and Renlin noticed that some vcond patterns are not supported in > AArch64(or AArch32?) backend, and they both had some patches fixing this. > After investigation, I agree with them that vcond/vcondu in AArch64's backend >

Re: [RX] Add support for atomic operations

On Tue, 2016-05-31 at 14:17 +0100, Nick Clifton wrote: > > Sorry, but my original patch was buggy. There are two problems: > > Thanks for your diligence in checking the patch. Just eating my own dogfood here ... :) > Approved - please apply. Committed as r236926. Cheers, Oleg

Re: Do not imply -fweb with -fpeel-loops

If the decision is taken to remove -fweb, please give me a heads-up as I have a target-specific pass that shares infrastructure with it. I can factor that out to facilitate the removal; just let me know. Thanks! -- Bill Bill Schmidt, Ph.D. GCC for LInux on Power Linux on Power Toolchain IBM

[PATCH] Support for SPARC M7 and VIS 4.0

This patch adds support for -mcpu=niagara7, corresponding to the SPARC M7 CPU as documented in the Oracle SPARC Architecture 2015 and the M7 Processor Supplement. The patch also includes intrinsics support for all the VIS 4.0 instructions. This patch has been tested in sparc64-*-linux-gnu,

Re: [PATCH v4] gcov: Runtime configurable destination output

Nathan Sidwell writes: > On 05/26/16 13:08, Aaron Conole wrote: >> The previous gcov behavior was to always output errors on the stderr channel. >> This is fine for most uses, but some programs will require stderr to be >> untouched by libgcov for certain tests. This change

]PATCH][RFC] Initial patch for better performance of 64-bit math instructions in 32-bit mode on x86-64

Hi Uros, Here is initial patch to improve performance of 64-bit integer arithmetic in 32-bit mode. We discovered that gcc is significantly behind icc and clang on rsa benchmark from eembc2.0 suite. Te problem function looks like typedef unsigned long long ull; typedef unsigned long ul; ul

Re: Moving backwards/FSM threader into its own pass

On 05/30/2016 03:16 AM, Richard Biener wrote: Ok, but the placement (and number of) threading passes then no longer depends on DOM/VRP passes - and as you placed the threading passes _before_ those passes the threading itself does not benefit from DOM/VRP but only from previous optimization

Re: Further refinement to -Wswitch-unreachable

On Tue, May 31, 2016 at 9:40 AM, Marek Polacek wrote: > On Fri, May 27, 2016 at 10:41:51AM -0400, Jason Merrill wrote: >> On 05/26/2016 02:44 PM, Marek Polacek wrote: >> > + if (gimple_code (stmt) == GIMPLE_TRY) >> > { >> > + /* A compiler-generated cleanup

Re: [PATCH][RFC] Remove ifcvt_repair_bool_pattern, re-do bool patterns

Richard, I built compiler with your patch and did not find out any issues with vectorization of loops marked with pragma simd. I also noticed that the size of the vectorized loop looks smaller (I can't tell you exact numbers since the fresh compiler performs fool unroll even if "-funroll-loops"

[PATCH][RFC][rtlanal] Fix rtl-optimization/71295

Hi all, The ICE in this PR occurs when initialising the reginfo for the ira_costs for an instruction of the form: (insn 6 15 16 2 (set (subreg:V2DI (reg/v:EI 111 [ b ]) 0) (const_vector:V2DI [ (const_int 1 [0x1]) (const_int 1 [0x1]) ]))

Re: C/C++ OpenACC routine directive, undeclared name error: try to help the user, once

On 05/24/16 12:28, Thomas Schwinge wrote: + static bool informed_once = false; + if (!informed_once) + { + inform (token->location, + "if the routine directive is meant to apply to the " + "lexically following

Re: [PATCH] Fix PR c++/27100

On Mon, May 30, 2016 at 4:19 PM, Patrick Palka wrote: > Here's a more straightforward version of the patch that abuses the fact > that the fields DECL_PENDING_INLINE_INFO and DECL_SAVED_FUNCTION_DATA > are a union. That gets into undefined behavior; let's go with the first

Re: [PATCH] c++/71306 - bogus -Wplacement-new with an array element

On Mon, May 30, 2016 at 6:59 PM, Martin Sebor wrote: > On 05/30/2016 12:42 PM, Jason Merrill wrote: >> >> OK. > > Sorry, I should have asked to begin with: Is it okay to backport > this fix to the 6.x branch too? Yes. Jason

Re: [C++ Patch] PR 71248

OK. Jason On Tue, May 31, 2016 at 8:54 AM, Paolo Carlini wrote: > Hi, > > the primary issue is already fixed, we don't ICE anymore, but the location > of the error message is (badly) incorrect, because > check_static_variable_definition doesn't use

Re: [Patch, ARM] PR71061, length pop* pattern in epilogue correctly

Hi Jiong, On 19/05/16 09:19, Jiong Wang wrote: On 13/05/16 14:54, Jiong Wang wrote: For thumb mode, this is causing wrong size calculation and may affect some rtl pass, for example bb-order where copy_bb_p needs accurate insn length info. This have eventually part of the reason for

Re: Thoughts on memcmp expansion (PR43052)

On 05/30/2016 11:37 AM, Florian Weimer wrote: * Expand __memcmp_eq for small constant sizes with loads and comparison, fall back to a memcmp call. Should we export such a function from glibc? I expect it's fairly common. Computing the tail difference costs a few cycles. At the moment

Re: [PATCH] Fix 416.gamess miscompare (PR71311)

On Tue, 31 May 2016, Richard Biener wrote: > > The following patch adds missing patterns with swapped comparison > operands for the @0 < @1 and @0 < @2 to @0 < min (@1, @2) transform. > This nullifies the difference gimplify-into-SSA made on > rhfuhf.F:ROFOCK which causes the function no longer

Re: [PATCH] Improve *avx_vperm_broadcast_*

On Tue, May 31, 2016 at 06:54:14AM -0700, H.J. Lu wrote: > On Mon, May 23, 2016 at 10:15 AM, Jakub Jelinek wrote: > > Hi! > > > > The vbroadcastss and vpermilps insns are already in AVX512F & AVX512VL, > > so can be used with v instead of x, the splitter case where we for AVX >

Re: [PATCH] Improve *avx_vperm_broadcast_*

On Mon, May 23, 2016 at 10:15 AM, Jakub Jelinek wrote: > Hi! > > The vbroadcastss and vpermilps insns are already in AVX512F & AVX512VL, > so can be used with v instead of x, the splitter case where we for AVX > emit vpermilps plus vpermf128 is more problematic, because the

Re: Do not imply -fweb with -fpeel-loops

On Tue, May 31, 2016 at 1:42 PM, Jan Hubicka wrote: >> > I would say we should handle -frename-registers same way as we do >> > -fschedule-insns. >> > I.e. enable/disable it on target basis rather than budnle it to loop >> > unrolling. >> > But that is for future patch. I will

[committed] FIx up lastprivate handling in doacross loops

Hi! Here is the promissed fix for lastprivate. We just need to do in the FE what gimplifier does when using a private counter because the normal counter is addressable - because we do the similar thing in the FE. Tested on x86_64-linux, committed to gomp-4_5-branch. 2016-05-31 Jakub Jelinek

Re: [wwwdocs] Remove broken link to old Intel handook in projects/tree-ssa

On Sun, 2016-05-29 at 10:11 +0200, Gerald Pfeifer wrote: > This one tries to redirect on the Intel side, and then even > leads to a "Server not found" > > Committed. > > Gerald > > Index: htdocs/projects/tree-ssa/vectorization.html >

Re: Further refinement to -Wswitch-unreachable

On Fri, May 27, 2016 at 10:41:51AM -0400, Jason Merrill wrote: > On 05/26/2016 02:44 PM, Marek Polacek wrote: > > + if (gimple_code (stmt) == GIMPLE_TRY) > > { > > + /* A compiler-generated cleanup or a user-written try block. > > +Try to get the first statement in

Re: C PATCH for comptypes handling of TYPE_REF_CAN_ALIAS_ALL

Sorry, gcc-patches fell out of CC. On Tue, May 31, 2016 at 03:14:43PM +0200, Marek Polacek wrote: > On Thu, May 26, 2016 at 05:16:39PM +, Joseph Myers wrote: > > On Thu, 26 May 2016, Marek Polacek wrote: > > > > > The C++ FE has been changed, as a part of c++/50800, in such a way that > > >

Re: [RX] Add support for atomic operations

Hi Oleg, > Sorry, but my original patch was buggy. There are two problems: Thanks for your diligence in checking the patch. > The attached patch fixes those issues. > OK for trunk? > > Cheers, > Oleg > > gcc/ChangeLog: > * config/rx/rx.md (FETCHOP_NO_MINUS): New code iterator. >

Re: RFC [1/2] divmod transform

On 30 May 2016 at 13:15, Richard Biener wrote: > On Mon, 30 May 2016, Prathamesh Kulkarni wrote: > >> The attached patch ICE's during bootstrap for x86_64, and is reproducible >> with >> following case with -m32 -O2: >> >> typedef long long type; >> >> type f(type x, type y)

[C++ Patch] PR 71248

Hi, the primary issue is already fixed, we don't ICE anymore, but the location of the error message is (badly) incorrect, because check_static_variable_definition doesn't use DECL_SOURCE_LOCATION. Just doing that, consistently, plus a number of additional column checks in existing testcases

[PATCH] Fix 416.gamess miscompare (PR71311)

The following patch adds missing patterns with swapped comparison operands for the @0 < @1 and @0 < @2 to @0 < min (@1, @2) transform. This nullifies the difference gimplify-into-SSA made on rhfuhf.F:ROFOCK which causes the function no longer to be miscompiled (by vectorization eventually,

Re: [PATCH][ARM] Use proper output modifier for DImode register in store exclusive patterns

Ping. Thanks, Kyrill On 19/05/16 14:27, Kyrill Tkachov wrote: Ping. Thanks, Kyrill On 09/05/16 12:13, Kyrill Tkachov wrote: Hi all, This seems to have fallen through the cracks. Ping. https://gcc.gnu.org/ml/gcc-patches/2016-03/msg00558.html Thanks, Kyrill On 09/03/16 12:56, Kyrill

[PATCH] Fix PR71352

The following fixes another fallout of the negate multiply reassoc patch. Bootstrapped and tested on x86_64-unknown-linux-gnu, applied. Richard. 2016-05-31 Richard Biener PR tree-optimization/71352 * tree-ssa-reassoc.c (zero_one_operation): Handle op

Re: [PATCH][i386] Add -march=native support for VIA nano CPUs

On Tue, 2016-05-31 at 13:38 +0200, Uros Bizjak wrote: > On Mon, May 30, 2016 at 12:09 AM, J. Mayer wrote: > > > > Hello, > > > > On Sun, 2016-05-29 at 21:12 +0200, Uros Bizjak wrote: > > > > > > Hello! > > > > > > > > > > > > > > > When trying to compile using

Re: Do not imply -fweb with -fpeel-loops

> > I would say we should handle -frename-registers same way as we do > > -fschedule-insns. > > I.e. enable/disable it on target basis rather than budnle it to loop > > unrolling. > > But that is for future patch. I will commit this and propose patch making > > -fpeel-loops > > independent of

Re: [PATCH][i386] Add -march=native support for VIA nano CPUs

On Mon, May 30, 2016 at 12:09 AM, J. Mayer wrote: > Hello, > > On Sun, 2016-05-29 at 21:12 +0200, Uros Bizjak wrote: >> Hello! >> >> > >> > When trying to compile using -march=native on a VIA nano CPU, gcc >> > selects "-march=core2" "-mtune=i386" then is unable to compile, as

Re: [patch] Fix segfault in vectorizer

2016-05-31 12:25 GMT+03:00 Richard Biener : > On Tue, May 31, 2016 at 10:22 AM, Eric Botcazou wrote: >> Hi, >> >> it's a regression present on the mainline and 6 branch: for the attached Ada >> testcase, optab_for_tree_code segfaults because the

Re: Do not imply -fweb with -fpeel-loops

On Tue, May 31, 2016 at 12:49 PM, Jan Hubicka wrote: > Hi, > enabling -fpeel-loops with -O3 and -Ofast had unexpected effect of enabling > -fweb and -frename-registers. This patch drop -fweb from list of passes that > are implied by -fpeel-loops because it is no longer needed

Re: Do not imply -frename-registers by -fpeel-loops

On Tue, 31 May 2016, Jan Hubicka wrote: > Hi, > this patch makes -frename-registers independent with -fpeel-loops. > I think the original idea for building this in was the fact that loop peeling > creates > large basic blocks where scheduling matters. This is no longer true about > -fpeel-loops

Do not imply -frename-registers by -fpeel-loops

Hi, this patch makes -frename-registers independent with -fpeel-loops. I think the original idea for building this in was the fact that loop peeling creates large basic blocks where scheduling matters. This is no longer true about -fpeel-loops because this happens only for complete peeling which

Do not imply -fweb with -fpeel-loops

Hi, enabling -fpeel-loops with -O3 and -Ofast had unexpected effect of enabling -fweb and -frename-registers. This patch drop -fweb from list of passes that are implied by -fpeel-loops because it is no longer needed since we do peeling at tree instead of RTL and the out-of-ssa pass cares about

Re: [PATCH] AARCH64: Remove spurious attribute __unused__ from NEON intrinsic

On Mon, Apr 25, 2016 at 05:47:57PM +0100, James Greenhalgh wrote: > On Mon, Apr 25, 2016 at 05:39:45PM +0200, Wladimir J. van der Laan wrote: > > > > Thanks for the info with regard to contributing, > > > > On Fri, Apr 22, 2016 at 09:40:11AM +0100, James Greenhalgh wrote: > > > This patch will

Re: Remove word_mode hack for split bitfields

On 05/26/2016 04:36 PM, Richard Sandiford wrote: This patch is effectively reverting a change from 1994. The reason I think it's a hack is that store_bit_field_1 is creating a subreg reference to one word of a field even though it has already proven that the field spills into the following

Re: [patch] Fix segfault in vectorizer

> I recall that some STMT_VINFO_RELEVANT_P checks have a || > STMT_VINFO_DEF_TYPE () == vect_reduction_def > or VECTORIZABLE_CYCLE_DEF (STMT_VINFO_DEF_TYPE ()). It's rather || STMT_VINFO_LIVE_P in most cases and this works here, the vectorization is properly blocked: opt56.adb:9:29: note: not

Re: [PATCH, ARM] Do not set ARM_ARCH_ISA_THUMB for armv5

On Friday 27 May 2016 14:01:22 Kyrill Tkachov wrote: > On 27/05/16 13:51, Thomas Preudhomme wrote: > > On Tuesday 24 May 2016 18:00:27 Kyrill Tkachov wrote: > >> Hi Thomas, > > > > Hi Kyrill, > > > >>> +/* Nonzero if chip supports Thumb. */ > >>> +extern int arm_arch_thumb; > >>> + > >> > >>

Re: [patch] Fix segfault in vectorizer

On Tue, May 31, 2016 at 11:46 AM, Eric Botcazou wrote: >> Note that vect_determine_vectorization_factor is supposed to set the >> vector type on all >> stmts. That it doesn't is a bug. Do you run into the else branch? > > Yes, for > > result_15 = _6 & result_3; > > wich

Re: [PATCH][AArch64] Use aarch64_fusion_enabled_p to check for insn fusion capabilities

On Fri, May 27, 2016 at 06:10:42PM -0500, Evandro Menezes wrote: > On 05/27/16 11:59, Kyrill Tkachov wrote: > >Hi all, > > > >This patch is a small cleanup that uses the newly introduced > >aarch64_fusion_enabled_p predicate > >to check for what fusion opportunities are enabled for the current >

Re: [PATCH][AArch64] Remove aarch64_simd_attr_length_move

On Fri, May 27, 2016 at 05:57:17PM +0100, Kyrill Tkachov wrote: > Hi all, > > I notice that we can do without aarch64_simd_attr_length_move. The move > alternatives for > the OI,CI,XImode modes that involve memory operands all use a single > load/store so are always > length 4, whereas the

Re: [PATCH][AArch64] Enable -frename-registers at -O2 and higher

On Fri, May 27, 2016 at 02:50:15PM +0100, Kyrill Tkachov wrote: > Hi all, > > As mentioned in https://gcc.gnu.org/ml/gcc-patches/2016-05/msg00297.html, > frename-registers registers can be beneficial for aarch64 and the patch at > https://gcc.gnu.org/ml/gcc-patches/2016-05/msg01618.html resolves

Re: [PATCH, OpenACC] Make reduction arguments addressable

On 2016/5/31 3:28 PM, Thomas Schwinge wrote: > Hi! > > On Mon, 30 May 2016 18:53:41 +0200, Jakub Jelinek wrote: >> On Mon, May 30, 2016 at 10:38:59PM +0800, Chung-Lin Tang wrote: >>> Hi, a previous patch of Cesar's has made the middle-end omp-lowering >>> automatically create

Re: [patch] Fix segfault in vectorizer

> Note that vect_determine_vectorization_factor is supposed to set the > vector type on all > stmts. That it doesn't is a bug. Do you run into the else branch? Yes, for result_15 = _6 & result_3; wich is a BIT_AND_EXPR, hence accepted by vectorizable_reduction. > I think that should only

Re: [PATCH 3/3][AArch64] Emit division using the Newton series

On Fri, May 27, 2016 at 05:57:30PM -0500, Evandro Menezes wrote: > On 05/25/16 11:16, James Greenhalgh wrote: > >On Wed, Apr 27, 2016 at 04:15:53PM -0500, Evandro Menezes wrote: > >>gcc/ > >> * config/aarch64/aarch64-protos.h > >> (tune_params): Add new member

Re: [patch] Fix segfault in vectorizer

On Tue, May 31, 2016 at 10:22 AM, Eric Botcazou wrote: > Hi, > > it's a regression present on the mainline and 6 branch: for the attached Ada > testcase, optab_for_tree_code segfaults because the function is invoked on a > NULL_TREE vectype_out from the vectorizer

Re: [PATCH] Fix PR tree-optimization/71314

On Mon, May 30, 2016 at 9:50 PM, Patrick Palka wrote: > The test case ssa-thread-14.c expects that non-short-circuit logical ops > are used so it fails on targets that don't use such ops by default. To > fix, I copied the dg directives from tree-ssa/reassoc-35.c which look

Re: [PATCH] Fix PR tree-optimization/71077

On Mon, May 30, 2016 at 9:50 PM, Patrick Palka wrote: > In this PR the function simplify_control_stmt_condition_1(), which is > responsible for recursing into the operands of a GIMPLE_COND during jump > threading to check for dominating ASSERT_EXPRs, was erroneously >

[patch] Fix segfault in vectorizer

Hi, it's a regression present on the mainline and 6 branch: for the attached Ada testcase, optab_for_tree_code segfaults because the function is invoked on a NULL_TREE vectype_out from the vectorizer (vectorizable_reduction): if (STMT_VINFO_VEC_REDUCTION_TYPE (stmt_info) ==

Re: [PATCH][wwwdocs] Improve arm and aarch64-related info in readings.html

Hi Gerald, On 28/05/16 21:04, Gerald Pfeifer wrote: Hi Kyrill, On Thu, 19 May 2016, Kyrill Tkachov wrote: I noticed that we have a readings.html page that has pointers to documentation of various backends that GCC supports. The info on arm seems a bit out of date and somewhat confusing, and

Re: [wwwdocs] Document GCC 6 Solaris changes

Gerald Pfeifer writes: > On Tue, 19 Apr 2016, Rainer Orth wrote: [gcc-6/changes.html] >> Btw., I noticed that the subsections of `Operating Systems' are in >> random order. Shouldn't they be sorted alphabetically? > > Yes. Want to give it a try? It's surely

Re: [PATCH, OpenACC] Make reduction arguments addressable

Hi! On Mon, 30 May 2016 18:53:41 +0200, Jakub Jelinek wrote: > On Mon, May 30, 2016 at 10:38:59PM +0800, Chung-Lin Tang wrote: > > Hi, a previous patch of Cesar's has made the middle-end omp-lowering > > automatically create and insert a tofrom (i.e. present_or_copy) map for >