RFC: Implementing a new API for value_range

Hi Richard. Hi folks. I'd like to implement a clean API that disallows direct access to any of the value_range internals. My aim is a clean API with no change in functionality. This is mostly a clean-up, but could also pave the way for possibly changing the underlying implementation in the

[PATCH] Use C++11 direct initialization in Debug associative containers

Just some code cleanup extending use of C++11 direct initialization.     * include/debug/map.h     (map<>::emplace<>(_Args&&...)): Use C++11 direct initialization.     (map<>::emplace_hint<>(const_iterator, _Args&&...)): Likewise.     (map<>::insert(value_type&&)): Likewise.     (map<>::insert<>

Re: [PATCH] RISC-V: Fix unordered float compare for Signaling NaN.

Hi Jim: Oh, I missed that pull request in github, Andrew's patch is better than our patch, you can just ignore our one. However I think this fix is kind of pre-requirement of rv32 glibc upstreaming, because Joseph want new port has all passed testsuite result. On Wed, Oct 3, 2018 at 10:46 AM Jim W

Re: [PATCH] RISC-V: Fix unordered float compare for Signaling NaN.

On Tue, Oct 2, 2018 at 7:23 PM Kito Cheng wrote: > This patch is fixing the wrong behavior for unordered float compare > for Signaling NaN, current implementation will suppress the FP > exception flags unconditionally, however signaling NaN should signal > an exception according IEEE 754-2008 spec

[PATCH] RISC-V: Fix unordered float compare for Signaling NaN.

Hi Jim: This patch is fixing the wrong behavior for unordered float compare for Signaling NaN, current implementation will suppress the FP exception flags unconditionally, however signaling NaN should signal an exception according IEEE 754-2008 spec. I've add an test for that, and full test is in

Re: [PATCH 0/2][IRA,LRA] Fix PR86939, IRA incorrectly creates an interference between a pseudo register and a hard register

On 10/2/18 7:17 PM, H.J. Lu wrote: >> Index: gcc/testsuite/gcc.target/i386/pr49095.c >> === >> --- gcc/testsuite/gcc.target/i386/pr49095.c (revision 264793) >> +++ gcc/testsuite/gcc.target/i386/pr49095.c (working copy) >> @@ -7

Re: [PATCH 0/2][IRA,LRA] Fix PR86939, IRA incorrectly creates an interference between a pseudo register and a hard register

On Tue, Oct 2, 2018 at 3:28 PM Peter Bergner wrote: > > On 10/2/18 4:52 PM, H.J. Lu wrote: > > I saw the same failures: > > > > FAIL: gcc.target/i386/pr49095.c scan-assembler-times \\), % 8 > > FAIL: gcc.target/i386/pr49095.c scan-assembler-times \\), % 8 > > > > I think the new ones are better, e

Re: [PATCH 0/2][IRA,LRA] Fix PR86939, IRA incorrectly creates an interference between a pseudo register and a hard register

On 10/2/18 4:52 PM, H.J. Lu wrote: > I saw the same failures: > > FAIL: gcc.target/i386/pr49095.c scan-assembler-times \\), % 8 > FAIL: gcc.target/i386/pr49095.c scan-assembler-times \\), % 8 > > I think the new ones are better, especially in 32-bit case: Excellent! Does the following test case

[OpenACC] initial manual deep copy in c

I've push the attach patch to my github trunk-acc-mdc branch which enables OpenMP 4.5 deep copy semantics in OpenACC data clauses in C. Now GCC accepts data clauses of the form #pragma acc data copy(v.a[:n], v.b) I think there are a couple of limitations in OpenMP that's going to force me to in

Re: [PATCH 0/2][IRA,LRA] Fix PR86939, IRA incorrectly creates an interference between a pseudo register and a hard register

On Tue, Oct 2, 2018 at 12:44 PM Peter Bergner wrote: > > On 10/2/18 9:59 AM, Peter Bergner wrote: > > gcc/ > > PR rtl-optimization/86939 > > PR rtl-optimization/87479 > > * ira.h (copy_insn_p): New prototype. > > * ira-lives.c (ignore_reg_for_conflicts): New static variable

Re: C++ PATCH to implement C++20 P0892R2 - explicit(bool)

On Mon, Oct 01, 2018 at 07:47:10PM -0400, Jason Merrill wrote: > On Mon, Oct 1, 2018 at 6:41 PM Marek Polacek wrote: > > > > This patch implements C++20 explicit(bool), as described in: > > . > > > > I tried to follow the noexce

Re: [PATCH 0/2][IRA,LRA] Fix PR86939, IRA incorrectly creates an interference between a pseudo register and a hard register

On 10/2/18 9:59 AM, Peter Bergner wrote: > gcc/ > PR rtl-optimization/86939 > PR rtl-optimization/87479 > * ira.h (copy_insn_p): New prototype. > * ira-lives.c (ignore_reg_for_conflicts): New static variable. > (make_hard_regno_dead): Don't add conflicts for register >

Re: [PATCH][IRA,LRA] Fix PR87466, all pseudos live across setjmp are spilled

On 10/2/18 1:21 PM, Segher Boessenkool wrote: > On Tue, Oct 02, 2018 at 11:42:19AM -0500, Peter Bergner wrote: >> +/* The default implementation of >> TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P. */ >> + >> +bool >> +default_setjmp_preserves_nonvolatile_regs_p (void) >> +{ >> + return false; >> +

Re: [PATCH][IRA,LRA] Fix PR87466, all pseudos live across setjmp are spilled

On 10/2/18 1:21 PM, Segher Boessenkool wrote: > Hi Peter, > > On Tue, Oct 02, 2018 at 11:42:19AM -0500, Peter Bergner wrote: >> +/* The default implementation of >> TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P. */ >> + >> +bool >> +default_setjmp_preserves_nonvolatile_regs_p (void) >> +{ >> + ret

Re: [PATCH][IRA,LRA] Fix PR87466, all pseudos live across setjmp are spilled

Hi Peter, On Tue, Oct 02, 2018 at 11:42:19AM -0500, Peter Bergner wrote: > +/* The default implementation of TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P. > */ > + > +bool > +default_setjmp_preserves_nonvolatile_regs_p (void) > +{ > + return false; > +} You can just use hook_bool_void_false for

Re: GCC options for kernel live-patching (Was: Add a new option to control inlining only on static functions)

On October 2, 2018 7:13:13 PM GMT+02:00, "Martin Liška" wrote: >On 10/2/18 5:12 PM, Qing Zhao wrote: >> >>> On Oct 2, 2018, at 9:55 AM, Martin Liška > wrote: >> >> Affected functions: 5 >>   __ilog2_u64/132 (include/linux/log2.h:40:5) >>   ablkcipher_request

Re: [PATCH][IRA,LRA] Fix PR87466, all pseudos live across setjmp are spilled

On 10/2/18 11:42 AM, Peter Bergner wrote: > On 10/1/18 4:25 AM, Eric Botcazou wrote: > This is currently bootstrapping right now, but ok for trunk assuming no > regressions? > > gcc/ > PR rtl-optimization/87466 > * target.def (setjmp_preserves_nonvolatile_regs_p): New target hook. >

Re: [PATCH] Properly mark lambdas in GCOV (PR gcov-profile/86109).

On 10/2/18 11:14 AM, Martin Liška wrote: > On 10/2/18 5:32 PM, Jeff Law wrote: >> On 9/12/18 6:39 AM, Martin Liška wrote: >>> Hi. >>> >>> This is follow-up of: >>> https://gcc.gnu.org/ml/gcc/2018-08/msg7.html >>> >>> I've chosen to implement that with new DECL_CXX_LAMBDA_FUNCTION that >>> uses

Re: [PATCH] Properly mark lambdas in GCOV (PR gcov-profile/86109).

On 10/2/18 5:32 PM, Jeff Law wrote: On 9/12/18 6:39 AM, Martin Liška wrote: Hi. This is follow-up of: https://gcc.gnu.org/ml/gcc/2018-08/msg7.html I've chosen to implement that with new DECL_CXX_LAMBDA_FUNCTION that uses an empty bit in tree_function_decl. Patch can bootstrap on ppc64le-r

Re: GCC options for kernel live-patching (Was: Add a new option to control inlining only on static functions)

On 10/2/18 5:12 PM, Qing Zhao wrote: On Oct 2, 2018, at 9:55 AM, Martin Liška mailto:mli...@suse.cz>> wrote: Affected functions: 5   __ilog2_u64/132 (include/linux/log2.h:40:5)   ablkcipher_request_alloc/1639 (include/linux/crypto.h:979:82)   ablkcipher_request_alloc.constprop.8/3198 (include

Re: [PATCH 0/2][IRA,LRA] Fix PR86939, IRA incorrectly creates an interference between a pseudo register and a hard register

On Tue, Oct 2, 2018 at 8:39 AM Peter Bergner wrote: > > On 10/2/18 10:32 AM, H.J. Lu wrote: > > On Tue, Oct 2, 2018 at 7:59 AM Peter Bergner wrote: > >> I'm currently performing bootstrap and regtesting on powerpc64le-linux and > >> x86_64-linux. H.J., could you please test this patch on i686 to

Re: libgo patch committed: Update to 1.11 release

On Fri, Sep 28, 2018 at 7:22 AM, Rainer Orth wrote: > >> I've committed a patch to update libgo to the 1.11 release. As usual >> for these updates, the patch is too large to attach to this e-mail >> message. I've attached some of the more relevant directories. This >> update required some minor

Re: [PATCH][IRA,LRA] Fix PR87466, all pseudos live across setjmp are spilled

On 10/1/18 4:25 AM, Eric Botcazou wrote: >> Since all implementations of this hook will have to do the same, I think >> it is better if you leave this test at the (only two) callers. The hook >> doesn't need an argument then, and maybe is better named something like >> setjmp_is_normal_call? (The

[PATCH 4/4] - Replace uses of old get_range_strlen with the new one.

[4/4] - Replace uses of old get_range_strlen with the new one. This change switches the remaining get_range_strlen() callers to use the new overload of the function that takes a strlen_data_t argument. There are no functional changes here. [4/4] - Replace uses of old get_range_strlen with the ne

[PATCH 3/4] - Change sprintf to use new get_range_strlen overload

[3/4] - Change sprintf to use new get_range_strlen overload This change makes use of the new get_range_strlen() overload in gimple-ssa-sprintf.c. This necessitated a few changes to the API but also enabled the removal of the flexarray member from strlen_data_t. This also patch restores the bool

[PATCH 2/4] - relax strlen range optimization to avoid making assumptions about types

[2/4] - Relax strlen range optimization to avoid making assumptions about types This main part of this patch is to relax the strlen range optimization to avoid relying on array types. Instead, the function either removes the upper bound of the strlen result altogether, or constrains it b

[PATCH 1/4] introduce struct strlen_data_t into gimple-fold

[1/4] - Introduce struct strlen_data_t into gimple-fold This patch introduces a new data structure to reduce the number of arguments and overloads of the get_range_strlen API. One of the goals of this change is to make the API safer to use for optimization (which looks for "permissive" results t

[PATCH 0/4] avoid relying on type information in get_range_strlen

This patch kit changes the get_range_strlen API to a) make its use more intuitive and less prone to misuse, and b) relax the strlen range optimization to avoid making use of array type sizes to constrain the upper bound of the function return value. I broke up the changes into a series of four in

[PATCH, AArch64 v2 10/11] aarch64: Implement TImode compare-and-swap

This pattern will only be used with the __sync functions, because we do not yet have a bare TImode atomic load. * config/aarch64/aarch64.c (aarch64_gen_compare_reg): Add support for NE comparison of TImode values. (aarch64_print_operand): Extend %R to handle general

[PATCH, AArch64 v2 11/11] Enable -matomic-ool by default

Do Not Merge Upstream. This is for agraf and his testing within SLES. --- gcc/common/config/aarch64/aarch64-common.c | 6 -- gcc/config/aarch64/aarch64.c | 6 -- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/gcc/common/config/aarch64/aarch64-common.c b/gcc/c

[PATCH, AArch64 v2 08/11] aarch64: Implement -matomic-ool

* config/aarch64/aarch64.opt (-matomic-ool): New. * config/aarch64/aarch64.c (aarch64_atomic_ool_func): New. (aarch64_ool_cas_names, aarch64_ool_swp_names): New. (aarch64_ool_ldadd_names, aarch64_ool_ldset_names): New. (aarch64_ool_ldclr_names, aarch64_ool_ld

[PATCH, AArch64 v2 09/11] aarch64: Force TImode values into even registers

The LSE CASP instruction requires values to be placed in even register pairs. A solution involving two additional register classes was rejected in favor of the much simpler solution of simply requiring all TImode values to be aligned. * config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok

[PATCH, AArch64 v2 07/11] aarch64: Add out-of-line functions for LSE atomics

This is the libgcc part of the interface -- providing the functions. Rationale is provided at the top of libgcc/config/aarch64/lse.c. * config/aarch64/lse.c: New file. * config/aarch64/t-lse: New file. * config.host: Add t-lse to all aarch64 tuples. --- libgcc/config/aarch

[PATCH, AArch64 v2 06/11] Add visibility to libfunc constructors

* optabs-libfuncs.c (build_libfunc_function_visibility): New, split out from... (build_libfunc_function): ... here. (init_one_libfunc_visibility): New, split out from ... (init_one_libfunc): ... here. --- gcc/optabs-libfuncs.h | 2 ++ gcc/optabs-libfuncs.c

[PATCH, AArch64 v2 05/11] aarch64: Emit LSE st instructions

When the result of an operation is not used, we can ignore the result by storing to XZR. For two of the memory models, using XZR with LD has a preferred assembler alias, ST. * config/aarch64/atomics.md (aarch64_atomic__lse): Use ST for relaxed and release models; load to XZR other

[PATCH, AArch64 v2 04/11] aarch64: Improve atomic-op lse generation

Fix constraints; avoid unnecessary split. Drop the use of the atomic_op iterator in favor of the ATOMIC_LDOP iterator; this is simplier and more logical for ldclr aka bic. * config/aarch64/aarch64.c (aarch64_emit_bic): Remove. (aarch64_atomic_ldop_supported_p): Remove. (aa

[PATCH, AArch64 v2 03/11] aarch64: Improve swp generation

Allow zero as an input; fix constraints; avoid unnecessary split. * config/aarch64/aarch64.c (aarch64_emit_atomic_swap): Remove. (aarch64_gen_atomic_ldop): Don't call it. * config/aarch64/atomics.md (atomic_exchange): Use aarch64_reg_or_zero. (aarch64_atomic

[PATCH, AArch64 v2 01/11] aarch64: Simplify LSE cas generation

The cas insn is a single insn, and if expanded properly need not be split after reload. Use the proper inputs for the insn. * config/aarch64/aarch64.c (aarch64_expand_compare_and_swap): Force oldval into the rval register for TARGET_LSE; emit the compare during initial exp

[PATCH, AArch64 v2 02/11] aarch64: Improve cas generation

Do not zero-extend the input to the cas for subword operations; instead, use the appropriate zero-extending compare insns. Correct the predicates and constraints for immediate expected operand. * config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): New. (aarch64_split_compa

[PATCH, AArch64 v2 00/11] LSE atomics out-of-line

Changes since v1: * Use config/t-slibgcc-libgcc instead of gcc.c changes. * Some style fixes. * Ifdefs to work with old glibc. * Force TImode registers into even regnos. Required by CASP, allowed by the ABI, and is seen as the simplier solution than adding two new register classes.

Re: [PATCH,Fortran] Fix libgfortran/io/close.c for !HAVE_UNLINK_OPEN_FILE

On Tue, Oct 2, 2018 at 2:08 PM Gerald Pfeifer wrote: > Revision r215307 | jb | 2014-09-16 23:40:28 +0200 (Di, 16 Sep 2014) > >PR libfortran/62768 Handle filenames with embedded null characters. >: > > made the changes like the following to libgfortran/io/close.c > >#if !HAVE_UNLINK_OP

[PATCH, libgcc]: Use type-generic fpclassify builtins in libgcc2.c

Nowadays, we have these type-generic builtins always available. 2018-10-02 Uros Bizjak * libgcc2.c (isnan): Use __builtin_isnan. (isfinite): Use __builtin_isfinite. (isinf): Use __builtin_isinf. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. OK for mainline? Uro

Re: [PATCH 0/2][IRA,LRA] Fix PR86939, IRA incorrectly creates an interference between a pseudo register and a hard register

On 10/2/18 10:32 AM, H.J. Lu wrote: > On Tue, Oct 2, 2018 at 7:59 AM Peter Bergner wrote: >> I'm currently performing bootstrap and regtesting on powerpc64le-linux and >> x86_64-linux. H.J., could you please test this patch on i686 to verify it >> doesn't expose any other problems there? Otherwi

[PATCH 2/2] S/390: Support IBM z14 Model ZR1 with -march=native

This adds the CPU model number of the IBM z14 Model ZR1 machine to -march=native. The patch doesn't actually change anything since we anyway default to z14 for unknown CPU model numbers. So this is just for the sake of completeness. 2018-10-02 Andreas Krebbel * config/s390/driver-nat

[PATCH 1/2] S/390: Rename arch12 to z14

This is a mechanical change not impacting code generation. With that patch I try to hide the artificial CPU name arch12 which we had to use before the announcement of the IBM z14 machine. arch12 of course stays a valid option to -march and -mtune. So this is just about making the code somewhat e

Re: [PATCH 0/2][IRA,LRA] Fix PR86939, IRA incorrectly creates an interference between a pseudo register and a hard register

On Tue, Oct 2, 2018 at 7:59 AM Peter Bergner wrote: > > On 10/1/18 10:52 PM, Peter Bergner wrote: > > Now that we handle conflicts at definitions and the pic hard reg > > is set via a copy from the pic pseudo, my PATCH 2 is setup to > > handle exactly this scenario (ie, a copy between a pseudo and

[PATCH, i386]: Remove isinf patterns

Generic builtins are better also for x87. 2018-10-02 Uros Bizjak * config/i386/i386.md (fxam2_i387_with_temp): Remove. (isinfxf2): Ditto. (isinf2): Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. diff --git a/gcc/config/i38

Re: [PATCH] Properly mark lambdas in GCOV (PR gcov-profile/86109).

On 9/12/18 6:39 AM, Martin Liška wrote: > Hi. > > This is follow-up of: > https://gcc.gnu.org/ml/gcc/2018-08/msg7.html > > I've chosen to implement that with new DECL_CXX_LAMBDA_FUNCTION that > uses an empty bit in tree_function_decl. > > Patch can bootstrap on ppc64le-redhat-linux and survi

Re: [PATCH] warn for sprintf argument mismatches (PR 87034)

On 8/21/18 8:10 PM, Martin Sebor wrote: > It didn't seem like we were making progress in the debate about > warning for sprintf argument mismatches earlier today so I took > a couple of hours this afternoon to prototype one of the solutions > I was trying to describe.  It mostly keeps the existing 

[PATCH, i386]: Perform ix86_emit_i387_round calculations in XFmode

The emitted assembly is actually the same. 2018-10-02 Uros Bizjak * config/i386/i386.c (ix86_emit_i387_round): Extend op1 to XFmode before emitting fxam. Perform calculations in XFmode. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros.

PING * 2: Re: VRP: special case all pointer conversion code

PING * 2 Forwarded Message Subject: PING: Re: VRP: special case all pointer conversion code Date: Wed, 26 Sep 2018 13:12:19 -0400 From: Aldy Hernandez To: gcc-patches CC: Jeff Law PING On 9/17/18 6:12 AM, Aldy Hernandez wrote: It seems most of the remaining anti range code

Re: GCC options for kernel live-patching (Was: Add a new option to control inlining only on static functions)

> On Oct 2, 2018, at 9:55 AM, Martin Liška wrote: Affected functions: 5 __ilog2_u64/132 (include/linux/log2.h:40:5) ablkcipher_request_alloc/1639 (include/linux/crypto.h:979:82) ablkcipher_request_alloc.constprop.8/3198 (include/linux/crypto.h:979:82) helpe

[patch,openacc] Add warning for unused acc routine parallelism

This patch teaches omp-general to be a little more verbose when it comes time to reporting the missing usage of gang, worker, and vector clauses on acc routines. As before, the Fortran FE does this directly so that it can handle modules. Therefore, this primarily handle the C and C++ cases (althoug

Re: libgo patch committed: Update to 1.11 release

On Fri, Sep 28, 2018 at 12:05 AM, Uros Bizjak wrote: > On Wed, Sep 26, 2018 at 9:57 AM, Uros Bizjak wrote: >> I've committed a patch to update libgo to the 1.11 release. As usual >> for these updates, the patch is too large to attach to this e-mail >> message. I've attached some of the more rel

[patch,openacc] Check for sufficient parallelism when calling acc routines in Fortran

This patch updates the Fortran FE OpenACC routine parser to enforce the new OpenACC 2.5 routine directive semantics. In addition to emitting a warning when the user doesn't specify a gang, worker or vector clause, it also clarifies some error messages and introduces a new error when the user tries

Re: [PATCH 0/2][IRA,LRA] Fix PR86939, IRA incorrectly creates an interference between a pseudo register and a hard register

On 10/1/18 10:52 PM, Peter Bergner wrote: > Now that we handle conflicts at definitions and the pic hard reg > is set via a copy from the pic pseudo, my PATCH 2 is setup to > handle exactly this scenario (ie, a copy between a pseudo and > a hard reg). I looked at the asm output from a build with b

[patch,openacc] Check clauses with intrinsic function specified in !$ACC ROUTINE ( NAME )

This patch allows Fortran intrinsic functions to be declared as acc routines. For instance, abort can now be called from acc within offloaded regions. Given that intrinsic functions like sin and cos are important for offloaded functions, I wonder if there is a better way to accomplish to enabling

Re: GCC options for kernel live-patching (Was: Add a new option to control inlining only on static functions)

On 10/2/18 4:46 PM, Qing Zhao wrote: > >> On Oct 2, 2018, at 9:02 AM, Martin Liška wrote: >> >> On 10/2/18 3:28 PM, Qing Zhao wrote: >>> On Oct 2, 2018, at 3:33 AM, Martin Jambor wrote: Hi, my apologies for being terse, I'm in a meeting. On Mon, Oct 01 2018, Qi

[patch,openacc] Repeated use of the OpenACC routine directive

This is another patch that teaches the C and C++ to emit more errors involving acc routine clauses. In retrospect, I should have merged it together with the patch I posted here , however at the time I thought it would make the patch too larg

Re: GCC options for kernel live-patching (Was: Add a new option to control inlining only on static functions)

> On Oct 2, 2018, at 9:02 AM, Martin Liška wrote: > > On 10/2/18 3:28 PM, Qing Zhao wrote: >> >>> On Oct 2, 2018, at 3:33 AM, Martin Jambor wrote: >>> >>> Hi, >>> >>> my apologies for being terse, I'm in a meeting. >>> >>> On Mon, Oct 01 2018, Qing Zhao wrote: Hi, Martin, I

Re: [PATCH 0/2][IRA,LRA] Fix PR86939, IRA incorrectly creates an interference between a pseudo register and a hard register

On 10/1/18 9:52 PM, Peter Bergner wrote: > On 10/1/18 7:45 AM, H.J. Lu wrote: >> You may have undone: >> >> https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=218059 > > Yes, the code above also needed to be modified to handle conflicts being > added at definitions rather than at uses. The pa

Re: [PATCH c++/pr87295] -fdebug-types-section ICE

Ping? On 9/17/18 7:30 AM, Nathan Sidwell wrote: Richard, this patch makes the ICE go away, but I really don't know if it's correct.  When cloning the type die I copy die_id, so it is found during the (currently ICEing) hash lookup.  In this particular testcase we clone the die twice.  Once fr

[PATCH] rs6000: Fix vec-init-6.c (PR87081)

Since a while we use a rldimi instead of rldicl/rldicr/or to combine two words to one. 2018-10-02 Segher Boessenkool PR target/87081 * gcc.target/powerpc/vec-init-6.c: Fix expected asm. --- gcc/testsuite/gcc.target/powerpc/vec-init-6.c | 3 +-- 1 file changed, 1 insertion(+)

[PATCH, rs6000] 1/2 Add x86 SSE3 intrinsics to GCC PPC64LE target

This is a follow-on to earlier commits for adding compatibility implementations of x86 intrinsics for PPC64LE. This is the first of two patches. This patch adds 11 of the 13 x86 intrinsics from ("SSE3"). (Patch 2/2 adds tests for these intrinsics, and briefly describes the tests performed.) Im

[PATCH, rs6000] 2/2 Add x86 SSE3 intrinsics to GCC PPC64LE target

This is part 2/2 for contributing PPC64LE support for X86 SSE3 instrisics. This patch includes testsuite/gcc.target tests for the intrinsics defined in pmmintrin.h. Tested on POWER8 ppc64le and ppc64 (-m64 and -m32, the latter only reporting 10 new unsupported tests.) [gcc/testsuite] 2018-10-01

Re: [committed] Use structure to bubble up information about unterminated strings from c_strlen

On 10/1/18 3:46 PM, Christophe Lyon wrote: > On Sat, 29 Sep 2018 at 18:06, Jeff Law wrote: >> >> >> This patch changes the NONSTR argument to c_strlen to instead be a >> little data structure c_strlen can populate with nuggets of information >> about the string. >> >> There's clearly a need for th

[patch,openacc] Add support for OpenACC routine nohost clause

Attached is a patch that introduces support for the acc routine nohost clause. Basically, if an acc routine function is marked as nohost, then the compiler does not generate code for the host. It's kind of strange to test for. Basically, we had to use acc_on_device at -O2 so that the host reference

[patch,openacc] Use oacc_verify_routine_clauses for C/C++

This patch introduces a new oacc_verify_routine_clauses function that reports errors if the user abuses the gang, worker and vector clauses for acc routine directives in C/C++. Fortran is a little different, because the FE has it's own IR. So, while it would be possible to defer checking for gang,

Re: GCC options for kernel live-patching (Was: Add a new option to control inlining only on static functions)

On 10/2/18 3:28 PM, Qing Zhao wrote: > >> On Oct 2, 2018, at 3:33 AM, Martin Jambor wrote: >> >> Hi, >> >> my apologies for being terse, I'm in a meeting. >> >> On Mon, Oct 01 2018, Qing Zhao wrote: >>> Hi, Martin, >>> >>> I have studied a little more on >>> >>> https://github.com/marxin/kgraft-a

[PATCHv3][PR 81376][PING] Remove unnecessary float casts in comparisons

Hi all, This is a second iteration of patch which gets rid of float casts in comparisons when all values of casted integral type are exactly representable by the float type (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81376). The new version addresses issue spotted by Richard in previous version

[PATCH] Avoid redundant runtime checks in std::visit

Calling std::get will check some static assertions and also do a runtime check for a valid index before calling __detail::__variant::__get. The std::visit function already handles the case where any variant has an invalid index, so __get can be used directly in __visit_invoke. * include/s

Re: Fold more boolean expressions

Thanks a lot!

Re: GCC options for kernel live-patching (Was: Add a new option to control inlining only on static functions)

> On Oct 2, 2018, at 3:33 AM, Martin Jambor wrote: > > Hi, > > my apologies for being terse, I'm in a meeting. > > On Mon, Oct 01 2018, Qing Zhao wrote: >> Hi, Martin, >> >> I have studied a little more on >> >> https://github.com/marxin/kgraft-analysis-tool/blob/master/README.md >>

Re: [PATCH][rs6000][PR target/87474] fix strncmp expansion with -mno-power8-vector

On Tue, Oct 02, 2018 at 08:24:31AM -0500, Aaron Sawdey wrote: > >> @@ -2205,6 +2205,7 @@ > >> } > >>else > >> { > >> + /* Implies TARGET_P8_VECTOR here. */ > > > > That isn't true as far as I see. > > We can only enter emit_final_str_compare_vec() if TARGET_P8_VECTOR is set. >

Re: [PATCH][rs6000][PR target/87474] fix strncmp expansion with -mno-power8-vector

On 10/2/18 3:38 AM, Segher Boessenkool wrote: > On Mon, Oct 01, 2018 at 11:09:44PM -0500, Aaron Sawdey wrote: >> PR/87474 happens because I didn't check that both vector and VSX instructions >> were enabled, so insns that are disabled get generated with >> -mno-power8-vector. > >> PR targ

[PATCH][GCC][front-end][opt-framework] Remove superfluous assignment in add_params.

Hi All, This fixes the superfluous assignment that Coverity reported in add_params, and changes the starting index from 0 to num_params - n in order for it to work properly if add_params is called multiple times. validate_params calls error so it doesn't matter that we don't check the results her

RE: [PATCH][GCC][front-end][opt-framework] Update options framework for parameters to properly handle and validate configure time params. [Patch (2/3)]

Hi Alexander, > -Original Message- > From: Alexander Monakov > Sent: Tuesday, October 2, 2018 08:01 > To: Tamar Christina > Cc: Jeff Law ; gcc-patches@gcc.gnu.org; nd > ; jos...@codesourcery.com > Subject: RE: [PATCH][GCC][front-end][opt-framework] Update options > framework for paramete

Re: [PATCH, GCC/ARM] Fix PR87374: ICE with -mslow-flash-data and -mword-relocations

On 02/10/2018 11:42, Thomas Preudhomme wrote: Hi Ramana, On Thu, 27 Sep 2018 at 11:14, Ramana Radhakrishnan wrote: On 27/09/2018 09:26, Kyrill Tkachov wrote: Hi Thomas, On 26/09/18 18:39, Thomas Preudhomme wrote: Hi, GCC ICEs under -mslow-flash-data and -mword-relocations because there is

Re: Use -fno-show-column in libstdc++ installed testing

On 02/10/18 00:58 +, Joseph Myers wrote: arranged for libstdc++ tests to use -fno-show-column by default, but only for build-tree testing. This patch adds it to the options used for installed testing as well. Tested with installed tes

Re: [PATCH] libstdc++: Remove unused define

On 01/10/18 23:01 +0200, Bernhard Reutner-Fischer wrote: __NO_STRING_INLINES was removed from uClibc around 2004 so has no effect. Ok for trunk? OK, thanks.

[PATCH,Fortran] Fix libgfortran/io/close.c for !HAVE_UNLINK_OPEN_FILE

Revision r215307 | jb | 2014-09-16 23:40:28 +0200 (Di, 16 Sep 2014) PR libfortran/62768 Handle filenames with embedded null characters. : made the changes like the following to libgfortran/io/close.c #if !HAVE_UNLINK_OPEN_FILE - path = fc_strdup (u->file, u->file_len); +

Privatize do_jump and do_jump_1

There is a single, convoluted use of do_jump outside dojump.c and no uses of do_jump_1 at all. Tested on x86-64/Linux, applied on the mainline as obvious. 2018-10-02 Eric Botcazou * dojump.h (do_jump): Delete. (do_jump_1): Likewise. (split_comparison): Move around.

Re: [PATCH, OpenACC] Properly handle wait clause with no arguments

Ping (adding Thomas to CC as OpenACC maintainer) On 2018/8/30 9:27 PM, Chung-Lin Tang wrote: Hi, this patch properly handles OpenACC 'wait' clauses without arguments, making it an equivalent of "wait all". (current trunk basically discards and ignores such argument-less wait clauses)  This add

Re: [PATCH, GCC/ARM] Fix PR87374: ICE with -mslow-flash-data and -mword-relocations

Hi Ramana, On Thu, 27 Sep 2018 at 11:14, Ramana Radhakrishnan wrote: > > On 27/09/2018 09:26, Kyrill Tkachov wrote: > > Hi Thomas, > > > > On 26/09/18 18:39, Thomas Preudhomme wrote: > >> Hi, > >> > >> GCC ICEs under -mslow-flash-data and -mword-relocations because there > >> is no way to load an

Small tweak to reorg.c

This changes make_return_insns to using emit_copy_of_insn_after when it needs to re-emit insns that were put in a delay slot, like routines doing the same thing in the file, and re-emitting the jump insn directly. Tested on SPARC/Solaris, applied on the mainline. 2018-10-02 Eric Botcazou

Re: [PATCH] Adjust V[24]DF reduc_plus_scal patterns (was: RFC: x87 reduc_plus_scal_* AVX (and AVX512?) expanders)

> On Mon, 1 Oct 2018, Richard Biener wrote: > > > > > I notice that for Zen we create > > > > 0.00 │ vhaddp %ymm3,%ymm3,%ymm3 > > 1.41 │ vperm2 $0x1,%ymm3,%ymm3,%ymm1 > > 1.45 │ vaddpd %ymm1,%ymm2,%ymm2 > > > > from reduc_plus_scal_v4df which uses a cross-lane permute vp

Re: [patch] Fix PR tree-optimization/86659

> so the fix is to simply not optimize here? Yes, we cannot turn a BIT_FIELD_REF with rev-storage into a VIEW_CONVERT_EXPR. > Are there correctness issues with the patterns we have for rev-storage? But > then some cases are let through via the realpart/imagpart/v_c_e case? I > suppose we should

[PATCH] Adjust V[24]DF reduc_plus_scal patterns (was: RFC: x87 reduc_plus_scal_* AVX (and AVX512?) expanders)

On Mon, 1 Oct 2018, Richard Biener wrote: > > I notice that for Zen we create > > 0.00 │ vhaddp %ymm3,%ymm3,%ymm3 > 1.41 │ vperm2 $0x1,%ymm3,%ymm3,%ymm1 > 1.45 │ vaddpd %ymm1,%ymm2,%ymm2 > > from reduc_plus_scal_v4df which uses a cross-lane permute vperm2f128 > even thou

Re: [PATCH][rs6000][PR target/87474] fix strncmp expansion with -mno-power8-vector

On Mon, Oct 01, 2018 at 11:09:44PM -0500, Aaron Sawdey wrote: > PR/87474 happens because I didn't check that both vector and VSX instructions > were enabled, so insns that are disabled get generated with > -mno-power8-vector. > PR target/87474 > * config/rs6000/rs6000-string.c (expand

Re: GCC options for kernel live-patching (Was: Add a new option to control inlining only on static functions)

Hi, my apologies for being terse, I'm in a meeting. On Mon, Oct 01 2018, Qing Zhao wrote: > Hi, Martin, > > I have studied a little more on > > https://github.com/marxin/kgraft-analysis-tool/blob/master/README.md > > > in the

RE: [PATCH][GCC][front-end][opt-framework] Update options framework for parameters to properly handle and validate configure time params. [Patch (2/3)]

Hello, On Tue, 24 Jul 2018, tamar.christ...@arm.com wrote: > > * params.c (validate_param): New. > (add_params): Use it. > (set_param_value): Refactor param validation into validate_param. > (diagnostic.h): Include. > * diagnostic.h (diagnostic_ready_p): New. this p